amd/amdgpu/nbio_v6_1.c

0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include "amdgpu.h"
0024 #include "amdgpu_atombios.h"
0025 #include "nbio_v6_1.h"
0026
0027 #include "nbio/nbio_6_1_default.h"
0028 #include "nbio/nbio_6_1_offset.h"
0029 #include "nbio/nbio_6_1_sh_mask.h"
0030 #include "nbio/nbio_6_1_smn.h"
0031 #include "vega10_enum.h"
0032 #include <uapi/linux/kfd_ioctl.h>
0033
0034 #define smnPCIE_LC_CNTL     0x11140280
0035 #define smnPCIE_LC_CNTL3    0x111402d4
0036 #define smnPCIE_LC_CNTL6    0x111402ec
0037 #define smnPCIE_LC_CNTL7    0x111402f0
0038 #define smnNBIF_MGCG_CTRL_LCLK  0x1013a05c
0039 #define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK    0x00001000L
0040 #define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK    0x0000FFFFL
0041 #define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK  0xFFFF0000L
0042 #define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL    0x10123530
0043 #define smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2   0x1014008c
0044 #define smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP   0x10140324
0045 #define smnPSWUSP0_PCIE_LC_CNTL2        0x111402c4
0046 #define smnRCC_BIF_STRAP2   0x10123488
0047 #define smnRCC_BIF_STRAP3   0x1012348c
0048 #define smnRCC_BIF_STRAP5   0x10123494
0049 #define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK         0x0400L
0050 #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK    0x0000FFFFL
0051 #define RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK    0x00004000L
0052 #define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT  0x0
0053 #define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT    0x10
0054 #define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT  0x0
0055
0056 static void nbio_v6_1_remap_hdp_registers(struct amdgpu_device *adev)
0057 {
0058     WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
0059         adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
0060     WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
0061         adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
0062 }
0063
0064 static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
0065 {
0066     u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
0067
0068     tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
0069     tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
0070
0071     return tmp;
0072 }
0073
0074 static void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable)
0075 {
0076     if (enable)
0077         WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
0078                  BIF_FB_EN__FB_READ_EN_MASK |
0079                  BIF_FB_EN__FB_WRITE_EN_MASK);
0080     else
0081         WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
0082 }
0083
0084 static u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev)
0085 {
0086     return RREG32_SOC15(NBIO, 0, mmRCC_PF_0_0_RCC_CONFIG_MEMSIZE);
0087 }
0088
0089 static void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
0090             bool use_doorbell, int doorbell_index, int doorbell_size)
0091 {
0092     u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
0093             SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
0094
0095     u32 doorbell_range = RREG32(reg);
0096
0097     if (use_doorbell) {
0098         doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
0099         doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
0100     } else
0101         doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
0102
0103     WREG32(reg, doorbell_range);
0104
0105 }
0106
0107 static void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev,
0108                            bool enable)
0109 {
0110     WREG32_FIELD15(NBIO, 0, RCC_PF_0_0_RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
0111 }
0112
0113 static void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
0114                             bool enable)
0115 {
0116     u32 tmp = 0;
0117
0118     if (enable) {
0119         tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
0120               REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
0121               REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
0122
0123         WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
0124                  lower_32_bits(adev->doorbell.base));
0125         WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
0126                  upper_32_bits(adev->doorbell.base));
0127     }
0128
0129     WREG32_SOC15(NBIO, 0, mmBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp);
0130 }
0131
0132
0133 static void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev,
0134                     bool use_doorbell, int doorbell_index)
0135 {
0136     u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE);
0137
0138     if (use_doorbell) {
0139         ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
0140         ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
0141                           BIF_IH_DOORBELL_RANGE, SIZE, 6);
0142     } else
0143         ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
0144
0145     WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
0146 }
0147
0148 static void nbio_v6_1_ih_control(struct amdgpu_device *adev)
0149 {
0150     u32 interrupt_cntl;
0151
0152     /* setup interrupt control */
0153     WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
0154     interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
0155     /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
0156      * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
0157      */
0158     interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
0159     /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
0160     interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
0161     WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
0162 }
0163
0164 static void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
0165                                bool enable)
0166 {
0167     uint32_t def, data;
0168
0169     def = data = RREG32_PCIE(smnCPM_CONTROL);
0170     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG)) {
0171         data |= (CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
0172              CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
0173              CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK |
0174              CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
0175              CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
0176              CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
0177              CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
0178     } else {
0179         data &= ~(CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK |
0180               CPM_CONTROL__TXCLK_DYN_GATE_ENABLE_MASK |
0181               CPM_CONTROL__TXCLK_PERM_GATE_ENABLE_MASK |
0182               CPM_CONTROL__TXCLK_LCNT_GATE_ENABLE_MASK |
0183               CPM_CONTROL__TXCLK_REGS_GATE_ENABLE_MASK |
0184               CPM_CONTROL__TXCLK_PRBS_GATE_ENABLE_MASK |
0185               CPM_CONTROL__REFCLK_REGS_GATE_ENABLE_MASK);
0186     }
0187
0188     if (def != data)
0189         WREG32_PCIE(smnCPM_CONTROL, data);
0190 }
0191
0192 static void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
0193                               bool enable)
0194 {
0195     uint32_t def, data;
0196
0197     def = data = RREG32_PCIE(smnPCIE_CNTL2);
0198     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
0199         data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
0200              PCIE_CNTL2__MST_MEM_LS_EN_MASK |
0201              PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
0202     } else {
0203         data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
0204               PCIE_CNTL2__MST_MEM_LS_EN_MASK |
0205               PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
0206     }
0207
0208     if (def != data)
0209         WREG32_PCIE(smnPCIE_CNTL2, data);
0210 }
0211
0212 static void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev,
0213                         u64 *flags)
0214 {
0215     int data;
0216
0217     /* AMD_CG_SUPPORT_BIF_MGCG */
0218     data = RREG32_PCIE(smnCPM_CONTROL);
0219     if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
0220         *flags |= AMD_CG_SUPPORT_BIF_MGCG;
0221
0222     /* AMD_CG_SUPPORT_BIF_LS */
0223     data = RREG32_PCIE(smnPCIE_CNTL2);
0224     if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
0225         *flags |= AMD_CG_SUPPORT_BIF_LS;
0226 }
0227
0228 static u32 nbio_v6_1_get_hdp_flush_req_offset(struct amdgpu_device *adev)
0229 {
0230     return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
0231 }
0232
0233 static u32 nbio_v6_1_get_hdp_flush_done_offset(struct amdgpu_device *adev)
0234 {
0235     return SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
0236 }
0237
0238 static u32 nbio_v6_1_get_pcie_index_offset(struct amdgpu_device *adev)
0239 {
0240     return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
0241 }
0242
0243 static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev)
0244 {
0245     return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
0246 }
0247
0248 const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
0249     .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
0250     .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
0251     .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
0252     .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
0253     .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
0254     .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
0255     .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
0256     .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
0257     .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
0258     .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
0259     .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
0260     .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK
0261 };
0262
0263 static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
0264 {
0265     uint32_t def, data;
0266
0267     def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL);
0268     data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
0269     data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
0270
0271     if (def != data)
0272         WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
0273
0274     def = data = RREG32_PCIE(smnPCIE_CI_CNTL);
0275     data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1);
0276
0277     if (def != data)
0278         WREG32_PCIE(smnPCIE_CI_CNTL, data);
0279
0280     if (amdgpu_sriov_vf(adev))
0281         adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
0282             mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
0283 }
0284
0285 #ifdef CONFIG_PCIEASPM
0286 static void nbio_v6_1_program_ltr(struct amdgpu_device *adev)
0287 {
0288     uint32_t def, data;
0289
0290     WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, 0x75EB);
0291
0292     def = data = RREG32_PCIE(smnRCC_BIF_STRAP2);
0293     data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK;
0294     if (def != data)
0295         WREG32_PCIE(smnRCC_BIF_STRAP2, data);
0296
0297     def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);
0298     data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK;
0299     if (def != data)
0300         WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data);
0301
0302     def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
0303     data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
0304     if (def != data)
0305         WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
0306 }
0307 #endif
0308
0309 static void nbio_v6_1_program_aspm(struct amdgpu_device *adev)
0310 {
0311 #ifdef CONFIG_PCIEASPM
0312     uint32_t def, data;
0313
0314     def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
0315     data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
0316     data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
0317     data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
0318     if (def != data)
0319         WREG32_PCIE(smnPCIE_LC_CNTL, data);
0320
0321     def = data = RREG32_PCIE(smnPCIE_LC_CNTL7);
0322     data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK;
0323     if (def != data)
0324         WREG32_PCIE(smnPCIE_LC_CNTL7, data);
0325
0326     def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
0327     data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK;
0328     if (def != data)
0329         WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data);
0330
0331     def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);
0332     data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
0333     if (def != data)
0334         WREG32_PCIE(smnPCIE_LC_CNTL3, data);
0335
0336     def = data = RREG32_PCIE(smnRCC_BIF_STRAP3);
0337     data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK;
0338     data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK;
0339     if (def != data)
0340         WREG32_PCIE(smnRCC_BIF_STRAP3, data);
0341
0342     def = data = RREG32_PCIE(smnRCC_BIF_STRAP5);
0343     data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK;
0344     if (def != data)
0345         WREG32_PCIE(smnRCC_BIF_STRAP5, data);
0346
0347     def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
0348     data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
0349     if (def != data)
0350         WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
0351
0352     WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001);
0353
0354     def = data = RREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2);
0355     data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK |
0356         PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK;
0357     data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK;
0358     if (def != data)
0359         WREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2, data);
0360
0361     def = data = RREG32_PCIE(smnPCIE_LC_CNTL6);
0362     data |= PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK |
0363         PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK;
0364     if (def != data)
0365         WREG32_PCIE(smnPCIE_LC_CNTL6, data);
0366
0367     /* Don't bother about LTR if LTR is not enabled
0368      * in the path */
0369     if (adev->pdev->ltr_path)
0370         nbio_v6_1_program_ltr(adev);
0371
0372     def = data = RREG32_PCIE(smnRCC_BIF_STRAP3);
0373     data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT;
0374     data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT;
0375     if (def != data)
0376         WREG32_PCIE(smnRCC_BIF_STRAP3, data);
0377
0378     def = data = RREG32_PCIE(smnRCC_BIF_STRAP5);
0379     data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT;
0380     if (def != data)
0381         WREG32_PCIE(smnRCC_BIF_STRAP5, data);
0382
0383     def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
0384     data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
0385     data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
0386     data |= 0x1 << PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT;
0387     if (def != data)
0388         WREG32_PCIE(smnPCIE_LC_CNTL, data);
0389
0390     def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);
0391     data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
0392     if (def != data)
0393         WREG32_PCIE(smnPCIE_LC_CNTL3, data);
0394 #endif
0395 }
0396
0397 const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {
0398     .get_hdp_flush_req_offset = nbio_v6_1_get_hdp_flush_req_offset,
0399     .get_hdp_flush_done_offset = nbio_v6_1_get_hdp_flush_done_offset,
0400     .get_pcie_index_offset = nbio_v6_1_get_pcie_index_offset,
0401     .get_pcie_data_offset = nbio_v6_1_get_pcie_data_offset,
0402     .get_rev_id = nbio_v6_1_get_rev_id,
0403     .mc_access_enable = nbio_v6_1_mc_access_enable,
0404     .get_memsize = nbio_v6_1_get_memsize,
0405     .sdma_doorbell_range = nbio_v6_1_sdma_doorbell_range,
0406     .enable_doorbell_aperture = nbio_v6_1_enable_doorbell_aperture,
0407     .enable_doorbell_selfring_aperture = nbio_v6_1_enable_doorbell_selfring_aperture,
0408     .ih_doorbell_range = nbio_v6_1_ih_doorbell_range,
0409     .update_medium_grain_clock_gating = nbio_v6_1_update_medium_grain_clock_gating,
0410     .update_medium_grain_light_sleep = nbio_v6_1_update_medium_grain_light_sleep,
0411     .get_clockgating_state = nbio_v6_1_get_clockgating_state,
0412     .ih_control = nbio_v6_1_ih_control,
0413     .init_registers = nbio_v6_1_init_registers,
0414     .remap_hdp_registers = nbio_v6_1_remap_hdp_registers,
0415     .program_aspm =  nbio_v6_1_program_aspm,
0416 };