amd/amdgpu/mxgpu_vi.h

0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  */
0022
0023 #ifndef __MXGPU_VI_H__
0024 #define __MXGPU_VI_H__
0025
0026 #define VI_MAILBOX_TIMEDOUT 12000
0027 #define VI_MAILBOX_RESET_TIME   12
0028
0029 /* VI mailbox messages request */
0030 enum idh_request {
0031     IDH_REQ_GPU_INIT_ACCESS = 1,
0032     IDH_REL_GPU_INIT_ACCESS,
0033     IDH_REQ_GPU_FINI_ACCESS,
0034     IDH_REL_GPU_FINI_ACCESS,
0035     IDH_REQ_GPU_RESET_ACCESS,
0036
0037     IDH_LOG_VF_ERROR       = 200,
0038 };
0039
0040 /* VI mailbox messages data */
0041 enum idh_event {
0042     IDH_CLR_MSG_BUF = 0,
0043     IDH_READY_TO_ACCESS_GPU,
0044     IDH_FLR_NOTIFICATION,
0045     IDH_FLR_NOTIFICATION_CMPL,
0046
0047     IDH_TEXT_MESSAGE = 255
0048 };
0049
0050 extern const struct amdgpu_virt_ops xgpu_vi_virt_ops;
0051
0052 void xgpu_vi_init_golden_registers(struct amdgpu_device *adev);
0053 void xgpu_vi_mailbox_set_irq_funcs(struct amdgpu_device *adev);
0054 int xgpu_vi_mailbox_add_irq_id(struct amdgpu_device *adev);
0055 int xgpu_vi_mailbox_get_irq(struct amdgpu_device *adev);
0056 void xgpu_vi_mailbox_put_irq(struct amdgpu_device *adev);
0057
0058 #endif