amd/amdgpu/mxgpu_ai.h

0001 /*
0002  * Copyright 2014 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef __MXGPU_AI_H__
0025 #define __MXGPU_AI_H__
0026
0027 #define AI_MAILBOX_POLL_ACK_TIMEDOUT    500
0028 #define AI_MAILBOX_POLL_MSG_TIMEDOUT    6000
0029 #define AI_MAILBOX_POLL_FLR_TIMEDOUT    10000
0030 #define AI_MAILBOX_POLL_MSG_REP_MAX 11
0031
0032 enum idh_request {
0033     IDH_REQ_GPU_INIT_ACCESS = 1,
0034     IDH_REL_GPU_INIT_ACCESS,
0035     IDH_REQ_GPU_FINI_ACCESS,
0036     IDH_REL_GPU_FINI_ACCESS,
0037     IDH_REQ_GPU_RESET_ACCESS,
0038     IDH_REQ_GPU_INIT_DATA,
0039
0040     IDH_LOG_VF_ERROR       = 200,
0041     IDH_READY_TO_RESET  = 201,
0042 };
0043
0044 enum idh_event {
0045     IDH_CLR_MSG_BUF = 0,
0046     IDH_READY_TO_ACCESS_GPU,
0047     IDH_FLR_NOTIFICATION,
0048     IDH_FLR_NOTIFICATION_CMPL,
0049     IDH_SUCCESS,
0050     IDH_FAIL,
0051     IDH_QUERY_ALIVE,
0052     IDH_REQ_GPU_INIT_DATA_READY,
0053
0054     IDH_TEXT_MESSAGE = 255,
0055 };
0056
0057 extern const struct amdgpu_virt_ops xgpu_ai_virt_ops;
0058
0059 void xgpu_ai_mailbox_set_irq_funcs(struct amdgpu_device *adev);
0060 int xgpu_ai_mailbox_add_irq_id(struct amdgpu_device *adev);
0061 int xgpu_ai_mailbox_get_irq(struct amdgpu_device *adev);
0062 void xgpu_ai_mailbox_put_irq(struct amdgpu_device *adev);
0063
0064 #define AI_MAIBOX_CONTROL_TRN_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4
0065 #define AI_MAIBOX_CONTROL_RCV_OFFSET_BYTE SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_CONTROL) * 4 + 1
0066
0067 #endif