amd/amdgpu/mmsch_v3_0.h

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef __MMSCH_V3_0_H__
0025 #define __MMSCH_V3_0_H__
0026
0027 #include "amdgpu_vcn.h"
0028
0029 #define MMSCH_VERSION_MAJOR 3
0030 #define MMSCH_VERSION_MINOR 0
0031 #define MMSCH_VERSION   (MMSCH_VERSION_MAJOR << 16 | MMSCH_VERSION_MINOR)
0032
0033 enum mmsch_v3_0_command_type {
0034     MMSCH_COMMAND__DIRECT_REG_WRITE = 0,
0035     MMSCH_COMMAND__DIRECT_REG_POLLING = 2,
0036     MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE = 3,
0037     MMSCH_COMMAND__INDIRECT_REG_WRITE = 8,
0038     MMSCH_COMMAND__END = 0xf
0039 };
0040
0041 struct mmsch_v3_0_table_info {
0042     uint32_t init_status;
0043     uint32_t table_offset;
0044     uint32_t table_size;
0045 };
0046
0047 struct mmsch_v3_0_init_header {
0048     uint32_t version;
0049     uint32_t total_size;
0050     struct mmsch_v3_0_table_info inst[AMDGPU_MAX_VCN_INSTANCES];
0051 };
0052
0053 struct mmsch_v3_0_cmd_direct_reg_header {
0054     uint32_t reg_offset   : 28;
0055     uint32_t command_type : 4;
0056 };
0057
0058 struct mmsch_v3_0_cmd_indirect_reg_header {
0059     uint32_t reg_offset    : 20;
0060     uint32_t reg_idx_space : 8;
0061     uint32_t command_type  : 4;
0062 };
0063
0064 struct mmsch_v3_0_cmd_direct_write {
0065     struct mmsch_v3_0_cmd_direct_reg_header cmd_header;
0066     uint32_t reg_value;
0067 };
0068
0069 struct mmsch_v3_0_cmd_direct_read_modify_write {
0070     struct mmsch_v3_0_cmd_direct_reg_header cmd_header;
0071     uint32_t write_data;
0072     uint32_t mask_value;
0073 };
0074
0075 struct mmsch_v3_0_cmd_direct_polling {
0076     struct mmsch_v3_0_cmd_direct_reg_header cmd_header;
0077     uint32_t mask_value;
0078     uint32_t wait_value;
0079 };
0080
0081 struct mmsch_v3_0_cmd_end {
0082     struct mmsch_v3_0_cmd_direct_reg_header cmd_header;
0083 };
0084
0085 struct mmsch_v3_0_cmd_indirect_write {
0086     struct mmsch_v3_0_cmd_indirect_reg_header cmd_header;
0087     uint32_t reg_value;
0088 };
0089
0090 #define MMSCH_V3_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \
0091     size = sizeof(struct mmsch_v3_0_cmd_direct_read_modify_write); \
0092     size_dw = size / 4; \
0093     direct_rd_mod_wt.cmd_header.reg_offset = reg; \
0094     direct_rd_mod_wt.mask_value = mask; \
0095     direct_rd_mod_wt.write_data = data; \
0096     memcpy((void *)table_loc, &direct_rd_mod_wt, size); \
0097     table_loc += size_dw; \
0098     table_size += size_dw; \
0099 }
0100
0101 #define MMSCH_V3_0_INSERT_DIRECT_WT(reg, value) { \
0102     size = sizeof(struct mmsch_v3_0_cmd_direct_write); \
0103     size_dw = size / 4; \
0104     direct_wt.cmd_header.reg_offset = reg; \
0105     direct_wt.reg_value = value; \
0106     memcpy((void *)table_loc, &direct_wt, size); \
0107     table_loc += size_dw; \
0108     table_size += size_dw; \
0109 }
0110
0111 #define MMSCH_V3_0_INSERT_DIRECT_POLL(reg, mask, wait) { \
0112     size = sizeof(struct mmsch_v3_0_cmd_direct_polling); \
0113     size_dw = size / 4; \
0114     direct_poll.cmd_header.reg_offset = reg; \
0115     direct_poll.mask_value = mask; \
0116     direct_poll.wait_value = wait; \
0117     memcpy((void *)table_loc, &direct_poll, size); \
0118     table_loc += size_dw; \
0119     table_size += size_dw; \
0120 }
0121
0122 #define MMSCH_V3_0_INSERT_END() { \
0123     size = sizeof(struct mmsch_v3_0_cmd_end); \
0124     size_dw = size / 4; \
0125     memcpy((void *)table_loc, &end, size); \
0126     table_loc += size_dw; \
0127     table_size += size_dw; \
0128 }
0129
0130 #endif