amd/amdgpu/mmsch_v1_0.h

0001 /*
0002  * Copyright 2017 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef __MMSCH_V1_0_H__
0025 #define __MMSCH_V1_0_H__
0026
0027 #define MMSCH_VERSION   0x1
0028
0029 enum mmsch_v1_0_command_type {
0030     MMSCH_COMMAND__DIRECT_REG_WRITE = 0,
0031     MMSCH_COMMAND__DIRECT_REG_POLLING = 2,
0032     MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE = 3,
0033     MMSCH_COMMAND__INDIRECT_REG_WRITE = 8,
0034     MMSCH_COMMAND__END = 0xf
0035 };
0036
0037 struct mmsch_v1_0_init_header {
0038     uint32_t version;
0039     uint32_t header_size;
0040     uint32_t vce_init_status;
0041     uint32_t uvd_init_status;
0042     uint32_t vce_table_offset;
0043     uint32_t vce_table_size;
0044     uint32_t uvd_table_offset;
0045     uint32_t uvd_table_size;
0046 };
0047
0048 struct mmsch_vf_eng_init_header {
0049     uint32_t init_status;
0050     uint32_t table_offset;
0051     uint32_t table_size;
0052 };
0053
0054 struct mmsch_v1_1_init_header {
0055     uint32_t version;
0056     uint32_t total_size;
0057     struct mmsch_vf_eng_init_header eng[2];
0058 };
0059
0060 struct mmsch_v1_0_cmd_direct_reg_header {
0061     uint32_t reg_offset   : 28;
0062     uint32_t command_type : 4;
0063 };
0064
0065 struct mmsch_v1_0_cmd_indirect_reg_header {
0066     uint32_t reg_offset    : 20;
0067     uint32_t reg_idx_space : 8;
0068     uint32_t command_type  : 4;
0069 };
0070
0071 struct mmsch_v1_0_cmd_direct_write {
0072     struct mmsch_v1_0_cmd_direct_reg_header cmd_header;
0073     uint32_t reg_value;
0074 };
0075
0076 struct mmsch_v1_0_cmd_direct_read_modify_write {
0077     struct mmsch_v1_0_cmd_direct_reg_header cmd_header;
0078     uint32_t write_data;
0079     uint32_t mask_value;
0080 };
0081
0082 struct mmsch_v1_0_cmd_direct_polling {
0083     struct mmsch_v1_0_cmd_direct_reg_header cmd_header;
0084     uint32_t mask_value;
0085     uint32_t wait_value;
0086 };
0087
0088 struct mmsch_v1_0_cmd_end {
0089     struct mmsch_v1_0_cmd_direct_reg_header cmd_header;
0090 };
0091
0092 struct mmsch_v1_0_cmd_indirect_write {
0093     struct mmsch_v1_0_cmd_indirect_reg_header cmd_header;
0094     uint32_t reg_value;
0095 };
0096
0097 static inline void mmsch_v1_0_insert_direct_wt(struct mmsch_v1_0_cmd_direct_write *direct_wt,
0098                            uint32_t *init_table,
0099                            uint32_t reg_offset,
0100                            uint32_t value)
0101 {
0102     direct_wt->cmd_header.reg_offset = reg_offset;
0103     direct_wt->reg_value = value;
0104     memcpy((void *)init_table, direct_wt, sizeof(struct mmsch_v1_0_cmd_direct_write));
0105 }
0106
0107 static inline void mmsch_v1_0_insert_direct_rd_mod_wt(struct mmsch_v1_0_cmd_direct_read_modify_write *direct_rd_mod_wt,
0108                               uint32_t *init_table,
0109                               uint32_t reg_offset,
0110                               uint32_t mask, uint32_t data)
0111 {
0112     direct_rd_mod_wt->cmd_header.reg_offset = reg_offset;
0113     direct_rd_mod_wt->mask_value = mask;
0114     direct_rd_mod_wt->write_data = data;
0115     memcpy((void *)init_table, direct_rd_mod_wt,
0116            sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write));
0117 }
0118
0119 static inline void mmsch_v1_0_insert_direct_poll(struct mmsch_v1_0_cmd_direct_polling *direct_poll,
0120                          uint32_t *init_table,
0121                          uint32_t reg_offset,
0122                          uint32_t mask, uint32_t wait)
0123 {
0124     direct_poll->cmd_header.reg_offset = reg_offset;
0125     direct_poll->mask_value = mask;
0126     direct_poll->wait_value = wait;
0127     memcpy((void *)init_table, direct_poll, sizeof(struct mmsch_v1_0_cmd_direct_polling));
0128 }
0129
0130 #define MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \
0131     mmsch_v1_0_insert_direct_rd_mod_wt(&direct_rd_mod_wt, \
0132                        init_table, (reg), \
0133                        (mask), (data)); \
0134     init_table += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write)/4; \
0135     table_size += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write)/4; \
0136 }
0137
0138 #define MMSCH_V1_0_INSERT_DIRECT_WT(reg, value) { \
0139     mmsch_v1_0_insert_direct_wt(&direct_wt, \
0140                     init_table, (reg), \
0141                     (value)); \
0142     init_table += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; \
0143     table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; \
0144 }
0145
0146 #define MMSCH_V1_0_INSERT_DIRECT_POLL(reg, mask, wait) { \
0147     mmsch_v1_0_insert_direct_poll(&direct_poll, \
0148                       init_table, (reg), \
0149                       (mask), (wait)); \
0150     init_table += sizeof(struct mmsch_v1_0_cmd_direct_polling)/4; \
0151     table_size += sizeof(struct mmsch_v1_0_cmd_direct_polling)/4; \
0152 }
0153
0154 #endif