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0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include "amdgpu.h"
0024 #include "amdgpu_ras.h"
0025 #include "mmhub_v9_4.h"
0026 
0027 #include "mmhub/mmhub_9_4_1_offset.h"
0028 #include "mmhub/mmhub_9_4_1_sh_mask.h"
0029 #include "mmhub/mmhub_9_4_1_default.h"
0030 #include "athub/athub_1_0_offset.h"
0031 #include "athub/athub_1_0_sh_mask.h"
0032 #include "vega10_enum.h"
0033 #include "soc15.h"
0034 #include "soc15_common.h"
0035 
0036 #define MMHUB_NUM_INSTANCES         2
0037 #define MMHUB_INSTANCE_REGISTER_OFFSET      0x3000
0038 
0039 static u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev)
0040 {
0041     /* The base should be same b/t 2 mmhubs on Acrturus. Read one here. */
0042     u64 base = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE);
0043     u64 top = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP);
0044 
0045     base &= VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
0046     base <<= 24;
0047 
0048     top &= VMSHAREDVC0_MC_VM_FB_LOCATION_TOP__FB_TOP_MASK;
0049     top <<= 24;
0050 
0051     adev->gmc.fb_start = base;
0052     adev->gmc.fb_end = top;
0053 
0054     return base;
0055 }
0056 
0057 static void mmhub_v9_4_setup_hubid_vm_pt_regs(struct amdgpu_device *adev, int hubid,
0058                 uint32_t vmid, uint64_t value)
0059 {
0060     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0061 
0062     WREG32_SOC15_OFFSET(MMHUB, 0,
0063                 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
0064                 hub->ctx_addr_distance * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
0065                 lower_32_bits(value));
0066 
0067     WREG32_SOC15_OFFSET(MMHUB, 0,
0068                 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
0069                 hub->ctx_addr_distance * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
0070                 upper_32_bits(value));
0071 
0072 }
0073 
0074 static void mmhub_v9_4_init_gart_aperture_regs(struct amdgpu_device *adev,
0075                            int hubid)
0076 {
0077     uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
0078 
0079     mmhub_v9_4_setup_hubid_vm_pt_regs(adev, hubid, 0, pt_base);
0080 
0081     WREG32_SOC15_OFFSET(MMHUB, 0,
0082                 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
0083                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
0084                 (u32)(adev->gmc.gart_start >> 12));
0085     WREG32_SOC15_OFFSET(MMHUB, 0,
0086                 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
0087                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
0088                 (u32)(adev->gmc.gart_start >> 44));
0089 
0090     WREG32_SOC15_OFFSET(MMHUB, 0,
0091                 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
0092                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
0093                 (u32)(adev->gmc.gart_end >> 12));
0094     WREG32_SOC15_OFFSET(MMHUB, 0,
0095                 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
0096                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
0097                 (u32)(adev->gmc.gart_end >> 44));
0098 }
0099 
0100 static void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
0101                 uint64_t page_table_base)
0102 {
0103     int i;
0104 
0105     for (i = 0; i < MMHUB_NUM_INSTANCES; i++)
0106         mmhub_v9_4_setup_hubid_vm_pt_regs(adev, i, vmid,
0107                 page_table_base);
0108 }
0109 
0110 static void mmhub_v9_4_init_system_aperture_regs(struct amdgpu_device *adev,
0111                              int hubid)
0112 {
0113     uint64_t value;
0114     uint32_t tmp;
0115 
0116     /* Program the AGP BAR */
0117     WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BASE,
0118                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
0119                 0);
0120     WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_TOP,
0121                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
0122                 adev->gmc.agp_end >> 24);
0123     WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BOT,
0124                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
0125                 adev->gmc.agp_start >> 24);
0126 
0127     if (!amdgpu_sriov_vf(adev)) {
0128         /* Program the system aperture low logical page number. */
0129         WREG32_SOC15_OFFSET(
0130             MMHUB, 0, mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR,
0131             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
0132             min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
0133         WREG32_SOC15_OFFSET(
0134             MMHUB, 0, mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
0135             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
0136             max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
0137 
0138         /* Set default page address. */
0139         value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
0140         WREG32_SOC15_OFFSET(
0141             MMHUB, 0,
0142             mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
0143             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
0144             (u32)(value >> 12));
0145         WREG32_SOC15_OFFSET(
0146             MMHUB, 0,
0147             mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
0148             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
0149             (u32)(value >> 44));
0150 
0151         /* Program "protection fault". */
0152         WREG32_SOC15_OFFSET(
0153             MMHUB, 0,
0154             mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
0155             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
0156             (u32)(adev->dummy_page_addr >> 12));
0157         WREG32_SOC15_OFFSET(
0158             MMHUB, 0,
0159             mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
0160             hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
0161             (u32)((u64)adev->dummy_page_addr >> 44));
0162 
0163         tmp = RREG32_SOC15_OFFSET(
0164             MMHUB, 0, mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
0165             hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
0166         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
0167                     ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
0168         WREG32_SOC15_OFFSET(MMHUB, 0,
0169                     mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
0170                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
0171                     tmp);
0172     }
0173 }
0174 
0175 static void mmhub_v9_4_init_tlb_regs(struct amdgpu_device *adev, int hubid)
0176 {
0177     uint32_t tmp;
0178 
0179     /* Setup TLB control */
0180     tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
0181                mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
0182                hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
0183 
0184     tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
0185                 ENABLE_L1_TLB, 1);
0186     tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
0187                 SYSTEM_ACCESS_MODE, 3);
0188     tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
0189                 ENABLE_ADVANCED_DRIVER_MODEL, 1);
0190     tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
0191                 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
0192     tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
0193                 MTYPE, MTYPE_UC);/* XXX for emulation. */
0194     tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
0195                 ATC_EN, 1);
0196 
0197     WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
0198                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
0199 }
0200 
0201 static void mmhub_v9_4_init_cache_regs(struct amdgpu_device *adev, int hubid)
0202 {
0203     uint32_t tmp;
0204 
0205     /* Setup L2 cache */
0206     tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
0207                   hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
0208     tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
0209                 ENABLE_L2_CACHE, 1);
0210     tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
0211                 ENABLE_L2_FRAGMENT_PROCESSING, 1);
0212     /* XXX for emulation, Refer to closed source code.*/
0213     tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
0214                 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
0215     tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
0216                 PDE_FAULT_CLASSIFICATION, 0);
0217     tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
0218                 CONTEXT1_IDENTITY_ACCESS_MODE, 1);
0219     tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
0220                 IDENTITY_MODE_FRAGMENT_SIZE, 0);
0221     WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
0222              hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
0223 
0224     tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2,
0225                   hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
0226     tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,
0227                 INVALIDATE_ALL_L1_TLBS, 1);
0228     tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,
0229                 INVALIDATE_L2_CACHE, 1);
0230     WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2,
0231                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
0232 
0233     tmp = mmVML2PF0_VM_L2_CNTL3_DEFAULT;
0234     if (adev->gmc.translate_further) {
0235         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 12);
0236         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
0237                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
0238     } else {
0239         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 9);
0240         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
0241                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
0242     }
0243     WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3,
0244                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
0245 
0246     tmp = mmVML2PF0_VM_L2_CNTL4_DEFAULT;
0247     tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,
0248                 VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
0249     tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,
0250                 VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
0251     WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL4,
0252                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
0253 }
0254 
0255 static void mmhub_v9_4_enable_system_domain(struct amdgpu_device *adev,
0256                         int hubid)
0257 {
0258     uint32_t tmp;
0259 
0260     tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL,
0261                   hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
0262     tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
0263     tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
0264     tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL,
0265                 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
0266     WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL,
0267                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
0268 }
0269 
0270 static void mmhub_v9_4_disable_identity_aperture(struct amdgpu_device *adev,
0271                          int hubid)
0272 {
0273     WREG32_SOC15_OFFSET(MMHUB, 0,
0274             mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
0275             hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0XFFFFFFFF);
0276     WREG32_SOC15_OFFSET(MMHUB, 0,
0277             mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
0278             hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0x0000000F);
0279 
0280     WREG32_SOC15_OFFSET(MMHUB, 0,
0281             mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
0282             hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
0283     WREG32_SOC15_OFFSET(MMHUB, 0,
0284             mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
0285             hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
0286 
0287     WREG32_SOC15_OFFSET(MMHUB, 0,
0288             mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
0289             hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
0290     WREG32_SOC15_OFFSET(MMHUB, 0,
0291             mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
0292             hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
0293 }
0294 
0295 static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid)
0296 {
0297     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0298     unsigned int num_level, block_size;
0299     uint32_t tmp;
0300     int i;
0301 
0302     num_level = adev->vm_manager.num_level;
0303     block_size = adev->vm_manager.block_size;
0304     if (adev->gmc.translate_further)
0305         num_level -= 1;
0306     else
0307         block_size -= 9;
0308 
0309     for (i = 0; i <= 14; i++) {
0310         tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
0311                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i);
0312         tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
0313                     ENABLE_CONTEXT, 1);
0314         tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
0315                     PAGE_TABLE_DEPTH,
0316                     num_level);
0317         tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
0318                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0319         tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
0320                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
0321                     1);
0322         tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
0323                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0324         tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
0325                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0326         tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
0327                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0328         tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
0329                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0330         tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
0331                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0332         tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
0333                     PAGE_TABLE_BLOCK_SIZE,
0334                     block_size);
0335         /* Send no-retry XNACK on fault to suppress VM fault storm. */
0336         tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
0337                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
0338                     !adev->gmc.noretry);
0339         WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
0340                     hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
0341                     i * hub->ctx_distance, tmp);
0342         WREG32_SOC15_OFFSET(MMHUB, 0,
0343                 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
0344                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
0345                 i * hub->ctx_addr_distance, 0);
0346         WREG32_SOC15_OFFSET(MMHUB, 0,
0347                 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
0348                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
0349                 i * hub->ctx_addr_distance, 0);
0350         WREG32_SOC15_OFFSET(MMHUB, 0,
0351                 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
0352                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
0353                 i * hub->ctx_addr_distance,
0354                 lower_32_bits(adev->vm_manager.max_pfn - 1));
0355         WREG32_SOC15_OFFSET(MMHUB, 0,
0356                 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
0357                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
0358                 i * hub->ctx_addr_distance,
0359                 upper_32_bits(adev->vm_manager.max_pfn - 1));
0360     }
0361 }
0362 
0363 static void mmhub_v9_4_program_invalidation(struct amdgpu_device *adev,
0364                         int hubid)
0365 {
0366     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0367     unsigned i;
0368 
0369     for (i = 0; i < 18; ++i) {
0370         WREG32_SOC15_OFFSET(MMHUB, 0,
0371                 mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
0372                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
0373                 i * hub->eng_addr_distance,
0374                 0xffffffff);
0375         WREG32_SOC15_OFFSET(MMHUB, 0,
0376                 mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
0377                 hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
0378                 i * hub->eng_addr_distance,
0379                 0x1f);
0380     }
0381 }
0382 
0383 static int mmhub_v9_4_gart_enable(struct amdgpu_device *adev)
0384 {
0385     int i;
0386 
0387     for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
0388         /* GART Enable. */
0389         mmhub_v9_4_init_gart_aperture_regs(adev, i);
0390         mmhub_v9_4_init_system_aperture_regs(adev, i);
0391         mmhub_v9_4_init_tlb_regs(adev, i);
0392         if (!amdgpu_sriov_vf(adev))
0393             mmhub_v9_4_init_cache_regs(adev, i);
0394 
0395         mmhub_v9_4_enable_system_domain(adev, i);
0396         if (!amdgpu_sriov_vf(adev))
0397             mmhub_v9_4_disable_identity_aperture(adev, i);
0398         mmhub_v9_4_setup_vmid_config(adev, i);
0399         mmhub_v9_4_program_invalidation(adev, i);
0400     }
0401 
0402     return 0;
0403 }
0404 
0405 static void mmhub_v9_4_gart_disable(struct amdgpu_device *adev)
0406 {
0407     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0408     u32 tmp;
0409     u32 i, j;
0410 
0411     for (j = 0; j < MMHUB_NUM_INSTANCES; j++) {
0412         /* Disable all tables */
0413         for (i = 0; i < AMDGPU_NUM_VMID; i++)
0414             WREG32_SOC15_OFFSET(MMHUB, 0,
0415                         mmVML2VC0_VM_CONTEXT0_CNTL,
0416                         j * MMHUB_INSTANCE_REGISTER_OFFSET +
0417                         i * hub->ctx_distance, 0);
0418 
0419         /* Setup TLB control */
0420         tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
0421                    mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
0422                    j * MMHUB_INSTANCE_REGISTER_OFFSET);
0423         tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
0424                     ENABLE_L1_TLB, 0);
0425         tmp = REG_SET_FIELD(tmp,
0426                     VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
0427                     ENABLE_ADVANCED_DRIVER_MODEL, 0);
0428         WREG32_SOC15_OFFSET(MMHUB, 0,
0429                     mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
0430                     j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
0431 
0432         /* Setup L2 cache */
0433         tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
0434                       j * MMHUB_INSTANCE_REGISTER_OFFSET);
0435         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
0436                     ENABLE_L2_CACHE, 0);
0437         WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
0438                     j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
0439         WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3,
0440                     j * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
0441     }
0442 }
0443 
0444 /**
0445  * mmhub_v9_4_set_fault_enable_default - update GART/VM fault handling
0446  *
0447  * @adev: amdgpu_device pointer
0448  * @value: true redirects VM faults to the default page
0449  */
0450 static void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev, bool value)
0451 {
0452     u32 tmp;
0453     int i;
0454 
0455     for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
0456         tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
0457                       mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
0458                       i * MMHUB_INSTANCE_REGISTER_OFFSET);
0459         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
0460                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT,
0461                     value);
0462         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
0463                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT,
0464                     value);
0465         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
0466                     PDE1_PROTECTION_FAULT_ENABLE_DEFAULT,
0467                     value);
0468         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
0469                     PDE2_PROTECTION_FAULT_ENABLE_DEFAULT,
0470                     value);
0471         tmp = REG_SET_FIELD(tmp,
0472                 VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
0473                 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
0474                 value);
0475         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
0476                     NACK_PROTECTION_FAULT_ENABLE_DEFAULT,
0477                     value);
0478         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
0479                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
0480                     value);
0481         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
0482                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT,
0483                     value);
0484         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
0485                     READ_PROTECTION_FAULT_ENABLE_DEFAULT,
0486                     value);
0487         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
0488                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT,
0489                     value);
0490         tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
0491                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT,
0492                     value);
0493         if (!value) {
0494             tmp = REG_SET_FIELD(tmp,
0495                         VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
0496                         CRASH_ON_NO_RETRY_FAULT, 1);
0497             tmp = REG_SET_FIELD(tmp,
0498                         VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
0499                         CRASH_ON_RETRY_FAULT, 1);
0500         }
0501 
0502         WREG32_SOC15_OFFSET(MMHUB, 0,
0503                     mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
0504                     i * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
0505     }
0506 }
0507 
0508 static void mmhub_v9_4_init(struct amdgpu_device *adev)
0509 {
0510     struct amdgpu_vmhub *hub[MMHUB_NUM_INSTANCES] =
0511         {&adev->vmhub[AMDGPU_MMHUB_0], &adev->vmhub[AMDGPU_MMHUB_1]};
0512     int i;
0513 
0514     for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
0515         hub[i]->ctx0_ptb_addr_lo32 =
0516             SOC15_REG_OFFSET(MMHUB, 0,
0517                 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) +
0518                 i * MMHUB_INSTANCE_REGISTER_OFFSET;
0519         hub[i]->ctx0_ptb_addr_hi32 =
0520             SOC15_REG_OFFSET(MMHUB, 0,
0521                 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) +
0522                 i * MMHUB_INSTANCE_REGISTER_OFFSET;
0523         hub[i]->vm_inv_eng0_sem =
0524             SOC15_REG_OFFSET(MMHUB, 0,
0525                      mmVML2VC0_VM_INVALIDATE_ENG0_SEM) +
0526                      i * MMHUB_INSTANCE_REGISTER_OFFSET;
0527         hub[i]->vm_inv_eng0_req =
0528             SOC15_REG_OFFSET(MMHUB, 0,
0529                      mmVML2VC0_VM_INVALIDATE_ENG0_REQ) +
0530                      i * MMHUB_INSTANCE_REGISTER_OFFSET;
0531         hub[i]->vm_inv_eng0_ack =
0532             SOC15_REG_OFFSET(MMHUB, 0,
0533                      mmVML2VC0_VM_INVALIDATE_ENG0_ACK) +
0534                      i * MMHUB_INSTANCE_REGISTER_OFFSET;
0535         hub[i]->vm_context0_cntl =
0536             SOC15_REG_OFFSET(MMHUB, 0,
0537                      mmVML2VC0_VM_CONTEXT0_CNTL) +
0538                      i * MMHUB_INSTANCE_REGISTER_OFFSET;
0539         hub[i]->vm_l2_pro_fault_status =
0540             SOC15_REG_OFFSET(MMHUB, 0,
0541                     mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS) +
0542                     i * MMHUB_INSTANCE_REGISTER_OFFSET;
0543         hub[i]->vm_l2_pro_fault_cntl =
0544             SOC15_REG_OFFSET(MMHUB, 0,
0545                     mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL) +
0546                     i * MMHUB_INSTANCE_REGISTER_OFFSET;
0547 
0548         hub[i]->ctx_distance = mmVML2VC0_VM_CONTEXT1_CNTL -
0549             mmVML2VC0_VM_CONTEXT0_CNTL;
0550         hub[i]->ctx_addr_distance = mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
0551             mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
0552         hub[i]->eng_distance = mmVML2VC0_VM_INVALIDATE_ENG1_REQ -
0553             mmVML2VC0_VM_INVALIDATE_ENG0_REQ;
0554         hub[i]->eng_addr_distance = mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
0555             mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
0556     }
0557 }
0558 
0559 static void mmhub_v9_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
0560                             bool enable)
0561 {
0562     uint32_t def, data, def1, data1;
0563     int i, j;
0564     int dist = mmDAGB1_CNTL_MISC2 - mmDAGB0_CNTL_MISC2;
0565 
0566     for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
0567         def = data = RREG32_SOC15_OFFSET(MMHUB, 0,
0568                     mmATCL2_0_ATC_L2_MISC_CG,
0569                     i * MMHUB_INSTANCE_REGISTER_OFFSET);
0570 
0571         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
0572             data |= ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK;
0573         else
0574             data &= ~ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK;
0575 
0576         if (def != data)
0577             WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
0578                 i * MMHUB_INSTANCE_REGISTER_OFFSET, data);
0579 
0580         for (j = 0; j < 5; j++) {
0581             def1 = data1 = RREG32_SOC15_OFFSET(MMHUB, 0,
0582                     mmDAGB0_CNTL_MISC2,
0583                     i * MMHUB_INSTANCE_REGISTER_OFFSET +
0584                     j * dist);
0585             if (enable &&
0586                 (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
0587                 data1 &=
0588                     ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
0589                     DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
0590                     DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
0591                     DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
0592                     DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
0593                     DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
0594             } else {
0595                 data1 |=
0596                     (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
0597                     DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
0598                     DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
0599                     DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
0600                     DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
0601                     DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
0602             }
0603 
0604             if (def1 != data1)
0605                 WREG32_SOC15_OFFSET(MMHUB, 0,
0606                     mmDAGB0_CNTL_MISC2,
0607                     i * MMHUB_INSTANCE_REGISTER_OFFSET +
0608                     j * dist, data1);
0609 
0610             if (i == 1 && j == 3)
0611                 break;
0612         }
0613     }
0614 }
0615 
0616 static void mmhub_v9_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
0617                                bool enable)
0618 {
0619     uint32_t def, data;
0620     int i;
0621 
0622     for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
0623         def = data = RREG32_SOC15_OFFSET(MMHUB, 0,
0624                     mmATCL2_0_ATC_L2_MISC_CG,
0625                     i * MMHUB_INSTANCE_REGISTER_OFFSET);
0626 
0627         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
0628             data |= ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
0629         else
0630             data &= ~ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
0631 
0632         if (def != data)
0633             WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
0634                 i * MMHUB_INSTANCE_REGISTER_OFFSET, data);
0635     }
0636 }
0637 
0638 static int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
0639                    enum amd_clockgating_state state)
0640 {
0641     if (amdgpu_sriov_vf(adev))
0642         return 0;
0643 
0644     switch (adev->asic_type) {
0645     case CHIP_ARCTURUS:
0646         mmhub_v9_4_update_medium_grain_clock_gating(adev,
0647                 state == AMD_CG_STATE_GATE);
0648         mmhub_v9_4_update_medium_grain_light_sleep(adev,
0649                 state == AMD_CG_STATE_GATE);
0650         break;
0651     default:
0652         break;
0653     }
0654 
0655     return 0;
0656 }
0657 
0658 static void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u64 *flags)
0659 {
0660     int data, data1;
0661 
0662     if (amdgpu_sriov_vf(adev))
0663         *flags = 0;
0664 
0665     /* AMD_CG_SUPPORT_MC_MGCG */
0666     data = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
0667 
0668     data1 = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
0669 
0670     if ((data & ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK) &&
0671         !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
0672                DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
0673                DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
0674                DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
0675                DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
0676                DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
0677         *flags |= AMD_CG_SUPPORT_MC_MGCG;
0678 
0679     /* AMD_CG_SUPPORT_MC_LS */
0680     if (data & ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
0681         *flags |= AMD_CG_SUPPORT_MC_LS;
0682 }
0683 
0684 static const struct soc15_ras_field_entry mmhub_v9_4_ras_fields[] = {
0685     /* MMHUB Range 0 */
0686     { "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
0687     SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
0688     SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
0689     },
0690     { "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
0691     SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
0692     SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
0693     },
0694     { "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
0695     SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
0696     SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
0697     },
0698     { "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
0699     SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
0700     SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_DED_COUNT),
0701     },
0702     { "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
0703     SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
0704     SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_DED_COUNT),
0705     },
0706     { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
0707     SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
0708     0, 0,
0709     },
0710     { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
0711     SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
0712     0, 0,
0713     },
0714     { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
0715     SOC15_REG_FIELD(MMEA0_EDC_CNT, IORD_CMDMEM_SED_COUNT),
0716     0, 0,
0717     },
0718     { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
0719     SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
0720     0, 0,
0721     },
0722     { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
0723     SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
0724     0, 0,
0725     },
0726     { "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
0727     SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
0728     SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
0729     },
0730     { "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
0731     SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
0732     SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
0733     },
0734     { "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
0735     SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
0736     SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
0737     },
0738     { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
0739     SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
0740     0, 0,
0741     },
0742     { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
0743     SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
0744     0, 0,
0745     },
0746     { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
0747     0, 0,
0748     SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
0749     },
0750     { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
0751     0, 0,
0752     SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
0753     },
0754     { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
0755     0, 0,
0756     SOC15_REG_FIELD(MMEA0_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
0757     },
0758     { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
0759     0, 0,
0760     SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
0761     },
0762     { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
0763     0, 0,
0764     SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
0765     },
0766     { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
0767     0, 0,
0768     SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
0769     },
0770     { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
0771     0, 0,
0772     SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
0773     },
0774     { "MMEA0_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
0775     SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_SED_COUNT),
0776     SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_DED_COUNT),
0777     },
0778     { "MMEA0_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
0779     SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_SED_COUNT),
0780     SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_DED_COUNT),
0781     },
0782     { "MMEA0_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
0783     SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_SED_COUNT),
0784     SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_DED_COUNT),
0785     },
0786     { "MMEA0_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
0787     SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_SED_COUNT),
0788     SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_DED_COUNT),
0789     },
0790 
0791     /* MMHUB Range 1 */
0792     { "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
0793     SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
0794     SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
0795     },
0796     { "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
0797     SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
0798     SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
0799     },
0800     { "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
0801     SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
0802     SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
0803     },
0804     { "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
0805     SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
0806     SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_DED_COUNT),
0807     },
0808     { "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
0809     SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
0810     SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_DED_COUNT),
0811     },
0812     { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
0813     SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
0814     0, 0,
0815     },
0816     { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
0817     SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
0818     0, 0,
0819     },
0820     { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
0821     SOC15_REG_FIELD(MMEA1_EDC_CNT, IORD_CMDMEM_SED_COUNT),
0822     0, 0,
0823     },
0824     { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
0825     SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
0826     0, 0,
0827     },
0828     { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
0829     SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
0830     0, 0,
0831     },
0832     { "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
0833     SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
0834     SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
0835     },
0836     { "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
0837     SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
0838     SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
0839     },
0840     { "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
0841     SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
0842     SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
0843     },
0844     { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
0845     SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
0846     0, 0,
0847     },
0848     { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
0849     SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
0850     0, 0,
0851     },
0852     { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
0853     0, 0,
0854     SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
0855     },
0856     { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
0857     0, 0,
0858     SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
0859     },
0860     { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
0861     0, 0,
0862     SOC15_REG_FIELD(MMEA1_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
0863     },
0864     { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
0865     0, 0,
0866     SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
0867     },
0868     { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
0869     0, 0,
0870     SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
0871     },
0872     { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
0873     0, 0,
0874     SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
0875     },
0876     { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
0877     0, 0,
0878     SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
0879     },
0880     { "MMEA1_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
0881     SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_SED_COUNT),
0882     SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_DED_COUNT),
0883     },
0884     { "MMEA1_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
0885     SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_SED_COUNT),
0886     SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_DED_COUNT),
0887     },
0888     { "MMEA1_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
0889     SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_SED_COUNT),
0890     SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_DED_COUNT),
0891     },
0892     { "MMEA1_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
0893     SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_SED_COUNT),
0894     SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_DED_COUNT),
0895     },
0896 
0897     /* MMHAB Range 2*/
0898     { "MMEA2_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
0899     SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
0900     SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
0901     },
0902     { "MMEA2_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
0903     SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
0904     SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
0905     },
0906     { "MMEA2_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
0907     SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
0908     SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
0909     },
0910     { "MMEA2_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
0911     SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
0912     SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_DED_COUNT),
0913     },
0914     { "MMEA2_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
0915     SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
0916     SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_DED_COUNT),
0917     },
0918     { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
0919     SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
0920     0, 0,
0921     },
0922     { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
0923     SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
0924     0, 0,
0925     },
0926     { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
0927     SOC15_REG_FIELD(MMEA2_EDC_CNT, IORD_CMDMEM_SED_COUNT),
0928     0, 0,
0929     },
0930     { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
0931     SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
0932     0, 0,
0933     },
0934     { "MMEA2_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
0935     SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
0936     0, 0,
0937     },
0938     { "MMEA2_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
0939     SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
0940     SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
0941     },
0942     { "MMEA2_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
0943     SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
0944     SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
0945     },
0946     { "MMEA2_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
0947     SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
0948     SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
0949     },
0950     { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
0951     SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
0952     0, 0,
0953     },
0954     { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
0955     SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
0956     0, 0,
0957     },
0958     { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
0959     0, 0,
0960     SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
0961     },
0962     { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
0963     0, 0,
0964     SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
0965     },
0966     { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
0967     0, 0,
0968     SOC15_REG_FIELD(MMEA2_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
0969     },
0970     { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
0971     0, 0,
0972     SOC15_REG_FIELD(MMEA2_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
0973     },
0974     { "MMEA2_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
0975     0, 0,
0976     SOC15_REG_FIELD(MMEA2_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
0977     },
0978     { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
0979     0, 0,
0980     SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
0981     },
0982     { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
0983     0, 0,
0984     SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
0985     },
0986     { "MMEA2_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
0987     SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D0MEM_SED_COUNT),
0988     SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D0MEM_DED_COUNT),
0989     },
0990     { "MMEA2_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
0991     SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_SED_COUNT),
0992     SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_DED_COUNT),
0993     },
0994     { "MMEA2_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
0995     SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_SED_COUNT),
0996     SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_DED_COUNT),
0997     },
0998     { "MMEA2_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
0999     SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1000     SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1001     },
1002 
1003     /* MMHUB Rang 3 */
1004     { "MMEA3_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1005     SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1006     SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1007     },
1008     { "MMEA3_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1009     SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1010     SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1011     },
1012     { "MMEA3_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1013     SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1014     SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1015     },
1016     { "MMEA3_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1017     SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1018     SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1019     },
1020     { "MMEA3_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1021     SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1022     SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1023     },
1024     { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1025     SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1026     0, 0,
1027     },
1028     { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1029     SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1030     0, 0,
1031     },
1032     { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1033     SOC15_REG_FIELD(MMEA3_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1034     0, 0,
1035     },
1036     { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1037     SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1038     0, 0,
1039     },
1040     { "MMEA3_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1041     SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1042     0, 0,
1043     },
1044     { "MMEA3_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1045     SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1046     SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1047     },
1048     { "MMEA3_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1049     SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1050     SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1051     },
1052     { "MMEA3_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1053     SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1054     SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1055     },
1056     { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1057     SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1058     0, 0,
1059     },
1060     { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1061     SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1062     0, 0,
1063     },
1064     { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1065     0, 0,
1066     SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1067     },
1068     { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1069     0, 0,
1070     SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1071     },
1072     { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1073     0, 0,
1074     SOC15_REG_FIELD(MMEA3_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1075     },
1076     { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1077     0, 0,
1078     SOC15_REG_FIELD(MMEA3_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1079     },
1080     { "MMEA3_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1081     0, 0,
1082     SOC15_REG_FIELD(MMEA3_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1083     },
1084     { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1085     0, 0,
1086     SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1087     },
1088     { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1089     0, 0,
1090     SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1091     },
1092     { "MMEA3_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1093     SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1094     SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1095     },
1096     { "MMEA3_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1097     SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1098     SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1099     },
1100     { "MMEA3_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1101     SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1102     SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1103     },
1104     { "MMEA3_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1105     SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1106     SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1107     },
1108 
1109     /* MMHUB Range 4 */
1110     { "MMEA4_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1111     SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1112     SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1113     },
1114     { "MMEA4_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1115     SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1116     SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1117     },
1118     { "MMEA4_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1119     SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1120     SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1121     },
1122     { "MMEA4_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1123     SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1124     SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1125     },
1126     { "MMEA4_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1127     SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1128     SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1129     },
1130     { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1131     SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1132     0, 0,
1133     },
1134     { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1135     SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1136     0, 0,
1137     },
1138     { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1139     SOC15_REG_FIELD(MMEA4_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1140     0, 0,
1141     },
1142     { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1143     SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1144     0, 0,
1145     },
1146     { "MMEA4_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1147     SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1148     0, 0,
1149     },
1150     { "MMEA4_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1151     SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1152     SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1153     },
1154     { "MMEA4_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1155     SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1156     SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1157     },
1158     { "MMEA4_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1159     SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1160     SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1161     },
1162     { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1163     SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1164     0, 0,
1165     },
1166     { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1167     SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1168     0, 0,
1169     },
1170     { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1171     0, 0,
1172     SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1173     },
1174     { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1175     0, 0,
1176     SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1177     },
1178     { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1179     0, 0,
1180     SOC15_REG_FIELD(MMEA4_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1181     },
1182     { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1183     0, 0,
1184     SOC15_REG_FIELD(MMEA4_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1185     },
1186     { "MMEA4_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1187     0, 0,
1188     SOC15_REG_FIELD(MMEA4_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1189     },
1190     { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1191     0, 0,
1192     SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1193     },
1194     { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1195     0, 0,
1196     SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1197     },
1198     { "MMEA4_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1199     SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1200     SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1201     },
1202     { "MMEA4_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1203     SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1204     SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1205     },
1206     { "MMEA4_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1207     SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1208     SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1209     },
1210     { "MMEA4_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1211     SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1212     SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1213     },
1214 
1215     /* MMHUAB Range 5 */
1216     { "MMEA5_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1217     SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1218     SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1219     },
1220     { "MMEA5_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1221     SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1222     SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1223     },
1224     { "MMEA5_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1225     SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1226     SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1227     },
1228     { "MMEA5_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1229     SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1230     SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1231     },
1232     { "MMEA5_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1233     SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1234     SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1235     },
1236     { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1237     SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1238     0, 0,
1239     },
1240     { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1241     SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1242     0, 0,
1243     },
1244     { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1245     SOC15_REG_FIELD(MMEA5_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1246     0, 0,
1247     },
1248     { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1249     SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1250     0, 0,
1251     },
1252     { "MMEA5_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1253     SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1254     0, 0,
1255     },
1256     { "MMEA5_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1257     SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1258     SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1259     },
1260     { "MMEA5_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1261     SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1262     SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1263     },
1264     { "MMEA5_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1265     SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1266     SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1267     },
1268     { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1269     SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1270     0, 0,
1271     },
1272     { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1273     SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1274     0, 0,
1275     },
1276     { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1277     0, 0,
1278     SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1279     },
1280     { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1281     0, 0,
1282     SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1283     },
1284     { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1285     0, 0,
1286     SOC15_REG_FIELD(MMEA5_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1287     },
1288     { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1289     0, 0,
1290     SOC15_REG_FIELD(MMEA5_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1291     },
1292     { "MMEA5_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1293     0, 0,
1294     SOC15_REG_FIELD(MMEA5_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1295     },
1296     { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1297     0, 0,
1298     SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1299     },
1300     { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1301     0, 0,
1302     SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1303     },
1304     { "MMEA5_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1305     SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1306     SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1307     },
1308     { "MMEA5_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1309     SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1310     SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1311     },
1312     { "MMEA5_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1313     SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1314     SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1315     },
1316     { "MMEA5_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1317     SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1318     SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1319     },
1320 
1321     /* MMHUB Range 6 */
1322     { "MMEA6_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1323     SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1324     SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1325     },
1326     { "MMEA6_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1327     SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1328     SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1329     },
1330     { "MMEA6_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1331     SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1332     SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1333     },
1334     { "MMEA6_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1335     SOC15_REG_FIELD(MMEA6_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1336     SOC15_REG_FIELD(MMEA6_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1337     },
1338     { "MMEA6_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1339     SOC15_REG_FIELD(MMEA6_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1340     SOC15_REG_FIELD(MMEA6_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1341     },
1342     { "MMEA6_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1343     SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1344     0, 0,
1345     },
1346     { "MMEA6_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1347     SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1348     0, 0,
1349     },
1350     { "MMEA6_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1351     SOC15_REG_FIELD(MMEA6_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1352     0, 0,
1353     },
1354     { "MMEA6_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1355     SOC15_REG_FIELD(MMEA6_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1356     0, 0,
1357     },
1358     { "MMEA6_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1359     SOC15_REG_FIELD(MMEA6_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1360     0, 0,
1361     },
1362     { "MMEA6_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1363     SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1364     SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1365     },
1366     { "MMEA6_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1367     SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1368     SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1369     },
1370     { "MMEA6_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1371     SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1372     SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1373     },
1374     { "MMEA6_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1375     SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1376     0, 0,
1377     },
1378     { "MMEA6_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1379     SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1380     0, 0,
1381     },
1382     { "MMEA6_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1383     0, 0,
1384     SOC15_REG_FIELD(MMEA6_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1385     },
1386     { "MMEA6_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1387     0, 0,
1388     SOC15_REG_FIELD(MMEA6_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1389     },
1390     { "MMEA6_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1391     0, 0,
1392     SOC15_REG_FIELD(MMEA6_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1393     },
1394     { "MMEA6_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1395     0, 0,
1396     SOC15_REG_FIELD(MMEA6_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1397     },
1398     { "MMEA6_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1399     0, 0,
1400     SOC15_REG_FIELD(MMEA6_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1401     },
1402     { "MMEA6_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1403     0, 0,
1404     SOC15_REG_FIELD(MMEA6_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1405     },
1406     { "MMEA6_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1407     0, 0,
1408     SOC15_REG_FIELD(MMEA6_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1409     },
1410     { "MMEA6_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1411     SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1412     SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1413     },
1414     { "MMEA6_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1415     SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1416     SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1417     },
1418     { "MMEA6_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1419     SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1420     SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1421     },
1422     { "MMEA6_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1423     SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1424     SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1425     },
1426 
1427     /* MMHUB Range 7*/
1428     { "MMEA7_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1429     SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1430     SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1431     },
1432     { "MMEA7_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1433     SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1434     SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1435     },
1436     { "MMEA7_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1437     SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1438     SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1439     },
1440     { "MMEA7_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1441     SOC15_REG_FIELD(MMEA7_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1442     SOC15_REG_FIELD(MMEA7_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1443     },
1444     { "MMEA7_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1445     SOC15_REG_FIELD(MMEA7_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1446     SOC15_REG_FIELD(MMEA7_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1447     },
1448     { "MMEA7_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1449     SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1450     0, 0,
1451     },
1452     { "MMEA7_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1453     SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1454     0, 0,
1455     },
1456     { "MMEA7_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1457     SOC15_REG_FIELD(MMEA7_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1458     0, 0,
1459     },
1460     { "MMEA7_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1461     SOC15_REG_FIELD(MMEA7_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1462     0, 0,
1463     },
1464     { "MMEA7_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1465     SOC15_REG_FIELD(MMEA7_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1466     0, 0,
1467     },
1468     { "MMEA7_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1469     SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1470     SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1471     },
1472     { "MMEA7_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1473     SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1474     SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1475     },
1476     { "MMEA7_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1477     SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1478     SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1479     },
1480     { "MMEA7_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1481     SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1482     0, 0,
1483     },
1484     { "MMEA7_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1485     SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1486     0, 0,
1487     },
1488     { "MMEA7_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1489     0, 0,
1490     SOC15_REG_FIELD(MMEA7_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1491     },
1492     { "MMEA7_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1493     0, 0,
1494     SOC15_REG_FIELD(MMEA7_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1495     },
1496     { "MMEA7_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1497     0, 0,
1498     SOC15_REG_FIELD(MMEA7_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1499     },
1500     { "MMEA7_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1501     0, 0,
1502     SOC15_REG_FIELD(MMEA7_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1503     },
1504     { "MMEA7_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1505     0, 0,
1506     SOC15_REG_FIELD(MMEA7_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1507     },
1508     { "MMEA7_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1509     0, 0,
1510     SOC15_REG_FIELD(MMEA7_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1511     },
1512     { "MMEA7_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1513     0, 0,
1514     SOC15_REG_FIELD(MMEA7_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1515     },
1516     { "MMEA7_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1517     SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1518     SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1519     },
1520     { "MMEA7_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1521     SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1522     SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1523     },
1524     { "MMEA7_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1525     SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1526     SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1527     },
1528     { "MMEA7_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1529     SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1530     SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1531     }
1532 };
1533 
1534 static const struct soc15_reg_entry mmhub_v9_4_edc_cnt_regs[] = {
1535     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 0, 0, 0 },
1536     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 0, 0, 0 },
1537     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 0, 0, 0 },
1538     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 0, 0, 0 },
1539     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 0, 0, 0 },
1540     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3), 0, 0, 0 },
1541     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 0, 0, 0 },
1542     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 0, 0, 0 },
1543     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3), 0, 0, 0 },
1544     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 0, 0, 0 },
1545     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 0, 0, 0 },
1546     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3), 0, 0, 0 },
1547     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 0, 0, 0 },
1548     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 0, 0, 0 },
1549     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3), 0, 0, 0 },
1550     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 0, 0, 0 },
1551     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 0, 0, 0 },
1552     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3), 0, 0, 0 },
1553     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 0, 0, 0 },
1554     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 0, 0, 0 },
1555     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3), 0, 0, 0 },
1556     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 0, 0, 0 },
1557     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 0, 0, 0 },
1558     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3), 0, 0, 0 },
1559 };
1560 
1561 static int mmhub_v9_4_get_ras_error_count(struct amdgpu_device *adev,
1562                       const struct soc15_reg_entry *reg,
1563                       uint32_t value,
1564                       uint32_t *sec_count,
1565                       uint32_t *ded_count)
1566 {
1567     uint32_t i;
1568     uint32_t sec_cnt, ded_cnt;
1569 
1570     for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_ras_fields); i++) {
1571         if(mmhub_v9_4_ras_fields[i].reg_offset != reg->reg_offset)
1572             continue;
1573 
1574         sec_cnt = (value &
1575                 mmhub_v9_4_ras_fields[i].sec_count_mask) >>
1576                 mmhub_v9_4_ras_fields[i].sec_count_shift;
1577         if (sec_cnt) {
1578             dev_info(adev->dev, "MMHUB SubBlock %s, SEC %d\n",
1579                 mmhub_v9_4_ras_fields[i].name,
1580                 sec_cnt);
1581             *sec_count += sec_cnt;
1582         }
1583 
1584         ded_cnt = (value &
1585                 mmhub_v9_4_ras_fields[i].ded_count_mask) >>
1586                 mmhub_v9_4_ras_fields[i].ded_count_shift;
1587         if (ded_cnt) {
1588             dev_info(adev->dev, "MMHUB SubBlock %s, DED %d\n",
1589                 mmhub_v9_4_ras_fields[i].name,
1590                 ded_cnt);
1591             *ded_count += ded_cnt;
1592         }
1593     }
1594 
1595     return 0;
1596 }
1597 
1598 static void mmhub_v9_4_query_ras_error_count(struct amdgpu_device *adev,
1599                        void *ras_error_status)
1600 {
1601     struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
1602     uint32_t sec_count = 0, ded_count = 0;
1603     uint32_t i;
1604     uint32_t reg_value;
1605 
1606     err_data->ue_count = 0;
1607     err_data->ce_count = 0;
1608 
1609     for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_edc_cnt_regs); i++) {
1610         reg_value =
1611             RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i]));
1612         if (reg_value)
1613             mmhub_v9_4_get_ras_error_count(adev, &mmhub_v9_4_edc_cnt_regs[i],
1614                 reg_value, &sec_count, &ded_count);
1615     }
1616 
1617     err_data->ce_count += sec_count;
1618     err_data->ue_count += ded_count;
1619 }
1620 
1621 static void mmhub_v9_4_reset_ras_error_count(struct amdgpu_device *adev)
1622 {
1623     uint32_t i;
1624 
1625     /* read back edc counter registers to reset the counters to 0 */
1626     if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) {
1627         for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_edc_cnt_regs); i++)
1628             RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i]));
1629     }
1630 }
1631 
1632 static const struct soc15_reg_entry mmhub_v9_4_err_status_regs[] = {
1633     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_ERR_STATUS), 0, 0, 0 },
1634     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_ERR_STATUS), 0, 0, 0 },
1635     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_ERR_STATUS), 0, 0, 0 },
1636     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_ERR_STATUS), 0, 0, 0 },
1637     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_ERR_STATUS), 0, 0, 0 },
1638     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_ERR_STATUS), 0, 0, 0 },
1639     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_ERR_STATUS), 0, 0, 0 },
1640     { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_ERR_STATUS), 0, 0, 0 },
1641 };
1642 
1643 static void mmhub_v9_4_query_ras_error_status(struct amdgpu_device *adev)
1644 {
1645     int i;
1646     uint32_t reg_value;
1647 
1648     if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB))
1649         return;
1650 
1651     for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_err_status_regs); i++) {
1652         reg_value =
1653             RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_err_status_regs[i]));
1654         if (REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_STATUS) ||
1655             REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_WRRSP_STATUS) ||
1656             REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
1657             /* SDP read/write error/parity error in FUE_IS_FATAL mode
1658              * can cause system fatal error in arcturas. Harvest the error
1659              * status before GPU reset */
1660             dev_warn(adev->dev, "MMHUB EA err detected at instance: %d, status: 0x%x!\n",
1661                     i, reg_value);
1662         }
1663     }
1664 }
1665 
1666 const struct amdgpu_ras_block_hw_ops mmhub_v9_4_ras_hw_ops = {
1667     .query_ras_error_count = mmhub_v9_4_query_ras_error_count,
1668     .reset_ras_error_count = mmhub_v9_4_reset_ras_error_count,
1669     .query_ras_error_status = mmhub_v9_4_query_ras_error_status,
1670 };
1671 
1672 struct amdgpu_mmhub_ras mmhub_v9_4_ras = {
1673     .ras_block = {
1674         .hw_ops = &mmhub_v9_4_ras_hw_ops,
1675     },
1676 };
1677 
1678 const struct amdgpu_mmhub_funcs mmhub_v9_4_funcs = {
1679     .get_fb_location = mmhub_v9_4_get_fb_location,
1680     .init = mmhub_v9_4_init,
1681     .gart_enable = mmhub_v9_4_gart_enable,
1682     .set_fault_enable_default = mmhub_v9_4_set_fault_enable_default,
1683     .gart_disable = mmhub_v9_4_gart_disable,
1684     .set_clockgating = mmhub_v9_4_set_clockgating,
1685     .get_clockgating = mmhub_v9_4_get_clockgating,
1686     .setup_vm_pt_regs = mmhub_v9_4_setup_vm_pt_regs,
1687 };
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