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0001 /*
0002  * Copyright 2022 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #include "amdgpu.h"
0025 #include "mmhub_v3_0_2.h"
0026 
0027 #include "mmhub/mmhub_3_0_2_offset.h"
0028 #include "mmhub/mmhub_3_0_2_sh_mask.h"
0029 #include "navi10_enum.h"
0030 
0031 #include "soc15_common.h"
0032 
0033 #define regMMVM_L2_CNTL3_DEFAULT                0x80100007
0034 #define regMMVM_L2_CNTL4_DEFAULT                0x000000c1
0035 #define regMMVM_L2_CNTL5_DEFAULT                0x00003fe0
0036 
0037 static const char *mmhub_client_ids_v3_0_2[][2] = {
0038     [0][0] = "VMC",
0039     [4][0] = "DCEDMC",
0040     [5][0] = "DCEVGA",
0041     [6][0] = "MP0",
0042     [7][0] = "MP1",
0043     [8][0] = "MPIO",
0044     [16][0] = "HDP",
0045     [17][0] = "LSDMA",
0046     [18][0] = "JPEG",
0047     [19][0] = "VCNU0",
0048     [21][0] = "VSCH",
0049     [22][0] = "VCNU1",
0050     [23][0] = "VCN1",
0051     [32+20][0] = "VCN0",
0052     [2][1] = "DBGUNBIO",
0053     [3][1] = "DCEDWB",
0054     [4][1] = "DCEDMC",
0055     [5][1] = "DCEVGA",
0056     [6][1] = "MP0",
0057     [7][1] = "MP1",
0058     [8][1] = "MPIO",
0059     [10][1] = "DBGU0",
0060     [11][1] = "DBGU1",
0061     [12][1] = "DBGU2",
0062     [13][1] = "DBGU3",
0063     [14][1] = "XDP",
0064     [15][1] = "OSSSYS",
0065     [16][1] = "HDP",
0066     [17][1] = "LSDMA",
0067     [18][1] = "JPEG",
0068     [19][1] = "VCNU0",
0069     [20][1] = "VCN0",
0070     [21][1] = "VSCH",
0071     [22][1] = "VCNU1",
0072     [23][1] = "VCN1",
0073 };
0074 
0075 static uint32_t mmhub_v3_0_2_get_invalidate_req(unsigned int vmid,
0076                           uint32_t flush_type)
0077 {
0078     u32 req = 0;
0079 
0080     /* invalidate using legacy mode on vmid*/
0081     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
0082                 PER_VMID_INVALIDATE_REQ, 1 << vmid);
0083     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
0084     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
0085     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
0086     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
0087     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
0088     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
0089     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
0090                 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
0091 
0092     return req;
0093 }
0094 
0095 static void
0096 mmhub_v3_0_2_print_l2_protection_fault_status(struct amdgpu_device *adev,
0097                          uint32_t status)
0098 {
0099     uint32_t cid, rw;
0100     const char *mmhub_cid = NULL;
0101 
0102     cid = REG_GET_FIELD(status,
0103                 MMVM_L2_PROTECTION_FAULT_STATUS, CID);
0104     rw = REG_GET_FIELD(status,
0105                MMVM_L2_PROTECTION_FAULT_STATUS, RW);
0106 
0107     dev_err(adev->dev,
0108         "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
0109         status);
0110 
0111     mmhub_cid = mmhub_client_ids_v3_0_2[cid][rw];
0112     dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
0113         mmhub_cid ? mmhub_cid : "unknown", cid);
0114     dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
0115         REG_GET_FIELD(status,
0116         MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
0117     dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
0118         REG_GET_FIELD(status,
0119         MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
0120     dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
0121         REG_GET_FIELD(status,
0122         MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
0123     dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
0124         REG_GET_FIELD(status,
0125         MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
0126     dev_err(adev->dev, "\t RW: 0x%x\n", rw);
0127 }
0128 
0129 static void mmhub_v3_0_2_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
0130                 uint64_t page_table_base)
0131 {
0132     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0133 
0134     WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
0135                 hub->ctx_addr_distance * vmid,
0136                 lower_32_bits(page_table_base));
0137 
0138     WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
0139                 hub->ctx_addr_distance * vmid,
0140                 upper_32_bits(page_table_base));
0141 }
0142 
0143 static void mmhub_v3_0_2_init_gart_aperture_regs(struct amdgpu_device *adev)
0144 {
0145     uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
0146 
0147     mmhub_v3_0_2_setup_vm_pt_regs(adev, 0, pt_base);
0148 
0149     WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
0150              (u32)(adev->gmc.gart_start >> 12));
0151     WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
0152              (u32)(adev->gmc.gart_start >> 44));
0153 
0154     WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
0155              (u32)(adev->gmc.gart_end >> 12));
0156     WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
0157              (u32)(adev->gmc.gart_end >> 44));
0158 }
0159 
0160 static void mmhub_v3_0_2_init_system_aperture_regs(struct amdgpu_device *adev)
0161 {
0162     uint64_t value;
0163     uint32_t tmp;
0164 
0165     /* Disable AGP. */
0166     WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);
0167     WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, 0);
0168     WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, 0x00FFFFFF);
0169 
0170     if (!amdgpu_sriov_vf(adev)) {
0171         /*
0172          * the new L1 policy will block SRIOV guest from writing
0173          * these regs, and they will be programed at host.
0174          * so skip programing these regs.
0175          */
0176         /* Program the system aperture low logical page number. */
0177         WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
0178                  adev->gmc.vram_start >> 18);
0179         WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
0180                  adev->gmc.vram_end >> 18);
0181     }
0182 
0183     /* Set default page address. */
0184     value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
0185         adev->vm_manager.vram_base_offset;
0186     WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
0187              (u32)(value >> 12));
0188     WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
0189              (u32)(value >> 44));
0190 
0191     /* Program "protection fault". */
0192     WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
0193              (u32)(adev->dummy_page_addr >> 12));
0194     WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
0195              (u32)((u64)adev->dummy_page_addr >> 44));
0196 
0197     tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);
0198     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
0199                 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
0200     WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
0201 }
0202 
0203 static void mmhub_v3_0_2_init_tlb_regs(struct amdgpu_device *adev)
0204 {
0205     uint32_t tmp;
0206 
0207     /* Setup TLB control */
0208     tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
0209 
0210     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
0211     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
0212     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
0213                 ENABLE_ADVANCED_DRIVER_MODEL, 1);
0214     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
0215                 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
0216     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
0217     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
0218                 MTYPE, MTYPE_UC); /* UC, uncached */
0219 
0220     WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
0221 }
0222 
0223 static void mmhub_v3_0_2_init_cache_regs(struct amdgpu_device *adev)
0224 {
0225     uint32_t tmp;
0226 
0227     /* These registers are not accessible to VF-SRIOV.
0228      * The PF will program them instead.
0229      */
0230     if (amdgpu_sriov_vf(adev))
0231         return;
0232 
0233     /* Setup L2 cache */
0234     tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
0235     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
0236     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
0237     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
0238                 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
0239     /* XXX for emulation, Refer to closed source code.*/
0240     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
0241                 0);
0242     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
0243     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
0244     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
0245     WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
0246 
0247     tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);
0248     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
0249     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
0250     WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp);
0251 
0252     tmp = regMMVM_L2_CNTL3_DEFAULT;
0253     if (adev->gmc.translate_further) {
0254         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
0255         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
0256                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
0257     } else {
0258         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
0259         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
0260                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
0261     }
0262     WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp);
0263 
0264     tmp = regMMVM_L2_CNTL4_DEFAULT;
0265     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
0266     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
0267     WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp);
0268 
0269     tmp = regMMVM_L2_CNTL5_DEFAULT;
0270     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
0271     WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp);
0272 }
0273 
0274 static void mmhub_v3_0_2_enable_system_domain(struct amdgpu_device *adev)
0275 {
0276     uint32_t tmp;
0277 
0278     tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
0279     tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
0280     tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
0281     tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
0282                 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
0283     WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp);
0284 }
0285 
0286 static void mmhub_v3_0_2_disable_identity_aperture(struct amdgpu_device *adev)
0287 {
0288     /* These registers are not accessible to VF-SRIOV.
0289      * The PF will program them instead.
0290      */
0291     if (amdgpu_sriov_vf(adev))
0292         return;
0293 
0294     WREG32_SOC15(MMHUB, 0,
0295              regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
0296              0xFFFFFFFF);
0297     WREG32_SOC15(MMHUB, 0,
0298              regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
0299              0x0000000F);
0300 
0301     WREG32_SOC15(MMHUB, 0,
0302              regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
0303     WREG32_SOC15(MMHUB, 0,
0304              regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
0305 
0306     WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
0307              0);
0308     WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
0309              0);
0310 }
0311 
0312 static void mmhub_v3_0_2_setup_vmid_config(struct amdgpu_device *adev)
0313 {
0314     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0315     int i;
0316     uint32_t tmp;
0317 
0318     for (i = 0; i <= 14; i++) {
0319         tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i);
0320         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
0321         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
0322                     adev->vm_manager.num_level);
0323         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0324                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0325         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0326                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
0327                     1);
0328         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0329                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0330         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0331                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0332         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0333                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0334         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0335                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0336         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0337                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0338         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0339                     PAGE_TABLE_BLOCK_SIZE,
0340                     adev->vm_manager.block_size - 9);
0341         /* Send no-retry XNACK on fault to suppress VM fault storm. */
0342         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0343                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
0344                     !amdgpu_noretry);
0345         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL,
0346                     i * hub->ctx_distance, tmp);
0347         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
0348                     i * hub->ctx_addr_distance, 0);
0349         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
0350                     i * hub->ctx_addr_distance, 0);
0351         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
0352                     i * hub->ctx_addr_distance,
0353                     lower_32_bits(adev->vm_manager.max_pfn - 1));
0354         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
0355                     i * hub->ctx_addr_distance,
0356                     upper_32_bits(adev->vm_manager.max_pfn - 1));
0357     }
0358 
0359     hub->vm_cntx_cntl = tmp;
0360 }
0361 
0362 static void mmhub_v3_0_2_program_invalidation(struct amdgpu_device *adev)
0363 {
0364     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0365     unsigned i;
0366 
0367     for (i = 0; i < 18; ++i) {
0368         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
0369                     i * hub->eng_addr_distance, 0xffffffff);
0370         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
0371                     i * hub->eng_addr_distance, 0x1f);
0372     }
0373 }
0374 
0375 static int mmhub_v3_0_2_gart_enable(struct amdgpu_device *adev)
0376 {
0377     /* GART Enable. */
0378     mmhub_v3_0_2_init_gart_aperture_regs(adev);
0379     mmhub_v3_0_2_init_system_aperture_regs(adev);
0380     mmhub_v3_0_2_init_tlb_regs(adev);
0381     mmhub_v3_0_2_init_cache_regs(adev);
0382 
0383     mmhub_v3_0_2_enable_system_domain(adev);
0384     mmhub_v3_0_2_disable_identity_aperture(adev);
0385     mmhub_v3_0_2_setup_vmid_config(adev);
0386     mmhub_v3_0_2_program_invalidation(adev);
0387 
0388     return 0;
0389 }
0390 
0391 static void mmhub_v3_0_2_gart_disable(struct amdgpu_device *adev)
0392 {
0393     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0394     u32 tmp;
0395     u32 i;
0396 
0397     /* Disable all tables */
0398     for (i = 0; i < 16; i++)
0399         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL,
0400                     i * hub->ctx_distance, 0);
0401 
0402     /* Setup TLB control */
0403     tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
0404     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
0405     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
0406                 ENABLE_ADVANCED_DRIVER_MODEL, 0);
0407     WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
0408 
0409     /* Setup L2 cache */
0410     tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
0411     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
0412     WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
0413     WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0);
0414 }
0415 
0416 /**
0417  * mmhub_v3_0_2_set_fault_enable_default - update GART/VM fault handling
0418  *
0419  * @adev: amdgpu_device pointer
0420  * @value: true redirects VM faults to the default page
0421  */
0422 static void mmhub_v3_0_2_set_fault_enable_default(struct amdgpu_device *adev, bool value)
0423 {
0424     u32 tmp;
0425 
0426     /* These registers are not accessible to VF-SRIOV.
0427      * The PF will program them instead.
0428      */
0429     if (amdgpu_sriov_vf(adev))
0430         return;
0431 
0432     tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
0433     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0434                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0435     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0436                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0437     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0438                 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0439     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0440                 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0441     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0442                 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
0443                 value);
0444     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0445                 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0446     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0447                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0448     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0449                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0450     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0451                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0452     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0453                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0454     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0455                 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0456     if (!value) {
0457         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0458                 CRASH_ON_NO_RETRY_FAULT, 1);
0459         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0460                 CRASH_ON_RETRY_FAULT, 1);
0461     }
0462     WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
0463 }
0464 
0465 static const struct amdgpu_vmhub_funcs mmhub_v3_0_2_vmhub_funcs = {
0466     .print_l2_protection_fault_status = mmhub_v3_0_2_print_l2_protection_fault_status,
0467     .get_invalidate_req = mmhub_v3_0_2_get_invalidate_req,
0468 };
0469 
0470 static void mmhub_v3_0_2_init(struct amdgpu_device *adev)
0471 {
0472     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0473 
0474     hub->ctx0_ptb_addr_lo32 =
0475         SOC15_REG_OFFSET(MMHUB, 0,
0476                  regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
0477     hub->ctx0_ptb_addr_hi32 =
0478         SOC15_REG_OFFSET(MMHUB, 0,
0479                  regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
0480     hub->vm_inv_eng0_sem =
0481         SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM);
0482     hub->vm_inv_eng0_req =
0483         SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ);
0484     hub->vm_inv_eng0_ack =
0485         SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK);
0486     hub->vm_context0_cntl =
0487         SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
0488     hub->vm_l2_pro_fault_status =
0489         SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS);
0490     hub->vm_l2_pro_fault_cntl =
0491         SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
0492 
0493     hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL;
0494     hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
0495         regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
0496     hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ -
0497         regMMVM_INVALIDATE_ENG0_REQ;
0498     hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
0499         regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
0500 
0501     hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0502         MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0503         MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0504         MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0505         MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0506         MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0507         MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
0508 
0509     hub->vm_l2_bank_select_reserved_cid2 =
0510         SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_BANK_SELECT_RESERVED_CID2);
0511 
0512     hub->vmhub_funcs = &mmhub_v3_0_2_vmhub_funcs;
0513 }
0514 
0515 static u64 mmhub_v3_0_2_get_fb_location(struct amdgpu_device *adev)
0516 {
0517     u64 base;
0518 
0519     base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);
0520     base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
0521     base <<= 24;
0522 
0523     return base;
0524 }
0525 
0526 static u64 mmhub_v3_0_2_get_mc_fb_offset(struct amdgpu_device *adev)
0527 {
0528     return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;
0529 }
0530 
0531 static void mmhub_v3_0_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
0532                             bool enable)
0533 {
0534     //TODO
0535 }
0536 
0537 static void mmhub_v3_0_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
0538                                bool enable)
0539 {
0540     //TODO
0541 }
0542 
0543 static int mmhub_v3_0_2_set_clockgating(struct amdgpu_device *adev,
0544                    enum amd_clockgating_state state)
0545 {
0546     if (amdgpu_sriov_vf(adev))
0547         return 0;
0548 
0549     mmhub_v3_0_2_update_medium_grain_clock_gating(adev,
0550             state == AMD_CG_STATE_GATE);
0551     mmhub_v3_0_2_update_medium_grain_light_sleep(adev,
0552             state == AMD_CG_STATE_GATE);
0553     return 0;
0554 }
0555 
0556 static void mmhub_v3_0_2_get_clockgating(struct amdgpu_device *adev, u64 *flags)
0557 {
0558     //TODO
0559 }
0560 
0561 const struct amdgpu_mmhub_funcs mmhub_v3_0_2_funcs = {
0562     .init = mmhub_v3_0_2_init,
0563     .get_fb_location = mmhub_v3_0_2_get_fb_location,
0564     .get_mc_fb_offset = mmhub_v3_0_2_get_mc_fb_offset,
0565     .gart_enable = mmhub_v3_0_2_gart_enable,
0566     .set_fault_enable_default = mmhub_v3_0_2_set_fault_enable_default,
0567     .gart_disable = mmhub_v3_0_2_gart_disable,
0568     .set_clockgating = mmhub_v3_0_2_set_clockgating,
0569     .get_clockgating = mmhub_v3_0_2_get_clockgating,
0570     .setup_vm_pt_regs = mmhub_v3_0_2_setup_vm_pt_regs,
0571 };
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