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0001 /*
0002  * Copyright 2022 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #include "amdgpu.h"
0025 #include "mmhub_v3_0_1.h"
0026 
0027 #include "mmhub/mmhub_3_0_1_offset.h"
0028 #include "mmhub/mmhub_3_0_1_sh_mask.h"
0029 #include "navi10_enum.h"
0030 
0031 #include "soc15_common.h"
0032 
0033 #define regMMVM_L2_CNTL3_DEFAULT                0x80100007
0034 #define regMMVM_L2_CNTL4_DEFAULT                0x000000c1
0035 #define regMMVM_L2_CNTL5_DEFAULT                0x00003fe0
0036 
0037 static const char *mmhub_client_ids_v3_0_1[][2] = {
0038     [0][0] = "VMC",
0039     [4][0] = "DCEDMC",
0040     [5][0] = "DCEVGA",
0041     [6][0] = "MP0",
0042     [7][0] = "MP1",
0043     [8][0] = "MPIO",
0044     [16][0] = "HDP",
0045     [17][0] = "LSDMA",
0046     [18][0] = "JPEG",
0047     [19][0] = "VCNU0",
0048     [21][0] = "VSCH",
0049     [22][0] = "VCNU1",
0050     [23][0] = "VCN1",
0051     [32+20][0] = "VCN0",
0052     [2][1] = "DBGUNBIO",
0053     [3][1] = "DCEDWB",
0054     [4][1] = "DCEDMC",
0055     [5][1] = "DCEVGA",
0056     [6][1] = "MP0",
0057     [7][1] = "MP1",
0058     [8][1] = "MPIO",
0059     [10][1] = "DBGU0",
0060     [11][1] = "DBGU1",
0061     [12][1] = "DBGU2",
0062     [13][1] = "DBGU3",
0063     [14][1] = "XDP",
0064     [15][1] = "OSSSYS",
0065     [16][1] = "HDP",
0066     [17][1] = "LSDMA",
0067     [18][1] = "JPEG",
0068     [19][1] = "VCNU0",
0069     [20][1] = "VCN0",
0070     [21][1] = "VSCH",
0071     [22][1] = "VCNU1",
0072     [23][1] = "VCN1",
0073 };
0074 
0075 static uint32_t mmhub_v3_0_1_get_invalidate_req(unsigned int vmid,
0076                         uint32_t flush_type)
0077 {
0078     u32 req = 0;
0079 
0080     /* invalidate using legacy mode on vmid*/
0081     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
0082                 PER_VMID_INVALIDATE_REQ, 1 << vmid);
0083     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
0084     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
0085     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
0086     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
0087     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
0088     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
0089     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
0090                 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
0091 
0092     return req;
0093 }
0094 
0095 static void
0096 mmhub_v3_0_1_print_l2_protection_fault_status(struct amdgpu_device *adev,
0097                           uint32_t status)
0098 {
0099     uint32_t cid, rw;
0100     const char *mmhub_cid = NULL;
0101 
0102     cid = REG_GET_FIELD(status,
0103                 MMVM_L2_PROTECTION_FAULT_STATUS, CID);
0104     rw = REG_GET_FIELD(status,
0105                MMVM_L2_PROTECTION_FAULT_STATUS, RW);
0106 
0107     dev_err(adev->dev,
0108         "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
0109         status);
0110 
0111     switch (adev->ip_versions[MMHUB_HWIP][0]) {
0112     case IP_VERSION(3, 0, 1):
0113         mmhub_cid = mmhub_client_ids_v3_0_1[cid][rw];
0114         break;
0115     default:
0116         mmhub_cid = NULL;
0117         break;
0118     }
0119 
0120     dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
0121         mmhub_cid ? mmhub_cid : "unknown", cid);
0122     dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
0123         REG_GET_FIELD(status,
0124         MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
0125     dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
0126         REG_GET_FIELD(status,
0127         MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
0128     dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
0129         REG_GET_FIELD(status,
0130         MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
0131     dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
0132         REG_GET_FIELD(status,
0133         MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
0134     dev_err(adev->dev, "\t RW: 0x%x\n", rw);
0135 }
0136 
0137 static void mmhub_v3_0_1_setup_vm_pt_regs(struct amdgpu_device *adev,
0138                       uint32_t vmid,
0139                       uint64_t page_table_base)
0140 {
0141     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0142 
0143     WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
0144                 hub->ctx_addr_distance * vmid,
0145                 lower_32_bits(page_table_base));
0146 
0147     WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
0148                 hub->ctx_addr_distance * vmid,
0149                 upper_32_bits(page_table_base));
0150 }
0151 
0152 static void mmhub_v3_0_1_init_gart_aperture_regs(struct amdgpu_device *adev)
0153 {
0154     uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
0155 
0156     mmhub_v3_0_1_setup_vm_pt_regs(adev, 0, pt_base);
0157 
0158     WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
0159              (u32)(adev->gmc.gart_start >> 12));
0160     WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
0161              (u32)(adev->gmc.gart_start >> 44));
0162 
0163     WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
0164              (u32)(adev->gmc.gart_end >> 12));
0165     WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
0166              (u32)(adev->gmc.gart_end >> 44));
0167 }
0168 
0169 static void mmhub_v3_0_1_init_system_aperture_regs(struct amdgpu_device *adev)
0170 {
0171     uint64_t value;
0172     uint32_t tmp;
0173 
0174     /* Program the AGP BAR */
0175     WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);
0176     WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
0177     WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
0178 
0179     /*
0180      * the new L1 policy will block SRIOV guest from writing
0181      * these regs, and they will be programed at host.
0182      * so skip programing these regs.
0183      */
0184     /* Program the system aperture low logical page number. */
0185     WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
0186              adev->gmc.vram_start >> 18);
0187     WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
0188              adev->gmc.vram_end >> 18);
0189 
0190     /* Set default page address. */
0191     value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
0192         adev->vm_manager.vram_base_offset;
0193     WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
0194              (u32)(value >> 12));
0195     WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
0196              (u32)(value >> 44));
0197 
0198     /* Program "protection fault". */
0199     WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
0200              (u32)(adev->dummy_page_addr >> 12));
0201     WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
0202              (u32)((u64)adev->dummy_page_addr >> 44));
0203 
0204     tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);
0205     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
0206                 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
0207     WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
0208 }
0209 
0210 static void mmhub_v3_0_1_init_tlb_regs(struct amdgpu_device *adev)
0211 {
0212     uint32_t tmp;
0213 
0214     /* Setup TLB control */
0215     tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
0216 
0217     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
0218     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
0219     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
0220                 ENABLE_ADVANCED_DRIVER_MODEL, 1);
0221     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
0222                 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
0223     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
0224     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
0225                 MTYPE, MTYPE_UC); /* UC, uncached */
0226 
0227     WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
0228 }
0229 
0230 static void mmhub_v3_0_1_init_cache_regs(struct amdgpu_device *adev)
0231 {
0232     uint32_t tmp;
0233 
0234     /* Setup L2 cache */
0235     tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
0236     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
0237     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
0238     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
0239                 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
0240     /* XXX for emulation, Refer to closed source code.*/
0241     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
0242                 0);
0243     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
0244     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
0245     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
0246     WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
0247 
0248     tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);
0249     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
0250     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
0251     WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp);
0252 
0253     tmp = regMMVM_L2_CNTL3_DEFAULT;
0254     if (adev->gmc.translate_further) {
0255         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
0256         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
0257                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
0258     } else {
0259         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
0260         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
0261                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
0262     }
0263     WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp);
0264 
0265     tmp = regMMVM_L2_CNTL4_DEFAULT;
0266     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
0267     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
0268     WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp);
0269 
0270     tmp = regMMVM_L2_CNTL5_DEFAULT;
0271     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
0272     WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp);
0273 }
0274 
0275 static void mmhub_v3_0_1_enable_system_domain(struct amdgpu_device *adev)
0276 {
0277     uint32_t tmp;
0278 
0279     tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
0280     tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
0281     tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
0282     tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
0283                 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
0284     WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp);
0285 }
0286 
0287 static void mmhub_v3_0_1_disable_identity_aperture(struct amdgpu_device *adev)
0288 {
0289     WREG32_SOC15(MMHUB, 0,
0290              regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
0291              0xFFFFFFFF);
0292     WREG32_SOC15(MMHUB, 0,
0293              regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
0294              0x0000000F);
0295 
0296     WREG32_SOC15(MMHUB, 0,
0297              regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
0298     WREG32_SOC15(MMHUB, 0,
0299              regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
0300 
0301     WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
0302              0);
0303     WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
0304              0);
0305 }
0306 
0307 static void mmhub_v3_0_1_setup_vmid_config(struct amdgpu_device *adev)
0308 {
0309     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0310     int i;
0311     uint32_t tmp;
0312 
0313     for (i = 0; i <= 14; i++) {
0314         tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i);
0315         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
0316         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
0317                     adev->vm_manager.num_level);
0318         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0319                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0320         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0321                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
0322                     1);
0323         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0324                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0325         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0326                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0327         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0328                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0329         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0330                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0331         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0332                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0333         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0334                     PAGE_TABLE_BLOCK_SIZE,
0335                     adev->vm_manager.block_size - 9);
0336         /* Send no-retry XNACK on fault to suppress VM fault storm. */
0337         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0338                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
0339                     !amdgpu_noretry);
0340         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL,
0341                     i * hub->ctx_distance, tmp);
0342         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
0343                     i * hub->ctx_addr_distance, 0);
0344         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
0345                     i * hub->ctx_addr_distance, 0);
0346         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
0347                     i * hub->ctx_addr_distance,
0348                     lower_32_bits(adev->vm_manager.max_pfn - 1));
0349         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
0350                     i * hub->ctx_addr_distance,
0351                     upper_32_bits(adev->vm_manager.max_pfn - 1));
0352     }
0353 
0354     hub->vm_cntx_cntl = tmp;
0355 }
0356 
0357 static void mmhub_v3_0_1_program_invalidation(struct amdgpu_device *adev)
0358 {
0359     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0360     unsigned i;
0361 
0362     for (i = 0; i < 18; ++i) {
0363         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
0364                     i * hub->eng_addr_distance, 0xffffffff);
0365         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
0366                     i * hub->eng_addr_distance, 0x1f);
0367     }
0368 }
0369 
0370 static int mmhub_v3_0_1_gart_enable(struct amdgpu_device *adev)
0371 {
0372     /* GART Enable. */
0373     mmhub_v3_0_1_init_gart_aperture_regs(adev);
0374     mmhub_v3_0_1_init_system_aperture_regs(adev);
0375     mmhub_v3_0_1_init_tlb_regs(adev);
0376     mmhub_v3_0_1_init_cache_regs(adev);
0377 
0378     mmhub_v3_0_1_enable_system_domain(adev);
0379     mmhub_v3_0_1_disable_identity_aperture(adev);
0380     mmhub_v3_0_1_setup_vmid_config(adev);
0381     mmhub_v3_0_1_program_invalidation(adev);
0382 
0383     return 0;
0384 }
0385 
0386 static void mmhub_v3_0_1_gart_disable(struct amdgpu_device *adev)
0387 {
0388     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0389     u32 tmp;
0390     u32 i;
0391 
0392     /* Disable all tables */
0393     for (i = 0; i < 16; i++)
0394         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL,
0395                     i * hub->ctx_distance, 0);
0396 
0397     /* Setup TLB control */
0398     tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
0399     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
0400     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
0401                 ENABLE_ADVANCED_DRIVER_MODEL, 0);
0402     WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
0403 
0404     /* Setup L2 cache */
0405     tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
0406     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
0407     WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
0408     WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0);
0409 }
0410 
0411 /**
0412  * mmhub_v3_0_1_set_fault_enable_default - update GART/VM fault handling
0413  *
0414  * @adev: amdgpu_device pointer
0415  * @value: true redirects VM faults to the default page
0416  */
0417 static void mmhub_v3_0_1_set_fault_enable_default(struct amdgpu_device *adev,
0418                           bool value)
0419 {
0420     u32 tmp;
0421 
0422     tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
0423     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0424                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0425     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0426                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0427     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0428                 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0429     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0430                 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0431     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0432                 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
0433                 value);
0434     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0435                 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0436     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0437                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0438     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0439                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0440     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0441                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0442     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0443                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0444     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0445                 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0446     if (!value) {
0447         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0448                 CRASH_ON_NO_RETRY_FAULT, 1);
0449         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0450                 CRASH_ON_RETRY_FAULT, 1);
0451     }
0452     WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
0453 }
0454 
0455 static const struct amdgpu_vmhub_funcs mmhub_v3_0_1_vmhub_funcs = {
0456     .print_l2_protection_fault_status = mmhub_v3_0_1_print_l2_protection_fault_status,
0457     .get_invalidate_req = mmhub_v3_0_1_get_invalidate_req,
0458 };
0459 
0460 static void mmhub_v3_0_1_init(struct amdgpu_device *adev)
0461 {
0462     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0463 
0464     hub->ctx0_ptb_addr_lo32 =
0465         SOC15_REG_OFFSET(MMHUB, 0,
0466                  regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
0467     hub->ctx0_ptb_addr_hi32 =
0468         SOC15_REG_OFFSET(MMHUB, 0,
0469                  regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
0470     hub->vm_inv_eng0_sem =
0471         SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM);
0472     hub->vm_inv_eng0_req =
0473         SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ);
0474     hub->vm_inv_eng0_ack =
0475         SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK);
0476     hub->vm_context0_cntl =
0477         SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
0478     hub->vm_l2_pro_fault_status =
0479         SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS);
0480     hub->vm_l2_pro_fault_cntl =
0481         SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
0482 
0483     hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL;
0484     hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
0485         regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
0486     hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ -
0487         regMMVM_INVALIDATE_ENG0_REQ;
0488     hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
0489         regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
0490 
0491     hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0492         MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0493         MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0494         MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0495         MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0496         MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0497         MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
0498 
0499     hub->vmhub_funcs = &mmhub_v3_0_1_vmhub_funcs;
0500 }
0501 
0502 static u64 mmhub_v3_0_1_get_fb_location(struct amdgpu_device *adev)
0503 {
0504     u64 base;
0505 
0506     base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);
0507     base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
0508     base <<= 24;
0509 
0510     return base;
0511 }
0512 
0513 static u64 mmhub_v3_0_1_get_mc_fb_offset(struct amdgpu_device *adev)
0514 {
0515     return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;
0516 }
0517 
0518 static void mmhub_v3_0_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
0519                               bool enable)
0520 {
0521     uint32_t def, data;
0522 
0523     def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);
0524 
0525     if (enable)
0526         data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;
0527     else
0528         data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;
0529 
0530     if (def != data)
0531         WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data);
0532 }
0533 
0534 static void mmhub_v3_0_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
0535                              bool enable)
0536 {
0537     uint32_t def, data;
0538 
0539     def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);
0540 
0541     if (enable)
0542         data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
0543     else
0544         data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
0545 
0546     if (def != data)
0547         WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data);
0548 }
0549 
0550 static int mmhub_v3_0_1_set_clockgating(struct amdgpu_device *adev,
0551                     enum amd_clockgating_state state)
0552 {
0553     if (amdgpu_sriov_vf(adev))
0554         return 0;
0555 
0556     mmhub_v3_0_1_update_medium_grain_clock_gating(adev,
0557             state == AMD_CG_STATE_GATE);
0558     mmhub_v3_0_1_update_medium_grain_light_sleep(adev,
0559             state == AMD_CG_STATE_GATE);
0560     return 0;
0561 }
0562 
0563 static void mmhub_v3_0_1_get_clockgating(struct amdgpu_device *adev, u64 *flags)
0564 {
0565     int data;
0566 
0567     if (amdgpu_sriov_vf(adev))
0568         *flags = 0;
0569 
0570     data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);
0571 
0572     /* AMD_CG_SUPPORT_MC_MGCG */
0573     if (data & MM_ATC_L2_MISC_CG__ENABLE_MASK)
0574         *flags |= AMD_CG_SUPPORT_MC_MGCG;
0575 
0576     /* AMD_CG_SUPPORT_MC_LS */
0577     if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
0578         *flags |= AMD_CG_SUPPORT_MC_LS;
0579 }
0580 
0581 const struct amdgpu_mmhub_funcs mmhub_v3_0_1_funcs = {
0582     .init = mmhub_v3_0_1_init,
0583     .get_fb_location = mmhub_v3_0_1_get_fb_location,
0584     .get_mc_fb_offset = mmhub_v3_0_1_get_mc_fb_offset,
0585     .gart_enable = mmhub_v3_0_1_gart_enable,
0586     .set_fault_enable_default = mmhub_v3_0_1_set_fault_enable_default,
0587     .gart_disable = mmhub_v3_0_1_gart_disable,
0588     .set_clockgating = mmhub_v3_0_1_set_clockgating,
0589     .get_clockgating = mmhub_v3_0_1_get_clockgating,
0590     .setup_vm_pt_regs = mmhub_v3_0_1_setup_vm_pt_regs,
0591 };
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