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0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #include "amdgpu.h"
0025 #include "mmhub_v3_0.h"
0026 
0027 #include "mmhub/mmhub_3_0_0_offset.h"
0028 #include "mmhub/mmhub_3_0_0_sh_mask.h"
0029 #include "navi10_enum.h"
0030 
0031 #include "soc15_common.h"
0032 
0033 #define regMMVM_L2_CNTL3_DEFAULT                0x80100007
0034 #define regMMVM_L2_CNTL4_DEFAULT                0x000000c1
0035 #define regMMVM_L2_CNTL5_DEFAULT                0x00003fe0
0036 
0037 static const char *mmhub_client_ids_v3_0_0[][2] = {
0038     [0][0] = "VMC",
0039     [4][0] = "DCEDMC",
0040     [5][0] = "DCEVGA",
0041     [6][0] = "MP0",
0042     [7][0] = "MP1",
0043     [8][0] = "MPIO",
0044     [16][0] = "HDP",
0045     [17][0] = "LSDMA",
0046     [18][0] = "JPEG",
0047     [19][0] = "VCNU0",
0048     [21][0] = "VSCH",
0049     [22][0] = "VCNU1",
0050     [23][0] = "VCN1",
0051     [32+20][0] = "VCN0",
0052     [2][1] = "DBGUNBIO",
0053     [3][1] = "DCEDWB",
0054     [4][1] = "DCEDMC",
0055     [5][1] = "DCEVGA",
0056     [6][1] = "MP0",
0057     [7][1] = "MP1",
0058     [8][1] = "MPIO",
0059     [10][1] = "DBGU0",
0060     [11][1] = "DBGU1",
0061     [12][1] = "DBGU2",
0062     [13][1] = "DBGU3",
0063     [14][1] = "XDP",
0064     [15][1] = "OSSSYS",
0065     [16][1] = "HDP",
0066     [17][1] = "LSDMA",
0067     [18][1] = "JPEG",
0068     [19][1] = "VCNU0",
0069     [20][1] = "VCN0",
0070     [21][1] = "VSCH",
0071     [22][1] = "VCNU1",
0072     [23][1] = "VCN1",
0073 };
0074 
0075 static uint32_t mmhub_v3_0_get_invalidate_req(unsigned int vmid,
0076                           uint32_t flush_type)
0077 {
0078     u32 req = 0;
0079 
0080     /* invalidate using legacy mode on vmid*/
0081     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
0082                 PER_VMID_INVALIDATE_REQ, 1 << vmid);
0083     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
0084     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
0085     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
0086     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
0087     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
0088     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
0089     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
0090                 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
0091 
0092     return req;
0093 }
0094 
0095 static void
0096 mmhub_v3_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
0097                          uint32_t status)
0098 {
0099     uint32_t cid, rw;
0100     const char *mmhub_cid = NULL;
0101 
0102     cid = REG_GET_FIELD(status,
0103                 MMVM_L2_PROTECTION_FAULT_STATUS, CID);
0104     rw = REG_GET_FIELD(status,
0105                MMVM_L2_PROTECTION_FAULT_STATUS, RW);
0106 
0107     dev_err(adev->dev,
0108         "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
0109         status);
0110     switch (adev->ip_versions[MMHUB_HWIP][0]) {
0111     case IP_VERSION(3, 0, 0):
0112     case IP_VERSION(3, 0, 1):
0113         mmhub_cid = mmhub_client_ids_v3_0_0[cid][rw];
0114         break;
0115     default:
0116         mmhub_cid = NULL;
0117         break;
0118     }
0119     dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
0120         mmhub_cid ? mmhub_cid : "unknown", cid);
0121     dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
0122         REG_GET_FIELD(status,
0123         MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
0124     dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
0125         REG_GET_FIELD(status,
0126         MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
0127     dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
0128         REG_GET_FIELD(status,
0129         MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
0130     dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
0131         REG_GET_FIELD(status,
0132         MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
0133     dev_err(adev->dev, "\t RW: 0x%x\n", rw);
0134 }
0135 
0136 static void mmhub_v3_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
0137                 uint64_t page_table_base)
0138 {
0139     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0140 
0141     WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
0142                 hub->ctx_addr_distance * vmid,
0143                 lower_32_bits(page_table_base));
0144 
0145     WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
0146                 hub->ctx_addr_distance * vmid,
0147                 upper_32_bits(page_table_base));
0148 }
0149 
0150 static void mmhub_v3_0_init_gart_aperture_regs(struct amdgpu_device *adev)
0151 {
0152     uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
0153 
0154     mmhub_v3_0_setup_vm_pt_regs(adev, 0, pt_base);
0155 
0156     WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
0157              (u32)(adev->gmc.gart_start >> 12));
0158     WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
0159              (u32)(adev->gmc.gart_start >> 44));
0160 
0161     WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
0162              (u32)(adev->gmc.gart_end >> 12));
0163     WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
0164              (u32)(adev->gmc.gart_end >> 44));
0165 }
0166 
0167 static void mmhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev)
0168 {
0169     uint64_t value;
0170     uint32_t tmp;
0171 
0172     /* Disable AGP. */
0173     WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BASE, 0);
0174     WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_TOP, 0);
0175     WREG32_SOC15(MMHUB, 0, regMMMC_VM_AGP_BOT, 0x00FFFFFF);
0176 
0177     if (!amdgpu_sriov_vf(adev)) {
0178         /*
0179          * the new L1 policy will block SRIOV guest from writing
0180          * these regs, and they will be programed at host.
0181          * so skip programing these regs.
0182          */
0183         /* Program the system aperture low logical page number. */
0184         WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
0185                  adev->gmc.vram_start >> 18);
0186         WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
0187                  adev->gmc.vram_end >> 18);
0188     }
0189 
0190     /* Set default page address. */
0191     value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
0192         adev->vm_manager.vram_base_offset;
0193     WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
0194              (u32)(value >> 12));
0195     WREG32_SOC15(MMHUB, 0, regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
0196              (u32)(value >> 44));
0197 
0198     /* Program "protection fault". */
0199     WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
0200              (u32)(adev->dummy_page_addr >> 12));
0201     WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
0202              (u32)((u64)adev->dummy_page_addr >> 44));
0203 
0204     tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2);
0205     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
0206                 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
0207     WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
0208 }
0209 
0210 static void mmhub_v3_0_init_tlb_regs(struct amdgpu_device *adev)
0211 {
0212     uint32_t tmp;
0213 
0214     /* Setup TLB control */
0215     tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
0216 
0217     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
0218     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
0219     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
0220                 ENABLE_ADVANCED_DRIVER_MODEL, 1);
0221     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
0222                 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
0223     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
0224     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
0225                 MTYPE, MTYPE_UC); /* UC, uncached */
0226 
0227     WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
0228 }
0229 
0230 static void mmhub_v3_0_init_cache_regs(struct amdgpu_device *adev)
0231 {
0232     uint32_t tmp;
0233 
0234     /* These registers are not accessible to VF-SRIOV.
0235      * The PF will program them instead.
0236      */
0237     if (amdgpu_sriov_vf(adev))
0238         return;
0239 
0240     /* Setup L2 cache */
0241     tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
0242     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
0243     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
0244     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
0245                 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
0246     /* XXX for emulation, Refer to closed source code.*/
0247     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
0248                 0);
0249     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
0250     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
0251     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
0252     WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
0253 
0254     tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2);
0255     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
0256     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
0257     WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL2, tmp);
0258 
0259     tmp = regMMVM_L2_CNTL3_DEFAULT;
0260     if (adev->gmc.translate_further) {
0261         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
0262         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
0263                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
0264     } else {
0265         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
0266         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
0267                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
0268     }
0269     WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, tmp);
0270 
0271     tmp = regMMVM_L2_CNTL4_DEFAULT;
0272     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
0273     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
0274     WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL4, tmp);
0275 
0276     tmp = regMMVM_L2_CNTL5_DEFAULT;
0277     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
0278     WREG32_SOC15(GC, 0, regMMVM_L2_CNTL5, tmp);
0279 }
0280 
0281 static void mmhub_v3_0_enable_system_domain(struct amdgpu_device *adev)
0282 {
0283     uint32_t tmp;
0284 
0285     tmp = RREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
0286     tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
0287     tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
0288     tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
0289                 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
0290     WREG32_SOC15(MMHUB, 0, regMMVM_CONTEXT0_CNTL, tmp);
0291 }
0292 
0293 static void mmhub_v3_0_disable_identity_aperture(struct amdgpu_device *adev)
0294 {
0295     /* These registers are not accessible to VF-SRIOV.
0296      * The PF will program them instead.
0297      */
0298     if (amdgpu_sriov_vf(adev))
0299         return;
0300 
0301     WREG32_SOC15(MMHUB, 0,
0302              regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
0303              0xFFFFFFFF);
0304     WREG32_SOC15(MMHUB, 0,
0305              regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
0306              0x0000000F);
0307 
0308     WREG32_SOC15(MMHUB, 0,
0309              regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
0310     WREG32_SOC15(MMHUB, 0,
0311              regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
0312 
0313     WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
0314              0);
0315     WREG32_SOC15(MMHUB, 0, regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
0316              0);
0317 }
0318 
0319 static void mmhub_v3_0_setup_vmid_config(struct amdgpu_device *adev)
0320 {
0321     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0322     int i;
0323     uint32_t tmp;
0324 
0325     for (i = 0; i <= 14; i++) {
0326         tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i);
0327         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
0328         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
0329                     adev->vm_manager.num_level);
0330         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0331                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0332         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0333                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
0334                     1);
0335         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0336                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0337         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0338                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0339         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0340                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0341         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0342                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0343         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0344                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0345         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0346                     PAGE_TABLE_BLOCK_SIZE,
0347                     adev->vm_manager.block_size - 9);
0348         /* Send no-retry XNACK on fault to suppress VM fault storm. */
0349         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0350                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
0351                     !amdgpu_noretry);
0352         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL,
0353                     i * hub->ctx_distance, tmp);
0354         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
0355                     i * hub->ctx_addr_distance, 0);
0356         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
0357                     i * hub->ctx_addr_distance, 0);
0358         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
0359                     i * hub->ctx_addr_distance,
0360                     lower_32_bits(adev->vm_manager.max_pfn - 1));
0361         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
0362                     i * hub->ctx_addr_distance,
0363                     upper_32_bits(adev->vm_manager.max_pfn - 1));
0364     }
0365 
0366     hub->vm_cntx_cntl = tmp;
0367 }
0368 
0369 static void mmhub_v3_0_program_invalidation(struct amdgpu_device *adev)
0370 {
0371     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0372     unsigned i;
0373 
0374     for (i = 0; i < 18; ++i) {
0375         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
0376                     i * hub->eng_addr_distance, 0xffffffff);
0377         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
0378                     i * hub->eng_addr_distance, 0x1f);
0379     }
0380 }
0381 
0382 static int mmhub_v3_0_gart_enable(struct amdgpu_device *adev)
0383 {
0384     /* GART Enable. */
0385     mmhub_v3_0_init_gart_aperture_regs(adev);
0386     mmhub_v3_0_init_system_aperture_regs(adev);
0387     mmhub_v3_0_init_tlb_regs(adev);
0388     mmhub_v3_0_init_cache_regs(adev);
0389 
0390     mmhub_v3_0_enable_system_domain(adev);
0391     mmhub_v3_0_disable_identity_aperture(adev);
0392     mmhub_v3_0_setup_vmid_config(adev);
0393     mmhub_v3_0_program_invalidation(adev);
0394 
0395     return 0;
0396 }
0397 
0398 static void mmhub_v3_0_gart_disable(struct amdgpu_device *adev)
0399 {
0400     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0401     u32 tmp;
0402     u32 i;
0403 
0404     /* Disable all tables */
0405     for (i = 0; i < 16; i++)
0406         WREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL,
0407                     i * hub->ctx_distance, 0);
0408 
0409     /* Setup TLB control */
0410     tmp = RREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL);
0411     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
0412     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
0413                 ENABLE_ADVANCED_DRIVER_MODEL, 0);
0414     WREG32_SOC15(MMHUB, 0, regMMMC_VM_MX_L1_TLB_CNTL, tmp);
0415 
0416     /* Setup L2 cache */
0417     tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL);
0418     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
0419     WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL, tmp);
0420     WREG32_SOC15(MMHUB, 0, regMMVM_L2_CNTL3, 0);
0421 }
0422 
0423 /**
0424  * mmhub_v3_0_set_fault_enable_default - update GART/VM fault handling
0425  *
0426  * @adev: amdgpu_device pointer
0427  * @value: true redirects VM faults to the default page
0428  */
0429 static void mmhub_v3_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
0430 {
0431     u32 tmp;
0432 
0433     /* These registers are not accessible to VF-SRIOV.
0434      * The PF will program them instead.
0435      */
0436     if (amdgpu_sriov_vf(adev))
0437         return;
0438 
0439     tmp = RREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
0440     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0441                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0442     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0443                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0444     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0445                 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0446     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0447                 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0448     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0449                 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
0450                 value);
0451     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0452                 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0453     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0454                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0455     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0456                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0457     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0458                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0459     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0460                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0461     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0462                 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0463     if (!value) {
0464         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0465                 CRASH_ON_NO_RETRY_FAULT, 1);
0466         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0467                 CRASH_ON_RETRY_FAULT, 1);
0468     }
0469     WREG32_SOC15(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
0470 }
0471 
0472 static const struct amdgpu_vmhub_funcs mmhub_v3_0_vmhub_funcs = {
0473     .print_l2_protection_fault_status = mmhub_v3_0_print_l2_protection_fault_status,
0474     .get_invalidate_req = mmhub_v3_0_get_invalidate_req,
0475 };
0476 
0477 static void mmhub_v3_0_init(struct amdgpu_device *adev)
0478 {
0479     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0480 
0481     hub->ctx0_ptb_addr_lo32 =
0482         SOC15_REG_OFFSET(MMHUB, 0,
0483                  regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
0484     hub->ctx0_ptb_addr_hi32 =
0485         SOC15_REG_OFFSET(MMHUB, 0,
0486                  regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
0487     hub->vm_inv_eng0_sem =
0488         SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_SEM);
0489     hub->vm_inv_eng0_req =
0490         SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_REQ);
0491     hub->vm_inv_eng0_ack =
0492         SOC15_REG_OFFSET(MMHUB, 0, regMMVM_INVALIDATE_ENG0_ACK);
0493     hub->vm_context0_cntl =
0494         SOC15_REG_OFFSET(MMHUB, 0, regMMVM_CONTEXT0_CNTL);
0495     hub->vm_l2_pro_fault_status =
0496         SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_STATUS);
0497     hub->vm_l2_pro_fault_cntl =
0498         SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_PROTECTION_FAULT_CNTL);
0499 
0500     hub->ctx_distance = regMMVM_CONTEXT1_CNTL - regMMVM_CONTEXT0_CNTL;
0501     hub->ctx_addr_distance = regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
0502         regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
0503     hub->eng_distance = regMMVM_INVALIDATE_ENG1_REQ -
0504         regMMVM_INVALIDATE_ENG0_REQ;
0505     hub->eng_addr_distance = regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
0506         regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
0507 
0508     hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0509         MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0510         MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0511         MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0512         MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0513         MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0514         MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
0515 
0516     hub->vm_l2_bank_select_reserved_cid2 =
0517         SOC15_REG_OFFSET(MMHUB, 0, regMMVM_L2_BANK_SELECT_RESERVED_CID2);
0518 
0519     hub->vmhub_funcs = &mmhub_v3_0_vmhub_funcs;
0520 }
0521 
0522 static u64 mmhub_v3_0_get_fb_location(struct amdgpu_device *adev)
0523 {
0524     u64 base;
0525 
0526     base = RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_LOCATION_BASE);
0527 
0528     base &= MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
0529     base <<= 24;
0530 
0531     return base;
0532 }
0533 
0534 static u64 mmhub_v3_0_get_mc_fb_offset(struct amdgpu_device *adev)
0535 {
0536     return (u64)RREG32_SOC15(MMHUB, 0, regMMMC_VM_FB_OFFSET) << 24;
0537 }
0538 
0539 static void mmhub_v3_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
0540                             bool enable)
0541 {
0542     uint32_t def, data;
0543 #if 0
0544     uint32_t def1, data1, def2 = 0, data2 = 0;
0545 #endif
0546 
0547     def  = data  = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);
0548 #if 0
0549     def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2);
0550     def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2);
0551 #endif
0552 
0553     if (enable) {
0554         data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;
0555 #if 0
0556         data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
0557                    DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
0558                    DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
0559                    DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
0560                    DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
0561                    DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
0562 
0563         data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
0564                    DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
0565                    DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
0566                    DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
0567                    DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
0568                    DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
0569 #endif
0570     } else {
0571         data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;
0572 #if 0
0573         data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
0574               DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
0575               DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
0576               DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
0577               DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
0578               DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
0579 
0580         data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
0581                   DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
0582                   DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
0583                   DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
0584                   DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
0585                   DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
0586 #endif
0587     }
0588 
0589     if (def != data)
0590         WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data);
0591 #if 0
0592     if (def1 != data1)
0593         WREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2, data1);
0594 
0595     if (def2 != data2)
0596         WREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2, data2);
0597 #endif
0598 }
0599 
0600 static void mmhub_v3_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
0601                                bool enable)
0602 {
0603     uint32_t def, data;
0604 
0605     def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);
0606 
0607     if (enable)
0608         data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
0609     else
0610         data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
0611 
0612     if (def != data)
0613         WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data);
0614 }
0615 
0616 static int mmhub_v3_0_set_clockgating(struct amdgpu_device *adev,
0617                    enum amd_clockgating_state state)
0618 {
0619     if (amdgpu_sriov_vf(adev))
0620         return 0;
0621 
0622     if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)
0623         mmhub_v3_0_update_medium_grain_clock_gating(adev,
0624                 state == AMD_CG_STATE_GATE);
0625 
0626     if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)
0627         mmhub_v3_0_update_medium_grain_light_sleep(adev,
0628                 state == AMD_CG_STATE_GATE);
0629 
0630     return 0;
0631 }
0632 
0633 static void mmhub_v3_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)
0634 {
0635     int data;
0636 
0637     if (amdgpu_sriov_vf(adev))
0638         *flags = 0;
0639 
0640     data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);
0641 
0642     /* AMD_CG_SUPPORT_MC_MGCG */
0643     if (data & MM_ATC_L2_MISC_CG__ENABLE_MASK)
0644         *flags |= AMD_CG_SUPPORT_MC_MGCG;
0645 
0646     /* AMD_CG_SUPPORT_MC_LS */
0647     if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
0648         *flags |= AMD_CG_SUPPORT_MC_LS;
0649 }
0650 
0651 const struct amdgpu_mmhub_funcs mmhub_v3_0_funcs = {
0652     .init = mmhub_v3_0_init,
0653     .get_fb_location = mmhub_v3_0_get_fb_location,
0654     .get_mc_fb_offset = mmhub_v3_0_get_mc_fb_offset,
0655     .gart_enable = mmhub_v3_0_gart_enable,
0656     .set_fault_enable_default = mmhub_v3_0_set_fault_enable_default,
0657     .gart_disable = mmhub_v3_0_gart_disable,
0658     .set_clockgating = mmhub_v3_0_set_clockgating,
0659     .get_clockgating = mmhub_v3_0_get_clockgating,
0660     .setup_vm_pt_regs = mmhub_v3_0_setup_vm_pt_regs,
0661 };
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