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OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #include "amdgpu.h"
0025 #include "mmhub_v2_3.h"
0026 
0027 #include "mmhub/mmhub_2_3_0_offset.h"
0028 #include "mmhub/mmhub_2_3_0_sh_mask.h"
0029 #include "mmhub/mmhub_2_3_0_default.h"
0030 #include "navi10_enum.h"
0031 
0032 #include "soc15_common.h"
0033 
0034 static const char *mmhub_client_ids_vangogh[][2] = {
0035     [0][0] = "MP0",
0036     [1][0] = "MP1",
0037     [2][0] = "DCEDMC",
0038     [3][0] = "DCEVGA",
0039     [13][0] = "UTCL2",
0040     [26][0] = "OSS",
0041     [27][0] = "HDP",
0042     [28][0] = "VCN",
0043     [29][0] = "VCNU",
0044     [30][0] = "JPEG",
0045     [0][1] = "MP0",
0046     [1][1] = "MP1",
0047     [2][1] = "DCEDMC",
0048     [3][1] = "DCEVGA",
0049     [4][1] = "DCEDWB",
0050     [5][1] = "XDP",
0051     [26][1] = "OSS",
0052     [27][1] = "HDP",
0053     [28][1] = "VCN",
0054     [29][1] = "VCNU",
0055     [30][1] = "JPEG",
0056 };
0057 
0058 static uint32_t mmhub_v2_3_get_invalidate_req(unsigned int vmid,
0059                           uint32_t flush_type)
0060 {
0061     u32 req = 0;
0062 
0063     /* invalidate using legacy mode on vmid*/
0064     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
0065                 PER_VMID_INVALIDATE_REQ, 1 << vmid);
0066     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
0067     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
0068     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
0069     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
0070     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
0071     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
0072     req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
0073                 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
0074 
0075     return req;
0076 }
0077 
0078 static void
0079 mmhub_v2_3_print_l2_protection_fault_status(struct amdgpu_device *adev,
0080                          uint32_t status)
0081 {
0082     uint32_t cid, rw;
0083     const char *mmhub_cid = NULL;
0084 
0085     cid = REG_GET_FIELD(status,
0086                 MMVM_L2_PROTECTION_FAULT_STATUS, CID);
0087     rw = REG_GET_FIELD(status,
0088                MMVM_L2_PROTECTION_FAULT_STATUS, RW);
0089 
0090     dev_err(adev->dev,
0091         "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
0092         status);
0093     switch (adev->ip_versions[MMHUB_HWIP][0]) {
0094     case IP_VERSION(2, 3, 0):
0095     case IP_VERSION(2, 4, 0):
0096     case IP_VERSION(2, 4, 1):
0097         mmhub_cid = mmhub_client_ids_vangogh[cid][rw];
0098         break;
0099     default:
0100         mmhub_cid = NULL;
0101         break;
0102     }
0103     dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
0104         mmhub_cid ? mmhub_cid : "unknown", cid);
0105     dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
0106         REG_GET_FIELD(status,
0107         MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
0108     dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
0109         REG_GET_FIELD(status,
0110         MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
0111     dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
0112         REG_GET_FIELD(status,
0113         MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
0114     dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
0115         REG_GET_FIELD(status,
0116         MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
0117     dev_err(adev->dev, "\t RW: 0x%x\n", rw);
0118 }
0119 
0120 static void mmhub_v2_3_setup_vm_pt_regs(struct amdgpu_device *adev,
0121                     uint32_t vmid,
0122                     uint64_t page_table_base)
0123 {
0124     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0125 
0126     WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
0127                 hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base));
0128 
0129     WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
0130                 hub->ctx_addr_distance * vmid, upper_32_bits(page_table_base));
0131 }
0132 
0133 static void mmhub_v2_3_init_gart_aperture_regs(struct amdgpu_device *adev)
0134 {
0135     uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
0136 
0137     mmhub_v2_3_setup_vm_pt_regs(adev, 0, pt_base);
0138 
0139     WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
0140              (u32)(adev->gmc.gart_start >> 12));
0141     WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
0142              (u32)(adev->gmc.gart_start >> 44));
0143 
0144     WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
0145              (u32)(adev->gmc.gart_end >> 12));
0146     WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
0147              (u32)(adev->gmc.gart_end >> 44));
0148 }
0149 
0150 static void mmhub_v2_3_init_system_aperture_regs(struct amdgpu_device *adev)
0151 {
0152     uint64_t value;
0153     uint32_t tmp;
0154 
0155     /* Disable AGP. */
0156     WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
0157     WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
0158     WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
0159 
0160     /* Program the system aperture low logical page number. */
0161     WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
0162              min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
0163     WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
0164              max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
0165 
0166     /* Set default page address. */
0167     value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
0168     WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
0169              (u32)(value >> 12));
0170     WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
0171              (u32)(value >> 44));
0172 
0173     /* Program "protection fault". */
0174     WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
0175              (u32)(adev->dummy_page_addr >> 12));
0176     WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
0177              (u32)((u64)adev->dummy_page_addr >> 44));
0178 
0179     tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2);
0180     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
0181                 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
0182     WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
0183 }
0184 
0185 static void mmhub_v2_3_init_tlb_regs(struct amdgpu_device *adev)
0186 {
0187     uint32_t tmp;
0188 
0189     /* Setup TLB control */
0190     tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
0191 
0192     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
0193     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
0194     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
0195                 ENABLE_ADVANCED_DRIVER_MODEL, 1);
0196     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
0197                 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
0198     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
0199                 MTYPE, MTYPE_UC); /* UC, uncached */
0200 
0201     WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
0202 }
0203 
0204 static void mmhub_v2_3_init_cache_regs(struct amdgpu_device *adev)
0205 {
0206     uint32_t tmp;
0207 
0208     /* Setup L2 cache */
0209     tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
0210     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
0211     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
0212     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
0213                 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
0214     /* XXX for emulation, Refer to closed source code.*/
0215     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
0216                 0);
0217     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
0218     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
0219     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
0220     WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
0221 
0222     tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2);
0223     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
0224     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
0225     WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);
0226 
0227     tmp = mmMMVM_L2_CNTL3_DEFAULT;
0228     if (adev->gmc.translate_further) {
0229         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
0230         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
0231                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
0232     } else {
0233         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
0234         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
0235                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
0236     }
0237     WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);
0238 
0239     tmp = mmMMVM_L2_CNTL4_DEFAULT;
0240     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
0241     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
0242     WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp);
0243 
0244     tmp = mmMMVM_L2_CNTL5_DEFAULT;
0245     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
0246     WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp);
0247 }
0248 
0249 static void mmhub_v2_3_enable_system_domain(struct amdgpu_device *adev)
0250 {
0251     uint32_t tmp;
0252 
0253     tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
0254     tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
0255     tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
0256     tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
0257                 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
0258     WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
0259 }
0260 
0261 static void mmhub_v2_3_disable_identity_aperture(struct amdgpu_device *adev)
0262 {
0263     WREG32_SOC15(MMHUB, 0,
0264              mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
0265              0xFFFFFFFF);
0266     WREG32_SOC15(MMHUB, 0,
0267              mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
0268              0x0000000F);
0269 
0270     WREG32_SOC15(MMHUB, 0,
0271              mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
0272     WREG32_SOC15(MMHUB, 0,
0273              mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
0274 
0275     WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
0276              0);
0277     WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
0278              0);
0279 }
0280 
0281 static void mmhub_v2_3_setup_vmid_config(struct amdgpu_device *adev)
0282 {
0283     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0284     int i;
0285     uint32_t tmp;
0286 
0287     for (i = 0; i <= 14; i++) {
0288         tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i);
0289         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
0290         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
0291                     adev->vm_manager.num_level);
0292         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0293                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0294         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0295                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
0296                     1);
0297         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0298                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0299         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0300                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0301         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0302                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0303         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0304                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0305         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0306                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0307         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0308                     PAGE_TABLE_BLOCK_SIZE,
0309                     adev->vm_manager.block_size - 9);
0310         /* Send no-retry XNACK on fault to suppress VM fault storm. */
0311         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
0312                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
0313                     !adev->gmc.noretry);
0314         WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL,
0315                     i * hub->ctx_distance, tmp);
0316         WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
0317                     i * hub->ctx_addr_distance, 0);
0318         WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
0319                     i * hub->ctx_addr_distance, 0);
0320         WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
0321                     i * hub->ctx_addr_distance,
0322                     lower_32_bits(adev->vm_manager.max_pfn - 1));
0323         WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
0324                     i * hub->ctx_addr_distance,
0325                     upper_32_bits(adev->vm_manager.max_pfn - 1));
0326     }
0327 
0328     hub->vm_cntx_cntl = tmp;
0329 }
0330 
0331 static void mmhub_v2_3_program_invalidation(struct amdgpu_device *adev)
0332 {
0333     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0334     unsigned i;
0335 
0336     for (i = 0; i < 18; ++i) {
0337         WREG32_SOC15_OFFSET(MMHUB, 0,
0338                     mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
0339                     i * hub->eng_addr_distance, 0xffffffff);
0340         WREG32_SOC15_OFFSET(MMHUB, 0,
0341                     mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
0342                     i * hub->eng_addr_distance, 0x1f);
0343     }
0344 }
0345 
0346 static int mmhub_v2_3_gart_enable(struct amdgpu_device *adev)
0347 {
0348     if (amdgpu_sriov_vf(adev)) {
0349         /*
0350          * MMMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
0351          * VF copy registers so vbios post doesn't program them, for
0352          * SRIOV driver need to program them
0353          */
0354         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_BASE,
0355                  adev->gmc.vram_start >> 24);
0356         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_FB_LOCATION_TOP,
0357                  adev->gmc.vram_end >> 24);
0358     }
0359 
0360     /* GART Enable. */
0361     mmhub_v2_3_init_gart_aperture_regs(adev);
0362     mmhub_v2_3_init_system_aperture_regs(adev);
0363     mmhub_v2_3_init_tlb_regs(adev);
0364     mmhub_v2_3_init_cache_regs(adev);
0365 
0366     mmhub_v2_3_enable_system_domain(adev);
0367     mmhub_v2_3_disable_identity_aperture(adev);
0368     mmhub_v2_3_setup_vmid_config(adev);
0369     mmhub_v2_3_program_invalidation(adev);
0370 
0371     return 0;
0372 }
0373 
0374 static void mmhub_v2_3_gart_disable(struct amdgpu_device *adev)
0375 {
0376     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0377     u32 tmp;
0378     u32 i;
0379 
0380     /* Disable all tables */
0381     for (i = 0; i < AMDGPU_NUM_VMID; i++)
0382         WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL,
0383                     i * hub->ctx_distance, 0);
0384 
0385     /* Setup TLB control */
0386     tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
0387     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
0388     tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
0389                 ENABLE_ADVANCED_DRIVER_MODEL, 0);
0390     WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
0391 
0392     /* Setup L2 cache */
0393     tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
0394     tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
0395     WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
0396     WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0);
0397 }
0398 
0399 /**
0400  * mmhub_v2_3_set_fault_enable_default - update GART/VM fault handling
0401  *
0402  * @adev: amdgpu_device pointer
0403  * @value: true redirects VM faults to the default page
0404  */
0405 static void mmhub_v2_3_set_fault_enable_default(struct amdgpu_device *adev,
0406                         bool value)
0407 {
0408     u32 tmp;
0409     tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
0410     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0411                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0412     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0413                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0414     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0415                 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0416     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0417                 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0418     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0419                 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
0420                 value);
0421     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0422                 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0423     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0424                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0425     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0426                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0427     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0428                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0429     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0430                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0431     tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0432                 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0433     if (!value) {
0434         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0435                 CRASH_ON_NO_RETRY_FAULT, 1);
0436         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
0437                 CRASH_ON_RETRY_FAULT, 1);
0438     }
0439     WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
0440 }
0441 
0442 static const struct amdgpu_vmhub_funcs mmhub_v2_3_vmhub_funcs = {
0443     .print_l2_protection_fault_status = mmhub_v2_3_print_l2_protection_fault_status,
0444     .get_invalidate_req = mmhub_v2_3_get_invalidate_req,
0445 };
0446 
0447 static void mmhub_v2_3_init(struct amdgpu_device *adev)
0448 {
0449     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0450 
0451     hub->ctx0_ptb_addr_lo32 =
0452         SOC15_REG_OFFSET(MMHUB, 0,
0453                  mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
0454     hub->ctx0_ptb_addr_hi32 =
0455         SOC15_REG_OFFSET(MMHUB, 0,
0456                  mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
0457     hub->vm_inv_eng0_sem =
0458         SOC15_REG_OFFSET(MMHUB, 0,
0459                  mmMMVM_INVALIDATE_ENG0_SEM);
0460     hub->vm_inv_eng0_req =
0461         SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ);
0462     hub->vm_inv_eng0_ack =
0463         SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK);
0464     hub->vm_context0_cntl =
0465         SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
0466     hub->vm_l2_pro_fault_status =
0467         SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS);
0468     hub->vm_l2_pro_fault_cntl =
0469         SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
0470 
0471     hub->ctx_distance = mmMMVM_CONTEXT1_CNTL - mmMMVM_CONTEXT0_CNTL;
0472     hub->ctx_addr_distance = mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
0473         mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
0474     hub->eng_distance = mmMMVM_INVALIDATE_ENG1_REQ -
0475         mmMMVM_INVALIDATE_ENG0_REQ;
0476     hub->eng_addr_distance = mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
0477         mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
0478 
0479     hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0480         MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0481         MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0482         MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0483         MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0484         MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0485         MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
0486 
0487     hub->vmhub_funcs = &mmhub_v2_3_vmhub_funcs;
0488 }
0489 
0490 static void
0491 mmhub_v2_3_update_medium_grain_clock_gating(struct amdgpu_device *adev,
0492                         bool enable)
0493 {
0494     uint32_t def, data, def1, data1;
0495 
0496     def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL);
0497     def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
0498 
0499     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
0500         data &= ~MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK;
0501         data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
0502                    DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
0503                    DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
0504                    DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
0505                    DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
0506                    DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
0507 
0508     } else {
0509         data |= MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK;
0510         data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
0511               DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
0512               DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
0513               DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
0514               DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
0515               DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
0516     }
0517 
0518     if (def != data)
0519         WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL, data);
0520     if (def1 != data1)
0521         WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
0522 }
0523 
0524 static void
0525 mmhub_v2_3_update_medium_grain_light_sleep(struct amdgpu_device *adev,
0526                        bool enable)
0527 {
0528     uint32_t def, data, def1, data1, def2, data2;
0529 
0530     def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL);
0531     def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_WR_CGTT_CLK_CTRL);
0532     def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB0_RD_CGTT_CLK_CTRL);
0533 
0534     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
0535         data &= ~MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK;
0536         data1 &= ~(DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
0537             DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
0538             DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
0539             DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
0540             DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK);
0541         data2 &= ~(DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
0542             DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
0543             DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
0544             DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
0545             DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK);
0546     } else {
0547         data |= MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK;
0548         data1 |= (DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
0549             DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
0550             DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
0551             DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
0552             DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK);
0553         data2 |= (DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
0554             DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
0555             DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
0556             DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
0557             DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK);
0558     }
0559 
0560     if (def != data)
0561         WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL, data);
0562     if (def1 != data1)
0563         WREG32_SOC15(MMHUB, 0, mmDAGB0_WR_CGTT_CLK_CTRL, data1);
0564     if (def2 != data2)
0565         WREG32_SOC15(MMHUB, 0, mmDAGB0_RD_CGTT_CLK_CTRL, data2);
0566 }
0567 
0568 static int mmhub_v2_3_set_clockgating(struct amdgpu_device *adev,
0569                       enum amd_clockgating_state state)
0570 {
0571     if (amdgpu_sriov_vf(adev))
0572         return 0;
0573 
0574     mmhub_v2_3_update_medium_grain_clock_gating(adev,
0575                 state == AMD_CG_STATE_GATE);
0576     mmhub_v2_3_update_medium_grain_light_sleep(adev,
0577                 state == AMD_CG_STATE_GATE);
0578 
0579     return 0;
0580 }
0581 
0582 static void mmhub_v2_3_get_clockgating(struct amdgpu_device *adev, u64 *flags)
0583 {
0584     int data, data1, data2, data3;
0585 
0586     if (amdgpu_sriov_vf(adev))
0587         *flags = 0;
0588 
0589     data = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
0590     data1  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_CGTT_CLK_CTRL);
0591     data2 = RREG32_SOC15(MMHUB, 0, mmDAGB0_WR_CGTT_CLK_CTRL);
0592     data3 = RREG32_SOC15(MMHUB, 0, mmDAGB0_RD_CGTT_CLK_CTRL);
0593 
0594     /* AMD_CG_SUPPORT_MC_MGCG */
0595     if (!(data & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
0596                DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
0597                DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
0598                DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
0599                DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
0600                DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK))
0601         && !(data1 & MM_ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK)) {
0602             *flags |= AMD_CG_SUPPORT_MC_MGCG;
0603     }
0604 
0605     /* AMD_CG_SUPPORT_MC_LS */
0606     if (!(data1 & MM_ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK)
0607         && !(data2 & (DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
0608                 DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
0609                 DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
0610                 DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
0611                 DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK))
0612         && !(data3 & (DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK |
0613                 DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK |
0614                 DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK |
0615                 DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK |
0616                 DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK)))
0617         *flags |= AMD_CG_SUPPORT_MC_LS;
0618 }
0619 
0620 const struct amdgpu_mmhub_funcs mmhub_v2_3_funcs = {
0621     .init = mmhub_v2_3_init,
0622     .gart_enable = mmhub_v2_3_gart_enable,
0623     .set_fault_enable_default = mmhub_v2_3_set_fault_enable_default,
0624     .gart_disable = mmhub_v2_3_gart_disable,
0625     .set_clockgating = mmhub_v2_3_set_clockgating,
0626     .get_clockgating = mmhub_v2_3_get_clockgating,
0627     .setup_vm_pt_regs = mmhub_v2_3_setup_vm_pt_regs,
0628 };
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