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OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include "amdgpu.h"
0024 #include "amdgpu_ras.h"
0025 #include "mmhub_v1_7.h"
0026 
0027 #include "mmhub/mmhub_1_7_offset.h"
0028 #include "mmhub/mmhub_1_7_sh_mask.h"
0029 #include "vega10_enum.h"
0030 
0031 #include "soc15_common.h"
0032 #include "soc15.h"
0033 
0034 #define regVM_L2_CNTL3_DEFAULT  0x80100007
0035 #define regVM_L2_CNTL4_DEFAULT  0x000000c1
0036 
0037 static u64 mmhub_v1_7_get_fb_location(struct amdgpu_device *adev)
0038 {
0039     u64 base = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE);
0040     u64 top = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP);
0041 
0042     base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
0043     base <<= 24;
0044 
0045     top &= MC_VM_FB_LOCATION_TOP__FB_TOP_MASK;
0046     top <<= 24;
0047 
0048     adev->gmc.fb_start = base;
0049     adev->gmc.fb_end = top;
0050 
0051     return base;
0052 }
0053 
0054 static void mmhub_v1_7_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
0055                 uint64_t page_table_base)
0056 {
0057     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0058 
0059     WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
0060             hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base));
0061 
0062     WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
0063             hub->ctx_addr_distance * vmid, upper_32_bits(page_table_base));
0064 }
0065 
0066 static void mmhub_v1_7_init_gart_aperture_regs(struct amdgpu_device *adev)
0067 {
0068     uint64_t pt_base;
0069 
0070     if (adev->gmc.pdb0_bo)
0071         pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo);
0072     else
0073         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
0074 
0075     mmhub_v1_7_setup_vm_pt_regs(adev, 0, pt_base);
0076 
0077     /* If use GART for FB translation, vmid0 page table covers both
0078      * vram and system memory (gart)
0079      */
0080     if (adev->gmc.pdb0_bo) {
0081         WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
0082                 (u32)(adev->gmc.fb_start >> 12));
0083         WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
0084                 (u32)(adev->gmc.fb_start >> 44));
0085 
0086         WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
0087                 (u32)(adev->gmc.gart_end >> 12));
0088         WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
0089                 (u32)(adev->gmc.gart_end >> 44));
0090 
0091     } else {
0092         WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
0093                 (u32)(adev->gmc.gart_start >> 12));
0094         WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
0095                 (u32)(adev->gmc.gart_start >> 44));
0096 
0097         WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
0098                 (u32)(adev->gmc.gart_end >> 12));
0099         WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
0100                 (u32)(adev->gmc.gart_end >> 44));
0101     }
0102 }
0103 
0104 static void mmhub_v1_7_init_system_aperture_regs(struct amdgpu_device *adev)
0105 {
0106     uint64_t value;
0107     uint32_t tmp;
0108 
0109     /* Program the AGP BAR */
0110     WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BASE, 0);
0111     WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
0112     WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
0113 
0114     if (amdgpu_sriov_vf(adev))
0115         return;
0116 
0117     /* Program the system aperture low logical page number. */
0118     WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR,
0119              min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
0120 
0121     WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
0122              max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
0123 
0124     /* In the case squeezing vram into GART aperture, we don't use
0125      * FB aperture and AGP aperture. Disable them.
0126      */
0127     if (adev->gmc.pdb0_bo) {
0128         WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, 0xFFFFFF);
0129         WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, 0);
0130         WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP, 0);
0131         WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);
0132         WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);
0133         WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);
0134     }
0135 
0136     /* Set default page address. */
0137     value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
0138     WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
0139              (u32)(value >> 12));
0140     WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
0141              (u32)(value >> 44));
0142 
0143     /* Program "protection fault". */
0144     WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
0145              (u32)(adev->dummy_page_addr >> 12));
0146     WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
0147              (u32)((u64)adev->dummy_page_addr >> 44));
0148 
0149     tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL2);
0150     tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
0151                 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
0152     WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL2, tmp);
0153 }
0154 
0155 static void mmhub_v1_7_init_tlb_regs(struct amdgpu_device *adev)
0156 {
0157     uint32_t tmp;
0158 
0159     /* Setup TLB control */
0160     tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);
0161 
0162     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
0163     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
0164     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
0165                 ENABLE_ADVANCED_DRIVER_MODEL, 1);
0166     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
0167                 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
0168     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
0169                 MTYPE, MTYPE_UC);/* XXX for emulation. */
0170     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
0171 
0172     WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp);
0173 }
0174 
0175 static void mmhub_v1_7_init_cache_regs(struct amdgpu_device *adev)
0176 {
0177     uint32_t tmp;
0178 
0179     if (amdgpu_sriov_vf(adev))
0180         return;
0181 
0182     /* Setup L2 cache */
0183     tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL);
0184     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
0185     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
0186     /* XXX for emulation, Refer to closed source code.*/
0187     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
0188                 0);
0189     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
0190     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
0191     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
0192     WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL, tmp);
0193 
0194     tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL2);
0195     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
0196     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
0197     WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL2, tmp);
0198 
0199     tmp = regVM_L2_CNTL3_DEFAULT;
0200     if (adev->gmc.translate_further) {
0201         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
0202         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
0203                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
0204     } else {
0205         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
0206         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
0207                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
0208     }
0209     WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL3, tmp);
0210 
0211     tmp = regVM_L2_CNTL4_DEFAULT;
0212     if (adev->gmc.xgmi.connected_to_cpu) {
0213         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
0214                     VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
0215         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
0216                     VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
0217     } else {
0218         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
0219                     VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
0220         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
0221                     VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
0222     }
0223     WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL4, tmp);
0224 }
0225 
0226 static void mmhub_v1_7_enable_system_domain(struct amdgpu_device *adev)
0227 {
0228     uint32_t tmp;
0229 
0230     tmp = RREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL);
0231     tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
0232     tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
0233             adev->gmc.vmid0_page_table_depth);
0234     tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,
0235             adev->gmc.vmid0_page_table_block_size);
0236     tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
0237                 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
0238     WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL, tmp);
0239 }
0240 
0241 static void mmhub_v1_7_disable_identity_aperture(struct amdgpu_device *adev)
0242 {
0243     if (amdgpu_sriov_vf(adev))
0244         return;
0245 
0246     WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
0247              0XFFFFFFFF);
0248     WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
0249              0x0000000F);
0250 
0251     WREG32_SOC15(MMHUB, 0,
0252              regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
0253     WREG32_SOC15(MMHUB, 0,
0254              regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
0255 
0256     WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
0257              0);
0258     WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
0259              0);
0260 }
0261 
0262 static void mmhub_v1_7_setup_vmid_config(struct amdgpu_device *adev)
0263 {
0264     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0265     unsigned num_level, block_size;
0266     uint32_t tmp;
0267     int i;
0268 
0269     num_level = adev->vm_manager.num_level;
0270     block_size = adev->vm_manager.block_size;
0271     if (adev->gmc.translate_further)
0272         num_level -= 1;
0273     else
0274         block_size -= 9;
0275 
0276     for (i = 0; i <= 14; i++) {
0277         tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL, i);
0278         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
0279         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
0280                     num_level);
0281         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0282                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0283         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0284                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
0285                     1);
0286         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0287                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0288         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0289                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0290         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0291                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0292         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0293                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0294         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0295                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0296         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0297                     PAGE_TABLE_BLOCK_SIZE,
0298                     block_size);
0299         /* On Aldebaran, XNACK can be enabled in the SQ per-process.
0300          * Retry faults need to be enabled for that to work.
0301          */
0302         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0303                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
0304                     1);
0305         WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL,
0306                     i * hub->ctx_distance, tmp);
0307         WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
0308                     i * hub->ctx_addr_distance, 0);
0309         WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
0310                     i * hub->ctx_addr_distance, 0);
0311         WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
0312                     i * hub->ctx_addr_distance,
0313                     lower_32_bits(adev->vm_manager.max_pfn - 1));
0314         WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
0315                     i * hub->ctx_addr_distance,
0316                     upper_32_bits(adev->vm_manager.max_pfn - 1));
0317     }
0318 }
0319 
0320 static void mmhub_v1_7_program_invalidation(struct amdgpu_device *adev)
0321 {
0322     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0323     unsigned i;
0324 
0325     for (i = 0; i < 18; ++i) {
0326         WREG32_SOC15_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
0327                     i * hub->eng_addr_distance, 0xffffffff);
0328         WREG32_SOC15_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
0329                     i * hub->eng_addr_distance, 0x1f);
0330     }
0331 }
0332 
0333 static int mmhub_v1_7_gart_enable(struct amdgpu_device *adev)
0334 {
0335     /* GART Enable. */
0336     mmhub_v1_7_init_gart_aperture_regs(adev);
0337     mmhub_v1_7_init_system_aperture_regs(adev);
0338     mmhub_v1_7_init_tlb_regs(adev);
0339     mmhub_v1_7_init_cache_regs(adev);
0340 
0341     mmhub_v1_7_enable_system_domain(adev);
0342     mmhub_v1_7_disable_identity_aperture(adev);
0343     mmhub_v1_7_setup_vmid_config(adev);
0344     mmhub_v1_7_program_invalidation(adev);
0345 
0346     return 0;
0347 }
0348 
0349 static void mmhub_v1_7_gart_disable(struct amdgpu_device *adev)
0350 {
0351     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0352     u32 tmp;
0353     u32 i;
0354 
0355     /* Disable all tables */
0356     for (i = 0; i < 16; i++)
0357         WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_CNTL,
0358                     i * hub->ctx_distance, 0);
0359 
0360     /* Setup TLB control */
0361     tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);
0362     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
0363     tmp = REG_SET_FIELD(tmp,
0364                 MC_VM_MX_L1_TLB_CNTL,
0365                 ENABLE_ADVANCED_DRIVER_MODEL,
0366                 0);
0367     WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp);
0368 
0369     if (!amdgpu_sriov_vf(adev)) {
0370         /* Setup L2 cache */
0371         tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL);
0372         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
0373         WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL, tmp);
0374         WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL3, 0);
0375     }
0376 }
0377 
0378 /**
0379  * mmhub_v1_7_set_fault_enable_default - update GART/VM fault handling
0380  *
0381  * @adev: amdgpu_device pointer
0382  * @value: true redirects VM faults to the default page
0383  */
0384 static void mmhub_v1_7_set_fault_enable_default(struct amdgpu_device *adev, bool value)
0385 {
0386     u32 tmp;
0387 
0388     if (amdgpu_sriov_vf(adev))
0389         return;
0390 
0391     tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL);
0392     tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
0393             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0394     tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
0395             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0396     tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
0397             PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0398     tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
0399             PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0400     tmp = REG_SET_FIELD(tmp,
0401             VM_L2_PROTECTION_FAULT_CNTL,
0402             TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
0403             value);
0404     tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
0405             NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0406     tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
0407             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0408     tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
0409             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0410     tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
0411             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0412     tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
0413             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0414     tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
0415             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0416     if (!value) {
0417         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
0418                 CRASH_ON_NO_RETRY_FAULT, 1);
0419         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
0420                 CRASH_ON_RETRY_FAULT, 1);
0421     }
0422 
0423     WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL, tmp);
0424 }
0425 
0426 static void mmhub_v1_7_init(struct amdgpu_device *adev)
0427 {
0428     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
0429 
0430     hub->ctx0_ptb_addr_lo32 =
0431         SOC15_REG_OFFSET(MMHUB, 0,
0432                  regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
0433     hub->ctx0_ptb_addr_hi32 =
0434         SOC15_REG_OFFSET(MMHUB, 0,
0435                  regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
0436     hub->vm_inv_eng0_req =
0437         SOC15_REG_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_REQ);
0438     hub->vm_inv_eng0_ack =
0439         SOC15_REG_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ACK);
0440     hub->vm_context0_cntl =
0441         SOC15_REG_OFFSET(MMHUB, 0, regVM_CONTEXT0_CNTL);
0442     hub->vm_l2_pro_fault_status =
0443         SOC15_REG_OFFSET(MMHUB, 0, regVM_L2_PROTECTION_FAULT_STATUS);
0444     hub->vm_l2_pro_fault_cntl =
0445         SOC15_REG_OFFSET(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL);
0446 
0447     hub->ctx_distance = regVM_CONTEXT1_CNTL - regVM_CONTEXT0_CNTL;
0448     hub->ctx_addr_distance = regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
0449         regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
0450     hub->eng_distance = regVM_INVALIDATE_ENG1_REQ - regVM_INVALIDATE_ENG0_REQ;
0451     hub->eng_addr_distance = regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
0452         regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
0453 
0454 }
0455 
0456 static void mmhub_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
0457                             bool enable)
0458 {
0459     uint32_t def, data, def1, data1, def2 = 0, data2 = 0;
0460 
0461     def  = data  = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG);
0462 
0463     def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2);
0464     def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2);
0465 
0466     if (enable) {
0467         data |= ATC_L2_MISC_CG__ENABLE_MASK;
0468 
0469         data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
0470                    DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
0471                    DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
0472                    DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
0473                    DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
0474                    DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
0475 
0476         data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
0477                    DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
0478                    DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
0479                    DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
0480                    DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
0481                    DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
0482     } else {
0483         data &= ~ATC_L2_MISC_CG__ENABLE_MASK;
0484 
0485         data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
0486               DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
0487               DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
0488               DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
0489               DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
0490               DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
0491 
0492         data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
0493                   DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
0494                   DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
0495                   DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
0496                   DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
0497                   DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
0498     }
0499 
0500     if (def != data)
0501         WREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG, data);
0502 
0503     if (def1 != data1)
0504         WREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2, data1);
0505 
0506     if (def2 != data2)
0507         WREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2, data2);
0508 }
0509 
0510 static void mmhub_v1_7_update_medium_grain_light_sleep(struct amdgpu_device *adev,
0511                                bool enable)
0512 {
0513     uint32_t def, data;
0514 
0515     def = data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG);
0516 
0517     if (enable)
0518         data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
0519     else
0520         data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
0521 
0522     if (def != data)
0523         WREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG, data);
0524 }
0525 
0526 static int mmhub_v1_7_set_clockgating(struct amdgpu_device *adev,
0527                    enum amd_clockgating_state state)
0528 {
0529     if (amdgpu_sriov_vf(adev))
0530         return 0;
0531 
0532     /* Change state only if MCCG support is enabled through driver */
0533     if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)
0534         mmhub_v1_7_update_medium_grain_clock_gating(adev,
0535                 state == AMD_CG_STATE_GATE);
0536 
0537     /* Change state only if LS support is enabled through driver */
0538     if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)
0539         mmhub_v1_7_update_medium_grain_light_sleep(adev,
0540                 state == AMD_CG_STATE_GATE);
0541 
0542     return 0;
0543 }
0544 
0545 static void mmhub_v1_7_get_clockgating(struct amdgpu_device *adev, u64 *flags)
0546 {
0547     int data, data1;
0548 
0549     if (amdgpu_sriov_vf(adev))
0550         *flags = 0;
0551 
0552     data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG);
0553 
0554     data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2);
0555 
0556     /* AMD_CG_SUPPORT_MC_MGCG */
0557     if ((data & ATC_L2_MISC_CG__ENABLE_MASK) &&
0558         !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
0559                DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
0560                DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
0561                DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
0562                DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
0563                DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
0564         *flags |= AMD_CG_SUPPORT_MC_MGCG;
0565 
0566     /* AMD_CG_SUPPORT_MC_LS */
0567     if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
0568         *flags |= AMD_CG_SUPPORT_MC_LS;
0569 }
0570 
0571 static const struct soc15_ras_field_entry mmhub_v1_7_ras_fields[] = {
0572     /* MMHUB Range 0 */
0573     { "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
0574     SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
0575     SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
0576     },
0577     { "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
0578     SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
0579     SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
0580     },
0581     { "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
0582     SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
0583     SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
0584     },
0585     { "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
0586     SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
0587     SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_DED_COUNT),
0588     },
0589     { "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
0590     SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
0591     SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_DED_COUNT),
0592     },
0593     { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
0594     SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
0595     SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
0596     },
0597     { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
0598     SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
0599     0, 0,
0600     },
0601     { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
0602     SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
0603     0, 0,
0604     },
0605     { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
0606     SOC15_REG_FIELD(MMEA0_EDC_CNT, IORD_CMDMEM_SED_COUNT),
0607     0, 0,
0608     },
0609     { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
0610     SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
0611     0, 0,
0612     },
0613     { "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
0614     SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
0615     SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
0616     },
0617     { "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
0618     SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
0619     SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
0620     },
0621     { "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
0622     SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
0623     SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
0624     },
0625     { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
0626     SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
0627     0, 0,
0628     },
0629     { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
0630     SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
0631     0, 0,
0632     },
0633     { "MMEA0_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
0634     SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_SED_COUNT),
0635     SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_DED_COUNT),
0636     },
0637     { "MMEA0_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
0638     SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_SED_COUNT),
0639     SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_DED_COUNT),
0640     },
0641     { "MMEA0_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
0642     SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_SED_COUNT),
0643     SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_DED_COUNT),
0644     },
0645     { "MMEA0_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
0646     SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_SED_COUNT),
0647     SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_DED_COUNT),
0648     },
0649     { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
0650     0, 0,
0651     SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
0652     },
0653     { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
0654     0, 0,
0655     SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
0656     },
0657     { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
0658     0, 0,
0659     SOC15_REG_FIELD(MMEA0_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
0660     },
0661     { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
0662     0, 0,
0663     SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
0664     },
0665     { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
0666     0, 0,
0667     SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
0668     },
0669     { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
0670     0, 0,
0671     SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
0672     },
0673 
0674     /* MMHUB Range 1 */
0675     { "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
0676     SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
0677     SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
0678     },
0679     { "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
0680     SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
0681     SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
0682     },
0683     { "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
0684     SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
0685     SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
0686     },
0687     { "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
0688     SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
0689     SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_DED_COUNT),
0690     },
0691     { "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
0692     SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
0693     SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_DED_COUNT),
0694     },
0695     { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
0696     SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
0697     SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
0698     },
0699     { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
0700     SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
0701     0, 0,
0702     },
0703     { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
0704     SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
0705     0, 0,
0706     },
0707     { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
0708     SOC15_REG_FIELD(MMEA1_EDC_CNT, IORD_CMDMEM_SED_COUNT),
0709     0, 0,
0710     },
0711     { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
0712     SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
0713     0, 0,
0714     },
0715     { "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
0716     SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
0717     SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
0718     },
0719     { "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
0720     SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
0721     SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
0722     },
0723     { "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
0724     SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
0725     SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
0726     },
0727     { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
0728     SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
0729     0, 0,
0730     },
0731     { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
0732     SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
0733     0, 0,
0734     },
0735     { "MMEA1_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
0736     SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_SED_COUNT),
0737     SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_DED_COUNT),
0738     },
0739     { "MMEA1_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
0740     SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_SED_COUNT),
0741     SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_DED_COUNT),
0742     },
0743     { "MMEA1_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
0744     SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_SED_COUNT),
0745     SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_DED_COUNT),
0746     },
0747     { "MMEA1_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
0748     SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_SED_COUNT),
0749     SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_DED_COUNT),
0750     },
0751     { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
0752     0, 0,
0753     SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
0754     },
0755     { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
0756     0, 0,
0757     SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
0758     },
0759     { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
0760     0, 0,
0761     SOC15_REG_FIELD(MMEA1_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
0762     },
0763     { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
0764     0, 0,
0765     SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
0766     },
0767     { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
0768     0, 0,
0769     SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
0770     },
0771     { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
0772     0, 0,
0773     SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
0774     },
0775 
0776     /* MMHAB Range 2*/
0777     { "MMEA2_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
0778     SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
0779     SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
0780     },
0781     { "MMEA2_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
0782     SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
0783     SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
0784     },
0785     { "MMEA2_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
0786     SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
0787     SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
0788     },
0789     { "MMEA2_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
0790     SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
0791     SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_DED_COUNT),
0792     },
0793     { "MMEA2_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
0794     SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
0795     SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_DED_COUNT),
0796     },
0797     { "MMEA2_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
0798     SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
0799     SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
0800     },
0801     { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
0802     SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
0803     0, 0,
0804     },
0805     { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
0806     SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
0807     0, 0,
0808     },
0809     { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
0810     SOC15_REG_FIELD(MMEA2_EDC_CNT, IORD_CMDMEM_SED_COUNT),
0811     0, 0,
0812     },
0813     { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
0814     SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
0815     0, 0,
0816     },
0817     { "MMEA2_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
0818     SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
0819     SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
0820     },
0821     { "MMEA2_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
0822     SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
0823     SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
0824     },
0825     { "MMEA2_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
0826     SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
0827     SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
0828     },
0829     { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
0830     SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
0831     0, 0,
0832     },
0833     { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
0834     SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
0835     0, 0,
0836     },
0837     { "MMEA2_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
0838     SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_SED_COUNT),
0839     SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_DED_COUNT),
0840     },
0841     { "MMEA2_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
0842     SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_SED_COUNT),
0843     SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_DED_COUNT),
0844     },
0845     { "MMEA2_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
0846     SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_SED_COUNT),
0847     SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_DED_COUNT),
0848     },
0849     { "MMEA2_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
0850     SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_SED_COUNT),
0851     SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_DED_COUNT),
0852     },
0853     { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
0854     0, 0,
0855     SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
0856     },
0857     { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
0858     0, 0,
0859     SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
0860     },
0861     { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
0862     0, 0,
0863     SOC15_REG_FIELD(MMEA2_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
0864     },
0865     { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
0866     0, 0,
0867     SOC15_REG_FIELD(MMEA2_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
0868     },
0869     { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
0870     0, 0,
0871     SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
0872     },
0873     { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
0874     0, 0,
0875     SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
0876     },
0877 
0878     /* MMHUB Rang 3 */
0879     { "MMEA3_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
0880     SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
0881     SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
0882     },
0883     { "MMEA3_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
0884     SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
0885     SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
0886     },
0887     { "MMEA3_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
0888     SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
0889     SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
0890     },
0891     { "MMEA3_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
0892     SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
0893     SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_DED_COUNT),
0894     },
0895     { "MMEA3_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
0896     SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
0897     SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_DED_COUNT),
0898     },
0899     { "MMEA3_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
0900         SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
0901         SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
0902         },
0903     { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
0904     SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
0905     0, 0,
0906     },
0907     { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
0908     SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
0909     0, 0,
0910     },
0911     { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
0912     SOC15_REG_FIELD(MMEA3_EDC_CNT, IORD_CMDMEM_SED_COUNT),
0913     0, 0,
0914     },
0915     { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
0916     SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
0917     0, 0,
0918     },
0919     { "MMEA3_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
0920     SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
0921     SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
0922     },
0923     { "MMEA3_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
0924     SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
0925     SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
0926     },
0927     { "MMEA3_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
0928     SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
0929     SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
0930     },
0931     { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
0932     SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
0933     0, 0,
0934     },
0935     { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
0936     SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
0937     0, 0,
0938     },
0939     { "MMEA3_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
0940     SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_SED_COUNT),
0941     SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_DED_COUNT),
0942     },
0943     { "MMEA3_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
0944     SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_SED_COUNT),
0945     SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_DED_COUNT),
0946     },
0947     { "MMEA3_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
0948     SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_SED_COUNT),
0949     SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_DED_COUNT),
0950     },
0951     { "MMEA3_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
0952     SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_SED_COUNT),
0953     SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_DED_COUNT),
0954     },
0955     { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
0956     0, 0,
0957     SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
0958     },
0959     { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
0960     0, 0,
0961     SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
0962     },
0963     { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
0964     0, 0,
0965     SOC15_REG_FIELD(MMEA3_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
0966     },
0967     { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
0968     0, 0,
0969     SOC15_REG_FIELD(MMEA3_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
0970     },
0971     { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
0972     0, 0,
0973     SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
0974     },
0975     { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
0976     0, 0,
0977     SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
0978     },
0979 
0980     /* MMHUB Range 4 */
0981     { "MMEA4_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
0982     SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
0983     SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
0984     },
0985     { "MMEA4_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
0986     SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
0987     SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
0988     },
0989     { "MMEA4_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
0990     SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
0991     SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
0992     },
0993     { "MMEA4_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
0994     SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
0995     SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_DED_COUNT),
0996     },
0997     { "MMEA4_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
0998     SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
0999     SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1000     },
1001     { "MMEA4_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1002     SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
1003     SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
1004     },
1005     { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1006     SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1007     0, 0,
1008     },
1009     { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1010     SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1011     0, 0,
1012     },
1013     { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1014     SOC15_REG_FIELD(MMEA4_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1015     0, 0,
1016     },
1017     { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1018     SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1019     0, 0,
1020     },
1021     { "MMEA4_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1022     SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1023     SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1024     },
1025     { "MMEA4_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1026     SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1027     SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1028     },
1029     { "MMEA4_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1030     SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1031     SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1032     },
1033     { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1034     SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1035     0, 0,
1036     },
1037     { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1038     SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1039     0, 0,
1040     },
1041     { "MMEA4_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1042     SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1043     SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1044     },
1045     { "MMEA4_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1046     SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1047     SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1048     },
1049     { "MMEA4_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1050     SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1051     SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1052     },
1053     { "MMEA4_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1054     SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1055     SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1056     },
1057     { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1058     0, 0,
1059     SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1060     },
1061     { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1062     0, 0,
1063     SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1064     },
1065     { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1066     0, 0,
1067     SOC15_REG_FIELD(MMEA4_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1068     },
1069     { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1070     0, 0,
1071     SOC15_REG_FIELD(MMEA4_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1072     },
1073     { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1074     0, 0,
1075     SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1076     },
1077     { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1078     0, 0,
1079     SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1080     },
1081 
1082     /* MMHUAB Range 5 */
1083     { "MMEA5_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1084     SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1085     SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1086     },
1087     { "MMEA5_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1088     SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1089     SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1090     },
1091     { "MMEA5_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1092     SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1093     SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1094     },
1095     { "MMEA5_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1096     SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1097     SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1098     },
1099     { "MMEA5_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1100     SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1101     SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1102     },
1103     { "MMEA5_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1104     SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
1105     SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
1106     },
1107     { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1108     SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1109     0, 0,
1110     },
1111     { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1112     SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1113     0, 0,
1114     },
1115     { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1116     SOC15_REG_FIELD(MMEA5_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1117     0, 0,
1118     },
1119     { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1120     SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1121     0, 0,
1122     },
1123     { "MMEA5_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1124     SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1125     SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1126     },
1127     { "MMEA5_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1128     SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1129     SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1130     },
1131     { "MMEA5_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1132     SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1133     SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1134     },
1135     { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1136     SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1137     0, 0,
1138     },
1139     { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1140     SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1141     0, 0,
1142     },
1143     { "MMEA5_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1144     SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1145     SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1146     },
1147     { "MMEA5_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1148     SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1149     SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1150     },
1151     { "MMEA5_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1152     SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1153     SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1154     },
1155     { "MMEA5_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1156     SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1157     SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1158     },
1159     { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1160     0, 0,
1161     SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1162     },
1163     { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1164     0, 0,
1165     SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1166     },
1167     { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1168     0, 0,
1169     SOC15_REG_FIELD(MMEA5_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1170     },
1171     { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1172     0, 0,
1173     SOC15_REG_FIELD(MMEA5_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1174     },
1175     { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1176     0, 0,
1177     SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1178     },
1179     { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1180     0, 0,
1181     SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1182     },
1183 };
1184 
1185 static const struct soc15_reg_entry mmhub_v1_7_edc_cnt_regs[] = {
1186     { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), 0, 0, 0 },
1187     { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), 0, 0, 0 },
1188     { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), 0, 0, 0 },
1189     { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), 0, 0, 0 },
1190     { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), 0, 0, 0 },
1191     { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), 0, 0, 0 },
1192     { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), 0, 0, 0 },
1193     { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), 0, 0, 0 },
1194     { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), 0, 0, 0 },
1195     { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), 0, 0, 0 },
1196     { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), 0, 0, 0 },
1197     { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), 0, 0, 0 },
1198     { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), 0, 0, 0 },
1199     { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), 0, 0, 0 },
1200     { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), 0, 0, 0 },
1201     { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), 0, 0, 0 },
1202     { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), 0, 0, 0 },
1203     { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), 0, 0, 0 },
1204 };
1205 
1206 static int mmhub_v1_7_get_ras_error_count(struct amdgpu_device *adev,
1207                       const struct soc15_reg_entry *reg,
1208                       uint32_t value,
1209                       uint32_t *sec_count,
1210                       uint32_t *ded_count)
1211 {
1212     uint32_t i;
1213     uint32_t sec_cnt, ded_cnt;
1214 
1215     for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ras_fields); i++) {
1216         if(mmhub_v1_7_ras_fields[i].reg_offset != reg->reg_offset)
1217             continue;
1218 
1219         sec_cnt = (value &
1220                 mmhub_v1_7_ras_fields[i].sec_count_mask) >>
1221                 mmhub_v1_7_ras_fields[i].sec_count_shift;
1222         if (sec_cnt) {
1223             dev_info(adev->dev, "MMHUB SubBlock %s, SEC %d\n",
1224                  mmhub_v1_7_ras_fields[i].name,
1225                  sec_cnt);
1226             *sec_count += sec_cnt;
1227         }
1228 
1229         ded_cnt = (value &
1230                 mmhub_v1_7_ras_fields[i].ded_count_mask) >>
1231                 mmhub_v1_7_ras_fields[i].ded_count_shift;
1232         if (ded_cnt) {
1233             dev_info(adev->dev, "MMHUB SubBlock %s, DED %d\n",
1234                  mmhub_v1_7_ras_fields[i].name,
1235                  ded_cnt);
1236             *ded_count += ded_cnt;
1237         }
1238     }
1239 
1240     return 0;
1241 }
1242 
1243 static void mmhub_v1_7_query_ras_error_count(struct amdgpu_device *adev,
1244                          void *ras_error_status)
1245 {
1246     struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
1247     uint32_t sec_count = 0, ded_count = 0;
1248     uint32_t i;
1249     uint32_t reg_value;
1250 
1251     err_data->ue_count = 0;
1252     err_data->ce_count = 0;
1253 
1254     for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_edc_cnt_regs); i++) {
1255         reg_value =
1256             RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i]));
1257         if (reg_value)
1258             mmhub_v1_7_get_ras_error_count(adev, &mmhub_v1_7_edc_cnt_regs[i],
1259                 reg_value, &sec_count, &ded_count);
1260     }
1261 
1262     err_data->ce_count += sec_count;
1263     err_data->ue_count += ded_count;
1264 }
1265 
1266 static void mmhub_v1_7_reset_ras_error_count(struct amdgpu_device *adev)
1267 {
1268     uint32_t i;
1269 
1270     /* write 0 to reset the edc counters */
1271     if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) {
1272         for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_edc_cnt_regs); i++)
1273             WREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i]), 0);
1274     }
1275 }
1276 
1277 static const struct soc15_reg_entry mmhub_v1_7_ea_err_status_regs[] = {
1278     { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_ERR_STATUS), 0, 0, 0 },
1279     { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_ERR_STATUS), 0, 0, 0 },
1280     { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_ERR_STATUS), 0, 0, 0 },
1281     { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_ERR_STATUS), 0, 0, 0 },
1282     { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_ERR_STATUS), 0, 0, 0 },
1283     { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_ERR_STATUS), 0, 0, 0 },
1284 };
1285 
1286 static void mmhub_v1_7_query_ras_error_status(struct amdgpu_device *adev)
1287 {
1288     int i;
1289     uint32_t reg_value;
1290 
1291     if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB))
1292         return;
1293 
1294     for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ea_err_status_regs); i++) {
1295         reg_value =
1296             RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_ea_err_status_regs[i]));
1297         if (REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_STATUS) ||
1298             REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_WRRSP_STATUS) ||
1299             REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
1300             dev_warn(adev->dev, "MMHUB EA err detected at instance: %d, status: 0x%x!\n",
1301                     i, reg_value);
1302         }
1303     }
1304 }
1305 
1306 static void mmhub_v1_7_reset_ras_error_status(struct amdgpu_device *adev)
1307 {
1308     int i;
1309     uint32_t reg_value;
1310 
1311     if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB))
1312         return;
1313 
1314     for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ea_err_status_regs); i++) {
1315         reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(
1316             mmhub_v1_7_ea_err_status_regs[i]));
1317         reg_value = REG_SET_FIELD(reg_value, MMEA0_ERR_STATUS,
1318                       CLEAR_ERROR_STATUS, 0x01);
1319         WREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_ea_err_status_regs[i]),
1320                reg_value);
1321     }
1322 }
1323 
1324 struct amdgpu_ras_block_hw_ops mmhub_v1_7_ras_hw_ops = {
1325     .query_ras_error_count = mmhub_v1_7_query_ras_error_count,
1326     .reset_ras_error_count = mmhub_v1_7_reset_ras_error_count,
1327     .query_ras_error_status = mmhub_v1_7_query_ras_error_status,
1328     .reset_ras_error_status = mmhub_v1_7_reset_ras_error_status,
1329 };
1330 
1331 struct amdgpu_mmhub_ras mmhub_v1_7_ras = {
1332     .ras_block = {
1333         .hw_ops = &mmhub_v1_7_ras_hw_ops,
1334     },
1335 };
1336 
1337 const struct amdgpu_mmhub_funcs mmhub_v1_7_funcs = {
1338     .get_fb_location = mmhub_v1_7_get_fb_location,
1339     .init = mmhub_v1_7_init,
1340     .gart_enable = mmhub_v1_7_gart_enable,
1341     .set_fault_enable_default = mmhub_v1_7_set_fault_enable_default,
1342     .gart_disable = mmhub_v1_7_gart_disable,
1343     .set_clockgating = mmhub_v1_7_set_clockgating,
1344     .get_clockgating = mmhub_v1_7_get_clockgating,
1345     .setup_vm_pt_regs = mmhub_v1_7_setup_vm_pt_regs,
1346 };
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