amd/amdgpu/lsdma_v6_0.c

0001 /*
0002  * Copyright 2022 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #include <linux/delay.h>
0025 #include "amdgpu.h"
0026 #include "lsdma_v6_0.h"
0027 #include "amdgpu_lsdma.h"
0028
0029 #include "lsdma/lsdma_6_0_0_offset.h"
0030 #include "lsdma/lsdma_6_0_0_sh_mask.h"
0031
0032 static int lsdma_v6_0_wait_pio_status(struct amdgpu_device *adev)
0033 {
0034     return amdgpu_lsdma_wait_for(adev, SOC15_REG_OFFSET(LSDMA, 0, regLSDMA_PIO_STATUS),
0035             LSDMA_PIO_STATUS__PIO_IDLE_MASK | LSDMA_PIO_STATUS__PIO_FIFO_EMPTY_MASK,
0036             LSDMA_PIO_STATUS__PIO_IDLE_MASK | LSDMA_PIO_STATUS__PIO_FIFO_EMPTY_MASK);
0037 }
0038
0039 static int lsdma_v6_0_copy_mem(struct amdgpu_device *adev,
0040                    uint64_t src_addr,
0041                    uint64_t dst_addr,
0042                    uint64_t size)
0043 {
0044     int ret;
0045     uint32_t tmp;
0046
0047     WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_SRC_ADDR_LO, lower_32_bits(src_addr));
0048     WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_SRC_ADDR_HI, upper_32_bits(src_addr));
0049
0050     WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_LO, lower_32_bits(dst_addr));
0051     WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_HI, upper_32_bits(dst_addr));
0052
0053     WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_CONTROL, 0x0);
0054
0055     tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND);
0056     tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size);
0057     tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0);
0058     tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0);
0059     tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0);
0060     tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0);
0061     tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, OVERLAP_DISABLE, 0);
0062     tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 0);
0063     WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND, tmp);
0064
0065     ret = lsdma_v6_0_wait_pio_status(adev);
0066     if (ret)
0067         dev_err(adev->dev, "LSDMA PIO failed to copy memory!\n");
0068
0069     return ret;
0070 }
0071
0072 static int lsdma_v6_0_fill_mem(struct amdgpu_device *adev,
0073                    uint64_t dst_addr,
0074                    uint32_t data,
0075                    uint64_t size)
0076 {
0077     int ret;
0078     uint32_t tmp;
0079
0080     WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_CONSTFILL_DATA, data);
0081
0082     WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_LO, lower_32_bits(dst_addr));
0083     WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_DST_ADDR_HI, upper_32_bits(dst_addr));
0084
0085     WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_CONTROL, 0x0);
0086
0087     tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND);
0088     tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, BYTE_COUNT, size);
0089     tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_LOCATION, 0);
0090     tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_LOCATION, 0);
0091     tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, SRC_ADDR_INC, 0);
0092     tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, DST_ADDR_INC, 0);
0093     tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, OVERLAP_DISABLE, 0);
0094     tmp = REG_SET_FIELD(tmp, LSDMA_PIO_COMMAND, CONSTANT_FILL, 1);
0095     WREG32_SOC15(LSDMA, 0, regLSDMA_PIO_COMMAND, tmp);
0096
0097     ret = lsdma_v6_0_wait_pio_status(adev);
0098     if (ret)
0099         dev_err(adev->dev, "LSDMA PIO failed to fill memory!\n");
0100
0101     return ret;
0102 }
0103
0104 static void lsdma_v6_0_update_memory_power_gating(struct amdgpu_device *adev,
0105                          bool enable)
0106 {
0107     uint32_t tmp;
0108
0109     tmp = RREG32_SOC15(LSDMA, 0, regLSDMA_MEM_POWER_CTRL);
0110     tmp = REG_SET_FIELD(tmp, LSDMA_MEM_POWER_CTRL, MEM_POWER_CTRL_EN, 0);
0111     WREG32_SOC15(LSDMA, 0, regLSDMA_MEM_POWER_CTRL, tmp);
0112
0113     tmp = REG_SET_FIELD(tmp, LSDMA_MEM_POWER_CTRL, MEM_POWER_CTRL_EN, enable);
0114     WREG32_SOC15(LSDMA, 0, regLSDMA_MEM_POWER_CTRL, tmp);
0115 }
0116
0117 const struct amdgpu_lsdma_funcs lsdma_v6_0_funcs = {
0118     .copy_mem = lsdma_v6_0_copy_mem,
0119     .fill_mem = lsdma_v6_0_fill_mem,
0120     .update_memory_power_gating = lsdma_v6_0_update_memory_power_gating
0121 };