amd/amdgpu/jpeg_v2_0.h

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef __JPEG_V2_0_H__
0025 #define __JPEG_V2_0_H__
0026
0027 #define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET             0x1bfff
0028 #define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET                0x4029
0029 #define mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET              0x402a
0030 #define mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET              0x402b
0031 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET      0x40ea
0032 #define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET     0x40eb
0033 #define mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET              0x40cf
0034 #define mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET             0x40d1
0035 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET         0x40e8
0036 #define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET        0x40e9
0037 #define mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET              0x4082
0038 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET      0x40ec
0039 #define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET     0x40ed
0040 #define mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET         0x4085
0041 #define mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET              0x4084
0042 #define mmUVD_JRBC_STATUS_INTERNAL_OFFSET               0x4089
0043 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET                0x401f
0044 #define mmUVD_JPEG_IH_CTRL_INTERNAL_OFFSET              0x4149
0045
0046 #define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR                0x18000
0047
0048 void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring);
0049 void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring);
0050 void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
0051                 unsigned flags);
0052 void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
0053                 struct amdgpu_ib *ib, uint32_t flags);
0054 void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
0055                 uint32_t val, uint32_t mask);
0056 void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
0057                 unsigned vmid, uint64_t pd_addr);
0058 void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
0059 void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count);
0060
0061 extern const struct amdgpu_ip_block_version jpeg_v2_0_ip_block;
0062
0063 #endif /* __JPEG_V2_0_H__ */