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0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #include "amdgpu.h"
0025 #include "amdgpu_jpeg.h"
0026 #include "amdgpu_pm.h"
0027 #include "soc15.h"
0028 #include "soc15d.h"
0029 #include "jpeg_v2_0.h"
0030 
0031 #include "vcn/vcn_2_0_0_offset.h"
0032 #include "vcn/vcn_2_0_0_sh_mask.h"
0033 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
0034 
0035 static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
0036 static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev);
0037 static int jpeg_v2_0_set_powergating_state(void *handle,
0038                 enum amd_powergating_state state);
0039 
0040 /**
0041  * jpeg_v2_0_early_init - set function pointers
0042  *
0043  * @handle: amdgpu_device pointer
0044  *
0045  * Set ring and irq function pointers
0046  */
0047 static int jpeg_v2_0_early_init(void *handle)
0048 {
0049     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0050 
0051     adev->jpeg.num_jpeg_inst = 1;
0052 
0053     jpeg_v2_0_set_dec_ring_funcs(adev);
0054     jpeg_v2_0_set_irq_funcs(adev);
0055 
0056     return 0;
0057 }
0058 
0059 /**
0060  * jpeg_v2_0_sw_init - sw init for JPEG block
0061  *
0062  * @handle: amdgpu_device pointer
0063  *
0064  * Load firmware and sw initialization
0065  */
0066 static int jpeg_v2_0_sw_init(void *handle)
0067 {
0068     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0069     struct amdgpu_ring *ring;
0070     int r;
0071 
0072     /* JPEG TRAP */
0073     r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
0074         VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
0075     if (r)
0076         return r;
0077 
0078     r = amdgpu_jpeg_sw_init(adev);
0079     if (r)
0080         return r;
0081 
0082     r = amdgpu_jpeg_resume(adev);
0083     if (r)
0084         return r;
0085 
0086     ring = &adev->jpeg.inst->ring_dec;
0087     ring->use_doorbell = true;
0088     ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
0089     sprintf(ring->name, "jpeg_dec");
0090     r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq,
0091                  0, AMDGPU_RING_PRIO_DEFAULT, NULL);
0092     if (r)
0093         return r;
0094 
0095     adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
0096     adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_PITCH);
0097 
0098     return 0;
0099 }
0100 
0101 /**
0102  * jpeg_v2_0_sw_fini - sw fini for JPEG block
0103  *
0104  * @handle: amdgpu_device pointer
0105  *
0106  * JPEG suspend and free up sw allocation
0107  */
0108 static int jpeg_v2_0_sw_fini(void *handle)
0109 {
0110     int r;
0111     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0112 
0113     r = amdgpu_jpeg_suspend(adev);
0114     if (r)
0115         return r;
0116 
0117     r = amdgpu_jpeg_sw_fini(adev);
0118 
0119     return r;
0120 }
0121 
0122 /**
0123  * jpeg_v2_0_hw_init - start and test JPEG block
0124  *
0125  * @handle: amdgpu_device pointer
0126  *
0127  */
0128 static int jpeg_v2_0_hw_init(void *handle)
0129 {
0130     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0131     struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
0132     int r;
0133 
0134     adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
0135         (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
0136 
0137     r = amdgpu_ring_test_helper(ring);
0138     if (!r)
0139         DRM_INFO("JPEG decode initialized successfully.\n");
0140 
0141     return r;
0142 }
0143 
0144 /**
0145  * jpeg_v2_0_hw_fini - stop the hardware block
0146  *
0147  * @handle: amdgpu_device pointer
0148  *
0149  * Stop the JPEG block, mark ring as not ready any more
0150  */
0151 static int jpeg_v2_0_hw_fini(void *handle)
0152 {
0153     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0154 
0155     cancel_delayed_work_sync(&adev->vcn.idle_work);
0156 
0157     if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
0158           RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS))
0159         jpeg_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
0160 
0161     return 0;
0162 }
0163 
0164 /**
0165  * jpeg_v2_0_suspend - suspend JPEG block
0166  *
0167  * @handle: amdgpu_device pointer
0168  *
0169  * HW fini and suspend JPEG block
0170  */
0171 static int jpeg_v2_0_suspend(void *handle)
0172 {
0173     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0174     int r;
0175 
0176     r = jpeg_v2_0_hw_fini(adev);
0177     if (r)
0178         return r;
0179 
0180     r = amdgpu_jpeg_suspend(adev);
0181 
0182     return r;
0183 }
0184 
0185 /**
0186  * jpeg_v2_0_resume - resume JPEG block
0187  *
0188  * @handle: amdgpu_device pointer
0189  *
0190  * Resume firmware and hw init JPEG block
0191  */
0192 static int jpeg_v2_0_resume(void *handle)
0193 {
0194     int r;
0195     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0196 
0197     r = amdgpu_jpeg_resume(adev);
0198     if (r)
0199         return r;
0200 
0201     r = jpeg_v2_0_hw_init(adev);
0202 
0203     return r;
0204 }
0205 
0206 static int jpeg_v2_0_disable_power_gating(struct amdgpu_device *adev)
0207 {
0208     uint32_t data;
0209     int r = 0;
0210 
0211     if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
0212         data = 1 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
0213         WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
0214 
0215         r = SOC15_WAIT_ON_RREG(JPEG, 0,
0216             mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS_UVDJ_PWR_ON,
0217             UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
0218 
0219         if (r) {
0220             DRM_ERROR("amdgpu: JPEG disable power gating failed\n");
0221             return r;
0222         }
0223     }
0224 
0225     /* Removing the anti hang mechanism to indicate the UVDJ tile is ON */
0226     data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS)) & ~0x1;
0227     WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
0228 
0229     return 0;
0230 }
0231 
0232 static int jpeg_v2_0_enable_power_gating(struct amdgpu_device *adev)
0233 {
0234     if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
0235         uint32_t data;
0236         int r = 0;
0237 
0238         data = RREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS));
0239         data &= ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK;
0240         data |=  0x1; //UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_TILES_OFF;
0241         WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_POWER_STATUS), data);
0242 
0243         data = 2 << UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT;
0244         WREG32(SOC15_REG_OFFSET(JPEG, 0, mmUVD_PGFSM_CONFIG), data);
0245 
0246         r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS,
0247             (2 << UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT),
0248             UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK);
0249 
0250         if (r) {
0251             DRM_ERROR("amdgpu: JPEG enable power gating failed\n");
0252             return r;
0253         }
0254     }
0255 
0256     return 0;
0257 }
0258 
0259 static void jpeg_v2_0_disable_clock_gating(struct amdgpu_device *adev)
0260 {
0261     uint32_t data;
0262 
0263     data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
0264     if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
0265         data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
0266     else
0267         data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
0268 
0269     data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
0270     data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
0271     WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
0272 
0273     data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
0274     data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
0275         | JPEG_CGC_GATE__JPEG2_DEC_MASK
0276         | JPEG_CGC_GATE__JPEG_ENC_MASK
0277         | JPEG_CGC_GATE__JMCIF_MASK
0278         | JPEG_CGC_GATE__JRBBM_MASK);
0279     WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
0280 }
0281 
0282 static void jpeg_v2_0_enable_clock_gating(struct amdgpu_device *adev)
0283 {
0284     uint32_t data;
0285 
0286     data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL);
0287     if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
0288         data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
0289     else
0290         data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
0291 
0292     data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
0293     data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
0294     WREG32_SOC15(JPEG, 0, mmJPEG_CGC_CTRL, data);
0295 
0296     data = RREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE);
0297     data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
0298         |JPEG_CGC_GATE__JPEG2_DEC_MASK
0299         |JPEG_CGC_GATE__JPEG_ENC_MASK
0300         |JPEG_CGC_GATE__JMCIF_MASK
0301         |JPEG_CGC_GATE__JRBBM_MASK);
0302     WREG32_SOC15(JPEG, 0, mmJPEG_CGC_GATE, data);
0303 }
0304 
0305 /**
0306  * jpeg_v2_0_start - start JPEG block
0307  *
0308  * @adev: amdgpu_device pointer
0309  *
0310  * Setup and start the JPEG block
0311  */
0312 static int jpeg_v2_0_start(struct amdgpu_device *adev)
0313 {
0314     struct amdgpu_ring *ring = &adev->jpeg.inst->ring_dec;
0315     int r;
0316 
0317     if (adev->pm.dpm_enabled)
0318         amdgpu_dpm_enable_jpeg(adev, true);
0319 
0320     /* disable power gating */
0321     r = jpeg_v2_0_disable_power_gating(adev);
0322     if (r)
0323         return r;
0324 
0325     /* JPEG disable CGC */
0326     jpeg_v2_0_disable_clock_gating(adev);
0327 
0328     WREG32_SOC15(JPEG, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
0329 
0330     /* enable JMI channel */
0331     WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL), 0,
0332         ~UVD_JMI_CNTL__SOFT_RESET_MASK);
0333 
0334     /* enable System Interrupt for JRBC */
0335     WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmJPEG_SYS_INT_EN),
0336         JPEG_SYS_INT_EN__DJRBC_MASK,
0337         ~JPEG_SYS_INT_EN__DJRBC_MASK);
0338 
0339     WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
0340     WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
0341     WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
0342         lower_32_bits(ring->gpu_addr));
0343     WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
0344         upper_32_bits(ring->gpu_addr));
0345     WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR, 0);
0346     WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, 0);
0347     WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L);
0348     WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
0349     ring->wptr = RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
0350 
0351     return 0;
0352 }
0353 
0354 /**
0355  * jpeg_v2_0_stop - stop JPEG block
0356  *
0357  * @adev: amdgpu_device pointer
0358  *
0359  * stop the JPEG block
0360  */
0361 static int jpeg_v2_0_stop(struct amdgpu_device *adev)
0362 {
0363     int r;
0364 
0365     /* reset JMI */
0366     WREG32_P(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JMI_CNTL),
0367         UVD_JMI_CNTL__SOFT_RESET_MASK,
0368         ~UVD_JMI_CNTL__SOFT_RESET_MASK);
0369 
0370     /* enable JPEG CGC */
0371     jpeg_v2_0_enable_clock_gating(adev);
0372 
0373     /* enable power gating */
0374     r = jpeg_v2_0_enable_power_gating(adev);
0375     if (r)
0376         return r;
0377 
0378     if (adev->pm.dpm_enabled)
0379         amdgpu_dpm_enable_jpeg(adev, false);
0380 
0381     return 0;
0382 }
0383 
0384 /**
0385  * jpeg_v2_0_dec_ring_get_rptr - get read pointer
0386  *
0387  * @ring: amdgpu_ring pointer
0388  *
0389  * Returns the current hardware read pointer
0390  */
0391 static uint64_t jpeg_v2_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
0392 {
0393     struct amdgpu_device *adev = ring->adev;
0394 
0395     return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_RPTR);
0396 }
0397 
0398 /**
0399  * jpeg_v2_0_dec_ring_get_wptr - get write pointer
0400  *
0401  * @ring: amdgpu_ring pointer
0402  *
0403  * Returns the current hardware write pointer
0404  */
0405 static uint64_t jpeg_v2_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
0406 {
0407     struct amdgpu_device *adev = ring->adev;
0408 
0409     if (ring->use_doorbell)
0410         return *ring->wptr_cpu_addr;
0411     else
0412         return RREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR);
0413 }
0414 
0415 /**
0416  * jpeg_v2_0_dec_ring_set_wptr - set write pointer
0417  *
0418  * @ring: amdgpu_ring pointer
0419  *
0420  * Commits the write pointer to the hardware
0421  */
0422 static void jpeg_v2_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
0423 {
0424     struct amdgpu_device *adev = ring->adev;
0425 
0426     if (ring->use_doorbell) {
0427         *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
0428         WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
0429     } else {
0430         WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
0431     }
0432 }
0433 
0434 /**
0435  * jpeg_v2_0_dec_ring_insert_start - insert a start command
0436  *
0437  * @ring: amdgpu_ring pointer
0438  *
0439  * Write a start command to the ring.
0440  */
0441 void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring)
0442 {
0443     amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
0444         0, 0, PACKETJ_TYPE0));
0445     amdgpu_ring_write(ring, 0x68e04);
0446 
0447     amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
0448         0, 0, PACKETJ_TYPE0));
0449     amdgpu_ring_write(ring, 0x80010000);
0450 }
0451 
0452 /**
0453  * jpeg_v2_0_dec_ring_insert_end - insert a end command
0454  *
0455  * @ring: amdgpu_ring pointer
0456  *
0457  * Write a end command to the ring.
0458  */
0459 void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring)
0460 {
0461     amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
0462         0, 0, PACKETJ_TYPE0));
0463     amdgpu_ring_write(ring, 0x68e04);
0464 
0465     amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
0466         0, 0, PACKETJ_TYPE0));
0467     amdgpu_ring_write(ring, 0x00010000);
0468 }
0469 
0470 /**
0471  * jpeg_v2_0_dec_ring_emit_fence - emit an fence & trap command
0472  *
0473  * @ring: amdgpu_ring pointer
0474  * @addr: address
0475  * @seq: sequence number
0476  * @flags: fence related flags
0477  *
0478  * Write a fence and a trap command to the ring.
0479  */
0480 void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
0481                 unsigned flags)
0482 {
0483     WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
0484 
0485     amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET,
0486         0, 0, PACKETJ_TYPE0));
0487     amdgpu_ring_write(ring, seq);
0488 
0489     amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET,
0490         0, 0, PACKETJ_TYPE0));
0491     amdgpu_ring_write(ring, seq);
0492 
0493     amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET,
0494         0, 0, PACKETJ_TYPE0));
0495     amdgpu_ring_write(ring, lower_32_bits(addr));
0496 
0497     amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET,
0498         0, 0, PACKETJ_TYPE0));
0499     amdgpu_ring_write(ring, upper_32_bits(addr));
0500 
0501     amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
0502         0, 0, PACKETJ_TYPE0));
0503     amdgpu_ring_write(ring, 0x8);
0504 
0505     amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET,
0506         0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4));
0507     amdgpu_ring_write(ring, 0);
0508 
0509     amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
0510         0, 0, PACKETJ_TYPE0));
0511     amdgpu_ring_write(ring, 0x3fbc);
0512 
0513     amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
0514         0, 0, PACKETJ_TYPE0));
0515     amdgpu_ring_write(ring, 0x1);
0516 
0517     amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7));
0518     amdgpu_ring_write(ring, 0);
0519 }
0520 
0521 /**
0522  * jpeg_v2_0_dec_ring_emit_ib - execute indirect buffer
0523  *
0524  * @ring: amdgpu_ring pointer
0525  * @job: job to retrieve vmid from
0526  * @ib: indirect buffer to execute
0527  * @flags: unused
0528  *
0529  * Write ring commands to execute the indirect buffer.
0530  */
0531 void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
0532                 struct amdgpu_job *job,
0533                 struct amdgpu_ib *ib,
0534                 uint32_t flags)
0535 {
0536     unsigned vmid = AMDGPU_JOB_GET_VMID(job);
0537 
0538     amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_IH_CTRL_INTERNAL_OFFSET,
0539         0, 0, PACKETJ_TYPE0));
0540     amdgpu_ring_write(ring, (vmid << JPEG_IH_CTRL__IH_VMID__SHIFT));
0541 
0542     amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET,
0543         0, 0, PACKETJ_TYPE0));
0544     amdgpu_ring_write(ring, (vmid | (vmid << 4)));
0545 
0546     amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET,
0547         0, 0, PACKETJ_TYPE0));
0548     amdgpu_ring_write(ring, (vmid | (vmid << 4)));
0549 
0550     amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET,
0551         0, 0, PACKETJ_TYPE0));
0552     amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
0553 
0554     amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET,
0555         0, 0, PACKETJ_TYPE0));
0556     amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
0557 
0558     amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET,
0559         0, 0, PACKETJ_TYPE0));
0560     amdgpu_ring_write(ring, ib->length_dw);
0561 
0562     amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET,
0563         0, 0, PACKETJ_TYPE0));
0564     amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr));
0565 
0566     amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET,
0567         0, 0, PACKETJ_TYPE0));
0568     amdgpu_ring_write(ring, upper_32_bits(ring->gpu_addr));
0569 
0570     amdgpu_ring_write(ring, PACKETJ(0, 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE2));
0571     amdgpu_ring_write(ring, 0);
0572 
0573     amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
0574         0, 0, PACKETJ_TYPE0));
0575     amdgpu_ring_write(ring, 0x01400200);
0576 
0577     amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
0578         0, 0, PACKETJ_TYPE0));
0579     amdgpu_ring_write(ring, 0x2);
0580 
0581     amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_STATUS_INTERNAL_OFFSET,
0582         0, PACKETJ_CONDITION_CHECK3, PACKETJ_TYPE3));
0583     amdgpu_ring_write(ring, 0x2);
0584 }
0585 
0586 void jpeg_v2_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
0587                 uint32_t val, uint32_t mask)
0588 {
0589     uint32_t reg_offset = (reg << 2);
0590 
0591     amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET,
0592         0, 0, PACKETJ_TYPE0));
0593     amdgpu_ring_write(ring, 0x01400200);
0594 
0595     amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET,
0596         0, 0, PACKETJ_TYPE0));
0597     amdgpu_ring_write(ring, val);
0598 
0599     amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
0600         0, 0, PACKETJ_TYPE0));
0601     if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
0602         amdgpu_ring_write(ring, 0);
0603         amdgpu_ring_write(ring,
0604             PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE3));
0605     } else {
0606         amdgpu_ring_write(ring, reg_offset);
0607         amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
0608             0, 0, PACKETJ_TYPE3));
0609     }
0610     amdgpu_ring_write(ring, mask);
0611 }
0612 
0613 void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
0614                 unsigned vmid, uint64_t pd_addr)
0615 {
0616     struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
0617     uint32_t data0, data1, mask;
0618 
0619     pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
0620 
0621     /* wait for register write */
0622     data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
0623     data1 = lower_32_bits(pd_addr);
0624     mask = 0xffffffff;
0625     jpeg_v2_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
0626 }
0627 
0628 void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
0629 {
0630     uint32_t reg_offset = (reg << 2);
0631 
0632     amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
0633         0, 0, PACKETJ_TYPE0));
0634     if (reg_offset >= 0x10000 && reg_offset <= 0x105ff) {
0635         amdgpu_ring_write(ring, 0);
0636         amdgpu_ring_write(ring,
0637             PACKETJ((reg_offset >> 2), 0, 0, PACKETJ_TYPE0));
0638     } else {
0639         amdgpu_ring_write(ring, reg_offset);
0640         amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
0641             0, 0, PACKETJ_TYPE0));
0642     }
0643     amdgpu_ring_write(ring, val);
0644 }
0645 
0646 void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count)
0647 {
0648     int i;
0649 
0650     WARN_ON(ring->wptr % 2 || count % 2);
0651 
0652     for (i = 0; i < count / 2; i++) {
0653         amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6));
0654         amdgpu_ring_write(ring, 0);
0655     }
0656 }
0657 
0658 static bool jpeg_v2_0_is_idle(void *handle)
0659 {
0660     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0661 
0662     return ((RREG32_SOC15(JPEG, 0, mmUVD_JRBC_STATUS) &
0663         UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
0664         UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
0665 }
0666 
0667 static int jpeg_v2_0_wait_for_idle(void *handle)
0668 {
0669     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0670     int ret;
0671 
0672     ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
0673         UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
0674 
0675     return ret;
0676 }
0677 
0678 static int jpeg_v2_0_set_clockgating_state(void *handle,
0679                       enum amd_clockgating_state state)
0680 {
0681     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0682     bool enable = (state == AMD_CG_STATE_GATE);
0683 
0684     if (enable) {
0685         if (!jpeg_v2_0_is_idle(handle))
0686             return -EBUSY;
0687         jpeg_v2_0_enable_clock_gating(adev);
0688     } else {
0689         jpeg_v2_0_disable_clock_gating(adev);
0690     }
0691 
0692     return 0;
0693 }
0694 
0695 static int jpeg_v2_0_set_powergating_state(void *handle,
0696                     enum amd_powergating_state state)
0697 {
0698     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0699     int ret;
0700 
0701     if (state == adev->jpeg.cur_state)
0702         return 0;
0703 
0704     if (state == AMD_PG_STATE_GATE)
0705         ret = jpeg_v2_0_stop(adev);
0706     else
0707         ret = jpeg_v2_0_start(adev);
0708 
0709     if (!ret)
0710         adev->jpeg.cur_state = state;
0711 
0712     return ret;
0713 }
0714 
0715 static int jpeg_v2_0_set_interrupt_state(struct amdgpu_device *adev,
0716                     struct amdgpu_irq_src *source,
0717                     unsigned type,
0718                     enum amdgpu_interrupt_state state)
0719 {
0720     return 0;
0721 }
0722 
0723 static int jpeg_v2_0_process_interrupt(struct amdgpu_device *adev,
0724                       struct amdgpu_irq_src *source,
0725                       struct amdgpu_iv_entry *entry)
0726 {
0727     DRM_DEBUG("IH: JPEG TRAP\n");
0728 
0729     switch (entry->src_id) {
0730     case VCN_2_0__SRCID__JPEG_DECODE:
0731         amdgpu_fence_process(&adev->jpeg.inst->ring_dec);
0732         break;
0733     default:
0734         DRM_ERROR("Unhandled interrupt: %d %d\n",
0735               entry->src_id, entry->src_data[0]);
0736         break;
0737     }
0738 
0739     return 0;
0740 }
0741 
0742 static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = {
0743     .name = "jpeg_v2_0",
0744     .early_init = jpeg_v2_0_early_init,
0745     .late_init = NULL,
0746     .sw_init = jpeg_v2_0_sw_init,
0747     .sw_fini = jpeg_v2_0_sw_fini,
0748     .hw_init = jpeg_v2_0_hw_init,
0749     .hw_fini = jpeg_v2_0_hw_fini,
0750     .suspend = jpeg_v2_0_suspend,
0751     .resume = jpeg_v2_0_resume,
0752     .is_idle = jpeg_v2_0_is_idle,
0753     .wait_for_idle = jpeg_v2_0_wait_for_idle,
0754     .check_soft_reset = NULL,
0755     .pre_soft_reset = NULL,
0756     .soft_reset = NULL,
0757     .post_soft_reset = NULL,
0758     .set_clockgating_state = jpeg_v2_0_set_clockgating_state,
0759     .set_powergating_state = jpeg_v2_0_set_powergating_state,
0760 };
0761 
0762 static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = {
0763     .type = AMDGPU_RING_TYPE_VCN_JPEG,
0764     .align_mask = 0xf,
0765     .vmhub = AMDGPU_MMHUB_0,
0766     .get_rptr = jpeg_v2_0_dec_ring_get_rptr,
0767     .get_wptr = jpeg_v2_0_dec_ring_get_wptr,
0768     .set_wptr = jpeg_v2_0_dec_ring_set_wptr,
0769     .emit_frame_size =
0770         SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
0771         SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
0772         8 + /* jpeg_v2_0_dec_ring_emit_vm_flush */
0773         18 + 18 + /* jpeg_v2_0_dec_ring_emit_fence x2 vm fence */
0774         8 + 16,
0775     .emit_ib_size = 24, /* jpeg_v2_0_dec_ring_emit_ib */
0776     .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
0777     .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
0778     .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
0779     .test_ring = amdgpu_jpeg_dec_ring_test_ring,
0780     .test_ib = amdgpu_jpeg_dec_ring_test_ib,
0781     .insert_nop = jpeg_v2_0_dec_ring_nop,
0782     .insert_start = jpeg_v2_0_dec_ring_insert_start,
0783     .insert_end = jpeg_v2_0_dec_ring_insert_end,
0784     .pad_ib = amdgpu_ring_generic_pad_ib,
0785     .begin_use = amdgpu_jpeg_ring_begin_use,
0786     .end_use = amdgpu_jpeg_ring_end_use,
0787     .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
0788     .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
0789     .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
0790 };
0791 
0792 static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)
0793 {
0794     adev->jpeg.inst->ring_dec.funcs = &jpeg_v2_0_dec_ring_vm_funcs;
0795     DRM_INFO("JPEG decode is enabled in VM mode\n");
0796 }
0797 
0798 static const struct amdgpu_irq_src_funcs jpeg_v2_0_irq_funcs = {
0799     .set = jpeg_v2_0_set_interrupt_state,
0800     .process = jpeg_v2_0_process_interrupt,
0801 };
0802 
0803 static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev)
0804 {
0805     adev->jpeg.inst->irq.num_types = 1;
0806     adev->jpeg.inst->irq.funcs = &jpeg_v2_0_irq_funcs;
0807 }
0808 
0809 const struct amdgpu_ip_block_version jpeg_v2_0_ip_block =
0810 {
0811         .type = AMD_IP_BLOCK_TYPE_JPEG,
0812         .major = 2,
0813         .minor = 0,
0814         .rev = 0,
0815         .funcs = &jpeg_v2_0_ip_funcs,
0816 };
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