amd/amdgpu/hdp_v6_0.c

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include "amdgpu.h"
0024 #include "amdgpu_atombios.h"
0025 #include "hdp_v6_0.h"
0026
0027 #include "hdp/hdp_6_0_0_offset.h"
0028 #include "hdp/hdp_6_0_0_sh_mask.h"
0029 #include <uapi/linux/kfd_ioctl.h>
0030
0031 static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev,
0032                 struct amdgpu_ring *ring)
0033 {
0034     if (!ring || !ring->funcs->emit_wreg)
0035         WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
0036     else
0037         amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
0038 }
0039
0040 static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev,
0041                      bool enable)
0042 {
0043     uint32_t hdp_clk_cntl, hdp_clk_cntl1;
0044     uint32_t hdp_mem_pwr_cntl;
0045
0046     if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
0047                 AMD_CG_SUPPORT_HDP_DS |
0048                 AMD_CG_SUPPORT_HDP_SD)))
0049         return;
0050
0051     hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0,regHDP_CLK_CNTL);
0052     hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
0053
0054     /* Before doing clock/power mode switch,
0055      * forced on IPH & RC clock */
0056     hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
0057                      RC_MEM_CLK_SOFT_OVERRIDE, 1);
0058     WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
0059
0060     /* disable clock and power gating before any changing */
0061     hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
0062                      ATOMIC_MEM_POWER_CTRL_EN, 0);
0063     hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
0064                      ATOMIC_MEM_POWER_LS_EN, 0);
0065     hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
0066                      ATOMIC_MEM_POWER_DS_EN, 0);
0067     hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
0068                      ATOMIC_MEM_POWER_SD_EN, 0);
0069     hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
0070                      RC_MEM_POWER_CTRL_EN, 0);
0071     hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
0072                      RC_MEM_POWER_LS_EN, 0);
0073     hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
0074                      RC_MEM_POWER_DS_EN, 0);
0075     hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
0076                      RC_MEM_POWER_SD_EN, 0);
0077     WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
0078
0079     /* Already disabled above. The actions below are for "enabled" only */
0080     if (enable) {
0081         /* only one clock gating mode (LS/DS/SD) can be enabled */
0082         if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
0083             hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
0084                              HDP_MEM_POWER_CTRL,
0085                              ATOMIC_MEM_POWER_SD_EN, 1);
0086             hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
0087                              HDP_MEM_POWER_CTRL,
0088                              RC_MEM_POWER_SD_EN, 1);
0089         } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
0090             hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
0091                              HDP_MEM_POWER_CTRL,
0092                              ATOMIC_MEM_POWER_LS_EN, 1);
0093             hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
0094                              HDP_MEM_POWER_CTRL,
0095                              RC_MEM_POWER_LS_EN, 1);
0096         } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
0097             hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
0098                              HDP_MEM_POWER_CTRL,
0099                              ATOMIC_MEM_POWER_DS_EN, 1);
0100             hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
0101                              HDP_MEM_POWER_CTRL,
0102                              RC_MEM_POWER_DS_EN, 1);
0103         }
0104
0105         /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to
0106          * be set for SRAM LS/DS/SD */
0107         if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
0108                       AMD_CG_SUPPORT_HDP_SD)) {
0109             hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
0110                              ATOMIC_MEM_POWER_CTRL_EN, 1);
0111             hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
0112                              RC_MEM_POWER_CTRL_EN, 1);
0113             WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
0114         }
0115     }
0116
0117     /* disable IPH & RC clock override after clock/power mode changing */
0118     hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
0119                      RC_MEM_CLK_SOFT_OVERRIDE, 0);
0120     WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
0121 }
0122
0123 static void hdp_v6_0_get_clockgating_state(struct amdgpu_device *adev,
0124                         u64 *flags)
0125 {
0126     uint32_t tmp;
0127
0128     /* AMD_CG_SUPPORT_HDP_LS/DS/SD */
0129     tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
0130     if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK)
0131         *flags |= AMD_CG_SUPPORT_HDP_LS;
0132     else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK)
0133         *flags |= AMD_CG_SUPPORT_HDP_DS;
0134     else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK)
0135         *flags |= AMD_CG_SUPPORT_HDP_SD;
0136 }
0137
0138 const struct amdgpu_hdp_funcs hdp_v6_0_funcs = {
0139     .flush_hdp = hdp_v6_0_flush_hdp,
0140     .update_clock_gating = hdp_v6_0_update_clock_gating,
0141     .get_clock_gating_state = hdp_v6_0_get_clockgating_state,
0142 };