Back to home page

OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2014 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #include <linux/firmware.h>
0025 #include <linux/module.h>
0026 #include <linux/pci.h>
0027 
0028 #include <drm/drm_cache.h>
0029 #include "amdgpu.h"
0030 #include "gmc_v8_0.h"
0031 #include "amdgpu_ucode.h"
0032 #include "amdgpu_amdkfd.h"
0033 #include "amdgpu_gem.h"
0034 
0035 #include "gmc/gmc_8_1_d.h"
0036 #include "gmc/gmc_8_1_sh_mask.h"
0037 
0038 #include "bif/bif_5_0_d.h"
0039 #include "bif/bif_5_0_sh_mask.h"
0040 
0041 #include "oss/oss_3_0_d.h"
0042 #include "oss/oss_3_0_sh_mask.h"
0043 
0044 #include "dce/dce_10_0_d.h"
0045 #include "dce/dce_10_0_sh_mask.h"
0046 
0047 #include "vid.h"
0048 #include "vi.h"
0049 
0050 #include "amdgpu_atombios.h"
0051 
0052 #include "ivsrcid/ivsrcid_vislands30.h"
0053 
0054 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev);
0055 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
0056 static int gmc_v8_0_wait_for_idle(void *handle);
0057 
0058 MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
0059 MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
0060 MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
0061 MODULE_FIRMWARE("amdgpu/polaris12_mc.bin");
0062 MODULE_FIRMWARE("amdgpu/polaris12_32_mc.bin");
0063 MODULE_FIRMWARE("amdgpu/polaris11_k_mc.bin");
0064 MODULE_FIRMWARE("amdgpu/polaris10_k_mc.bin");
0065 MODULE_FIRMWARE("amdgpu/polaris12_k_mc.bin");
0066 
0067 static const u32 golden_settings_tonga_a11[] =
0068 {
0069     mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
0070     mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
0071     mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
0072     mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
0073     mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
0074     mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
0075     mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
0076 };
0077 
0078 static const u32 tonga_mgcg_cgcg_init[] =
0079 {
0080     mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
0081 };
0082 
0083 static const u32 golden_settings_fiji_a10[] =
0084 {
0085     mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
0086     mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
0087     mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
0088     mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
0089 };
0090 
0091 static const u32 fiji_mgcg_cgcg_init[] =
0092 {
0093     mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
0094 };
0095 
0096 static const u32 golden_settings_polaris11_a11[] =
0097 {
0098     mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
0099     mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
0100     mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
0101     mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
0102 };
0103 
0104 static const u32 golden_settings_polaris10_a11[] =
0105 {
0106     mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
0107     mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
0108     mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
0109     mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
0110     mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
0111 };
0112 
0113 static const u32 cz_mgcg_cgcg_init[] =
0114 {
0115     mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
0116 };
0117 
0118 static const u32 stoney_mgcg_cgcg_init[] =
0119 {
0120     mmATC_MISC_CG, 0xffffffff, 0x000c0200,
0121     mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
0122 };
0123 
0124 static const u32 golden_settings_stoney_common[] =
0125 {
0126     mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
0127     mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
0128 };
0129 
0130 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
0131 {
0132     switch (adev->asic_type) {
0133     case CHIP_FIJI:
0134         amdgpu_device_program_register_sequence(adev,
0135                             fiji_mgcg_cgcg_init,
0136                             ARRAY_SIZE(fiji_mgcg_cgcg_init));
0137         amdgpu_device_program_register_sequence(adev,
0138                             golden_settings_fiji_a10,
0139                             ARRAY_SIZE(golden_settings_fiji_a10));
0140         break;
0141     case CHIP_TONGA:
0142         amdgpu_device_program_register_sequence(adev,
0143                             tonga_mgcg_cgcg_init,
0144                             ARRAY_SIZE(tonga_mgcg_cgcg_init));
0145         amdgpu_device_program_register_sequence(adev,
0146                             golden_settings_tonga_a11,
0147                             ARRAY_SIZE(golden_settings_tonga_a11));
0148         break;
0149     case CHIP_POLARIS11:
0150     case CHIP_POLARIS12:
0151     case CHIP_VEGAM:
0152         amdgpu_device_program_register_sequence(adev,
0153                             golden_settings_polaris11_a11,
0154                             ARRAY_SIZE(golden_settings_polaris11_a11));
0155         break;
0156     case CHIP_POLARIS10:
0157         amdgpu_device_program_register_sequence(adev,
0158                             golden_settings_polaris10_a11,
0159                             ARRAY_SIZE(golden_settings_polaris10_a11));
0160         break;
0161     case CHIP_CARRIZO:
0162         amdgpu_device_program_register_sequence(adev,
0163                             cz_mgcg_cgcg_init,
0164                             ARRAY_SIZE(cz_mgcg_cgcg_init));
0165         break;
0166     case CHIP_STONEY:
0167         amdgpu_device_program_register_sequence(adev,
0168                             stoney_mgcg_cgcg_init,
0169                             ARRAY_SIZE(stoney_mgcg_cgcg_init));
0170         amdgpu_device_program_register_sequence(adev,
0171                             golden_settings_stoney_common,
0172                             ARRAY_SIZE(golden_settings_stoney_common));
0173         break;
0174     default:
0175         break;
0176     }
0177 }
0178 
0179 static void gmc_v8_0_mc_stop(struct amdgpu_device *adev)
0180 {
0181     u32 blackout;
0182 
0183     gmc_v8_0_wait_for_idle(adev);
0184 
0185     blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
0186     if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
0187         /* Block CPU access */
0188         WREG32(mmBIF_FB_EN, 0);
0189         /* blackout the MC */
0190         blackout = REG_SET_FIELD(blackout,
0191                      MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
0192         WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
0193     }
0194     /* wait for the MC to settle */
0195     udelay(100);
0196 }
0197 
0198 static void gmc_v8_0_mc_resume(struct amdgpu_device *adev)
0199 {
0200     u32 tmp;
0201 
0202     /* unblackout the MC */
0203     tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
0204     tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
0205     WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
0206     /* allow CPU access */
0207     tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
0208     tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
0209     WREG32(mmBIF_FB_EN, tmp);
0210 }
0211 
0212 /**
0213  * gmc_v8_0_init_microcode - load ucode images from disk
0214  *
0215  * @adev: amdgpu_device pointer
0216  *
0217  * Use the firmware interface to load the ucode images into
0218  * the driver (not loaded into hw).
0219  * Returns 0 on success, error on failure.
0220  */
0221 static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
0222 {
0223     const char *chip_name;
0224     char fw_name[30];
0225     int err;
0226 
0227     DRM_DEBUG("\n");
0228 
0229     switch (adev->asic_type) {
0230     case CHIP_TONGA:
0231         chip_name = "tonga";
0232         break;
0233     case CHIP_POLARIS11:
0234         if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
0235             ASICID_IS_P31(adev->pdev->device, adev->pdev->revision))
0236             chip_name = "polaris11_k";
0237         else
0238             chip_name = "polaris11";
0239         break;
0240     case CHIP_POLARIS10:
0241         if (ASICID_IS_P30(adev->pdev->device, adev->pdev->revision))
0242             chip_name = "polaris10_k";
0243         else
0244             chip_name = "polaris10";
0245         break;
0246     case CHIP_POLARIS12:
0247         if (ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) {
0248             chip_name = "polaris12_k";
0249         } else {
0250             WREG32(mmMC_SEQ_IO_DEBUG_INDEX, ixMC_IO_DEBUG_UP_159);
0251             /* Polaris12 32bit ASIC needs a special MC firmware */
0252             if (RREG32(mmMC_SEQ_IO_DEBUG_DATA) == 0x05b4dc40)
0253                 chip_name = "polaris12_32";
0254             else
0255                 chip_name = "polaris12";
0256         }
0257         break;
0258     case CHIP_FIJI:
0259     case CHIP_CARRIZO:
0260     case CHIP_STONEY:
0261     case CHIP_VEGAM:
0262         return 0;
0263     default: BUG();
0264     }
0265 
0266     snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
0267     err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);
0268     if (err)
0269         goto out;
0270     err = amdgpu_ucode_validate(adev->gmc.fw);
0271 
0272 out:
0273     if (err) {
0274         pr_err("mc: Failed to load firmware \"%s\"\n", fw_name);
0275         release_firmware(adev->gmc.fw);
0276         adev->gmc.fw = NULL;
0277     }
0278     return err;
0279 }
0280 
0281 /**
0282  * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw
0283  *
0284  * @adev: amdgpu_device pointer
0285  *
0286  * Load the GDDR MC ucode into the hw (VI).
0287  * Returns 0 on success, error on failure.
0288  */
0289 static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
0290 {
0291     const struct mc_firmware_header_v1_0 *hdr;
0292     const __le32 *fw_data = NULL;
0293     const __le32 *io_mc_regs = NULL;
0294     u32 running;
0295     int i, ucode_size, regs_size;
0296 
0297     /* Skip MC ucode loading on SR-IOV capable boards.
0298      * vbios does this for us in asic_init in that case.
0299      * Skip MC ucode loading on VF, because hypervisor will do that
0300      * for this adaptor.
0301      */
0302     if (amdgpu_sriov_bios(adev))
0303         return 0;
0304 
0305     if (!adev->gmc.fw)
0306         return -EINVAL;
0307 
0308     hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
0309     amdgpu_ucode_print_mc_hdr(&hdr->header);
0310 
0311     adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
0312     regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
0313     io_mc_regs = (const __le32 *)
0314         (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
0315     ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
0316     fw_data = (const __le32 *)
0317         (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
0318 
0319     running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
0320 
0321     if (running == 0) {
0322         /* reset the engine and set to writable */
0323         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
0324         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
0325 
0326         /* load mc io regs */
0327         for (i = 0; i < regs_size; i++) {
0328             WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
0329             WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
0330         }
0331         /* load the MC ucode */
0332         for (i = 0; i < ucode_size; i++)
0333             WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
0334 
0335         /* put the engine back into the active state */
0336         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
0337         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
0338         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
0339 
0340         /* wait for training to complete */
0341         for (i = 0; i < adev->usec_timeout; i++) {
0342             if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
0343                       MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
0344                 break;
0345             udelay(1);
0346         }
0347         for (i = 0; i < adev->usec_timeout; i++) {
0348             if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
0349                       MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
0350                 break;
0351             udelay(1);
0352         }
0353     }
0354 
0355     return 0;
0356 }
0357 
0358 static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
0359 {
0360     const struct mc_firmware_header_v1_0 *hdr;
0361     const __le32 *fw_data = NULL;
0362     const __le32 *io_mc_regs = NULL;
0363     u32 data;
0364     int i, ucode_size, regs_size;
0365 
0366     /* Skip MC ucode loading on SR-IOV capable boards.
0367      * vbios does this for us in asic_init in that case.
0368      * Skip MC ucode loading on VF, because hypervisor will do that
0369      * for this adaptor.
0370      */
0371     if (amdgpu_sriov_bios(adev))
0372         return 0;
0373 
0374     if (!adev->gmc.fw)
0375         return -EINVAL;
0376 
0377     hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
0378     amdgpu_ucode_print_mc_hdr(&hdr->header);
0379 
0380     adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
0381     regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
0382     io_mc_regs = (const __le32 *)
0383         (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
0384     ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
0385     fw_data = (const __le32 *)
0386         (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
0387 
0388     data = RREG32(mmMC_SEQ_MISC0);
0389     data &= ~(0x40);
0390     WREG32(mmMC_SEQ_MISC0, data);
0391 
0392     /* load mc io regs */
0393     for (i = 0; i < regs_size; i++) {
0394         WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
0395         WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
0396     }
0397 
0398     WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
0399     WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
0400 
0401     /* load the MC ucode */
0402     for (i = 0; i < ucode_size; i++)
0403         WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
0404 
0405     /* put the engine back into the active state */
0406     WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
0407     WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
0408     WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
0409 
0410     /* wait for training to complete */
0411     for (i = 0; i < adev->usec_timeout; i++) {
0412         data = RREG32(mmMC_SEQ_MISC0);
0413         if (data & 0x80)
0414             break;
0415         udelay(1);
0416     }
0417 
0418     return 0;
0419 }
0420 
0421 static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
0422                        struct amdgpu_gmc *mc)
0423 {
0424     u64 base = 0;
0425 
0426     if (!amdgpu_sriov_vf(adev))
0427         base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
0428     base <<= 24;
0429 
0430     amdgpu_gmc_vram_location(adev, mc, base);
0431     amdgpu_gmc_gart_location(adev, mc);
0432 }
0433 
0434 /**
0435  * gmc_v8_0_mc_program - program the GPU memory controller
0436  *
0437  * @adev: amdgpu_device pointer
0438  *
0439  * Set the location of vram, gart, and AGP in the GPU's
0440  * physical address space (VI).
0441  */
0442 static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
0443 {
0444     u32 tmp;
0445     int i, j;
0446 
0447     /* Initialize HDP */
0448     for (i = 0, j = 0; i < 32; i++, j += 0x6) {
0449         WREG32((0xb05 + j), 0x00000000);
0450         WREG32((0xb06 + j), 0x00000000);
0451         WREG32((0xb07 + j), 0x00000000);
0452         WREG32((0xb08 + j), 0x00000000);
0453         WREG32((0xb09 + j), 0x00000000);
0454     }
0455     WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
0456 
0457     if (gmc_v8_0_wait_for_idle((void *)adev)) {
0458         dev_warn(adev->dev, "Wait for MC idle timedout !\n");
0459     }
0460     if (adev->mode_info.num_crtc) {
0461         /* Lockout access through VGA aperture*/
0462         tmp = RREG32(mmVGA_HDP_CONTROL);
0463         tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
0464         WREG32(mmVGA_HDP_CONTROL, tmp);
0465 
0466         /* disable VGA render */
0467         tmp = RREG32(mmVGA_RENDER_CONTROL);
0468         tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
0469         WREG32(mmVGA_RENDER_CONTROL, tmp);
0470     }
0471     /* Update configuration */
0472     WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
0473            adev->gmc.vram_start >> 12);
0474     WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
0475            adev->gmc.vram_end >> 12);
0476     WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
0477            adev->vram_scratch.gpu_addr >> 12);
0478 
0479     if (amdgpu_sriov_vf(adev)) {
0480         tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16;
0481         tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF);
0482         WREG32(mmMC_VM_FB_LOCATION, tmp);
0483         /* XXX double check these! */
0484         WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
0485         WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
0486         WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
0487     }
0488 
0489     WREG32(mmMC_VM_AGP_BASE, 0);
0490     WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
0491     WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
0492     if (gmc_v8_0_wait_for_idle((void *)adev)) {
0493         dev_warn(adev->dev, "Wait for MC idle timedout !\n");
0494     }
0495 
0496     WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
0497 
0498     tmp = RREG32(mmHDP_MISC_CNTL);
0499     tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
0500     WREG32(mmHDP_MISC_CNTL, tmp);
0501 
0502     tmp = RREG32(mmHDP_HOST_PATH_CNTL);
0503     WREG32(mmHDP_HOST_PATH_CNTL, tmp);
0504 }
0505 
0506 /**
0507  * gmc_v8_0_mc_init - initialize the memory controller driver params
0508  *
0509  * @adev: amdgpu_device pointer
0510  *
0511  * Look up the amount of vram, vram width, and decide how to place
0512  * vram and gart within the GPU's physical address space (VI).
0513  * Returns 0 for success.
0514  */
0515 static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
0516 {
0517     int r;
0518     u32 tmp;
0519 
0520     adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
0521     if (!adev->gmc.vram_width) {
0522         int chansize, numchan;
0523 
0524         /* Get VRAM informations */
0525         tmp = RREG32(mmMC_ARB_RAMCFG);
0526         if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
0527             chansize = 64;
0528         } else {
0529             chansize = 32;
0530         }
0531         tmp = RREG32(mmMC_SHARED_CHMAP);
0532         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
0533         case 0:
0534         default:
0535             numchan = 1;
0536             break;
0537         case 1:
0538             numchan = 2;
0539             break;
0540         case 2:
0541             numchan = 4;
0542             break;
0543         case 3:
0544             numchan = 8;
0545             break;
0546         case 4:
0547             numchan = 3;
0548             break;
0549         case 5:
0550             numchan = 6;
0551             break;
0552         case 6:
0553             numchan = 10;
0554             break;
0555         case 7:
0556             numchan = 12;
0557             break;
0558         case 8:
0559             numchan = 16;
0560             break;
0561         }
0562         adev->gmc.vram_width = numchan * chansize;
0563     }
0564     /* size in MB on si */
0565     tmp = RREG32(mmCONFIG_MEMSIZE);
0566     /* some boards may have garbage in the upper 16 bits */
0567     if (tmp & 0xffff0000) {
0568         DRM_INFO("Probable bad vram size: 0x%08x\n", tmp);
0569         if (tmp & 0xffff)
0570             tmp &= 0xffff;
0571     }
0572     adev->gmc.mc_vram_size = tmp * 1024ULL * 1024ULL;
0573     adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
0574 
0575     if (!(adev->flags & AMD_IS_APU)) {
0576         r = amdgpu_device_resize_fb_bar(adev);
0577         if (r)
0578             return r;
0579     }
0580     adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
0581     adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
0582 
0583 #ifdef CONFIG_X86_64
0584     if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) {
0585         adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
0586         adev->gmc.aper_size = adev->gmc.real_vram_size;
0587     }
0588 #endif
0589 
0590     /* In case the PCI BAR is larger than the actual amount of vram */
0591     adev->gmc.visible_vram_size = adev->gmc.aper_size;
0592     if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
0593         adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
0594 
0595     /* set the gart size */
0596     if (amdgpu_gart_size == -1) {
0597         switch (adev->asic_type) {
0598         case CHIP_POLARIS10: /* all engines support GPUVM */
0599         case CHIP_POLARIS11: /* all engines support GPUVM */
0600         case CHIP_POLARIS12: /* all engines support GPUVM */
0601         case CHIP_VEGAM:     /* all engines support GPUVM */
0602         default:
0603             adev->gmc.gart_size = 256ULL << 20;
0604             break;
0605         case CHIP_TONGA:   /* UVD, VCE do not support GPUVM */
0606         case CHIP_FIJI:    /* UVD, VCE do not support GPUVM */
0607         case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
0608         case CHIP_STONEY:  /* UVD does not support GPUVM, DCE SG support */
0609             adev->gmc.gart_size = 1024ULL << 20;
0610             break;
0611         }
0612     } else {
0613         adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
0614     }
0615 
0616     adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
0617     gmc_v8_0_vram_gtt_location(adev, &adev->gmc);
0618 
0619     return 0;
0620 }
0621 
0622 /**
0623  * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid
0624  *
0625  * @adev: amdgpu_device pointer
0626  * @pasid: pasid to be flush
0627  * @flush_type: type of flush
0628  * @all_hub: flush all hubs
0629  *
0630  * Flush the TLB for the requested pasid.
0631  */
0632 static int gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
0633                     uint16_t pasid, uint32_t flush_type,
0634                     bool all_hub)
0635 {
0636     int vmid;
0637     unsigned int tmp;
0638 
0639     if (amdgpu_in_reset(adev))
0640         return -EIO;
0641 
0642     for (vmid = 1; vmid < 16; vmid++) {
0643 
0644         tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
0645         if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
0646             (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
0647             WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
0648             RREG32(mmVM_INVALIDATE_RESPONSE);
0649             break;
0650         }
0651     }
0652 
0653     return 0;
0654 
0655 }
0656 
0657 /*
0658  * GART
0659  * VMID 0 is the physical GPU addresses as used by the kernel.
0660  * VMIDs 1-15 are used for userspace clients and are handled
0661  * by the amdgpu vm/hsa code.
0662  */
0663 
0664 /**
0665  * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback
0666  *
0667  * @adev: amdgpu_device pointer
0668  * @vmid: vm instance to flush
0669  * @vmhub: which hub to flush
0670  * @flush_type: type of flush
0671  *
0672  * Flush the TLB for the requested page table (VI).
0673  */
0674 static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
0675                     uint32_t vmhub, uint32_t flush_type)
0676 {
0677     /* bits 0-15 are the VM contexts0-15 */
0678     WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
0679 }
0680 
0681 static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
0682                         unsigned vmid, uint64_t pd_addr)
0683 {
0684     uint32_t reg;
0685 
0686     if (vmid < 8)
0687         reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
0688     else
0689         reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
0690     amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
0691 
0692     /* bits 0-15 are the VM contexts0-15 */
0693     amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
0694 
0695     return pd_addr;
0696 }
0697 
0698 static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
0699                     unsigned pasid)
0700 {
0701     amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
0702 }
0703 
0704 /*
0705  * PTE format on VI:
0706  * 63:40 reserved
0707  * 39:12 4k physical page base address
0708  * 11:7 fragment
0709  * 6 write
0710  * 5 read
0711  * 4 exe
0712  * 3 reserved
0713  * 2 snooped
0714  * 1 system
0715  * 0 valid
0716  *
0717  * PDE format on VI:
0718  * 63:59 block fragment size
0719  * 58:40 reserved
0720  * 39:1 physical base address of PTE
0721  * bits 5:1 must be 0.
0722  * 0 valid
0723  */
0724 
0725 static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level,
0726                 uint64_t *addr, uint64_t *flags)
0727 {
0728     BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
0729 }
0730 
0731 static void gmc_v8_0_get_vm_pte(struct amdgpu_device *adev,
0732                 struct amdgpu_bo_va_mapping *mapping,
0733                 uint64_t *flags)
0734 {
0735     *flags &= ~AMDGPU_PTE_EXECUTABLE;
0736     *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
0737     *flags &= ~AMDGPU_PTE_PRT;
0738 }
0739 
0740 /**
0741  * gmc_v8_0_set_fault_enable_default - update VM fault handling
0742  *
0743  * @adev: amdgpu_device pointer
0744  * @value: true redirects VM faults to the default page
0745  */
0746 static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
0747                           bool value)
0748 {
0749     u32 tmp;
0750 
0751     tmp = RREG32(mmVM_CONTEXT1_CNTL);
0752     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0753                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0754     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0755                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0756     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0757                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0758     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0759                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0760     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0761                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0762     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0763                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0764     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0765                 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0766     WREG32(mmVM_CONTEXT1_CNTL, tmp);
0767 }
0768 
0769 /**
0770  * gmc_v8_0_set_prt - set PRT VM fault
0771  *
0772  * @adev: amdgpu_device pointer
0773  * @enable: enable/disable VM fault handling for PRT
0774 */
0775 static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
0776 {
0777     u32 tmp;
0778 
0779     if (enable && !adev->gmc.prt_warning) {
0780         dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
0781         adev->gmc.prt_warning = true;
0782     }
0783 
0784     tmp = RREG32(mmVM_PRT_CNTL);
0785     tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
0786                 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
0787     tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
0788                 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
0789     tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
0790                 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
0791     tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
0792                 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
0793     tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
0794                 L2_CACHE_STORE_INVALID_ENTRIES, enable);
0795     tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
0796                 L1_TLB_STORE_INVALID_ENTRIES, enable);
0797     tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
0798                 MASK_PDE0_FAULT, enable);
0799     WREG32(mmVM_PRT_CNTL, tmp);
0800 
0801     if (enable) {
0802         uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
0803         uint32_t high = adev->vm_manager.max_pfn -
0804             (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
0805 
0806         WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
0807         WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
0808         WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
0809         WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
0810         WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
0811         WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
0812         WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
0813         WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
0814     } else {
0815         WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
0816         WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
0817         WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
0818         WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
0819         WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
0820         WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
0821         WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
0822         WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
0823     }
0824 }
0825 
0826 /**
0827  * gmc_v8_0_gart_enable - gart enable
0828  *
0829  * @adev: amdgpu_device pointer
0830  *
0831  * This sets up the TLBs, programs the page tables for VMID0,
0832  * sets up the hw for VMIDs 1-15 which are allocated on
0833  * demand, and sets up the global locations for the LDS, GDS,
0834  * and GPUVM for FSA64 clients (VI).
0835  * Returns 0 for success, errors for failure.
0836  */
0837 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
0838 {
0839     uint64_t table_addr;
0840     u32 tmp, field;
0841     int i;
0842 
0843     if (adev->gart.bo == NULL) {
0844         dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
0845         return -EINVAL;
0846     }
0847     amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
0848     table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
0849 
0850     /* Setup TLB control */
0851     tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
0852     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
0853     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
0854     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
0855     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
0856     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
0857     WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
0858     /* Setup L2 cache */
0859     tmp = RREG32(mmVM_L2_CNTL);
0860     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
0861     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
0862     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
0863     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
0864     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
0865     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
0866     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
0867     WREG32(mmVM_L2_CNTL, tmp);
0868     tmp = RREG32(mmVM_L2_CNTL2);
0869     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
0870     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
0871     WREG32(mmVM_L2_CNTL2, tmp);
0872 
0873     field = adev->vm_manager.fragment_size;
0874     tmp = RREG32(mmVM_L2_CNTL3);
0875     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
0876     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
0877     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
0878     WREG32(mmVM_L2_CNTL3, tmp);
0879     /* XXX: set to enable PTE/PDE in system memory */
0880     tmp = RREG32(mmVM_L2_CNTL4);
0881     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
0882     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
0883     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
0884     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
0885     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
0886     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
0887     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
0888     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
0889     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
0890     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
0891     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
0892     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
0893     WREG32(mmVM_L2_CNTL4, tmp);
0894     /* setup context0 */
0895     WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
0896     WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
0897     WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
0898     WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
0899             (u32)(adev->dummy_page_addr >> 12));
0900     WREG32(mmVM_CONTEXT0_CNTL2, 0);
0901     tmp = RREG32(mmVM_CONTEXT0_CNTL);
0902     tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
0903     tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
0904     tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0905     WREG32(mmVM_CONTEXT0_CNTL, tmp);
0906 
0907     WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
0908     WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
0909     WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
0910 
0911     /* empty context1-15 */
0912     /* FIXME start with 4G, once using 2 level pt switch to full
0913      * vm size space
0914      */
0915     /* set vm size, must be a multiple of 4 */
0916     WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
0917     WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
0918     for (i = 1; i < AMDGPU_NUM_VMID; i++) {
0919         if (i < 8)
0920             WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
0921                    table_addr >> 12);
0922         else
0923             WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
0924                    table_addr >> 12);
0925     }
0926 
0927     /* enable context1-15 */
0928     WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
0929            (u32)(adev->dummy_page_addr >> 12));
0930     WREG32(mmVM_CONTEXT1_CNTL2, 4);
0931     tmp = RREG32(mmVM_CONTEXT1_CNTL);
0932     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
0933     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
0934     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0935     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0936     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0937     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0938     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0939     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0940     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0941     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
0942                 adev->vm_manager.block_size - 9);
0943     WREG32(mmVM_CONTEXT1_CNTL, tmp);
0944     if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
0945         gmc_v8_0_set_fault_enable_default(adev, false);
0946     else
0947         gmc_v8_0_set_fault_enable_default(adev, true);
0948 
0949     gmc_v8_0_flush_gpu_tlb(adev, 0, 0, 0);
0950     DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
0951          (unsigned)(adev->gmc.gart_size >> 20),
0952          (unsigned long long)table_addr);
0953     return 0;
0954 }
0955 
0956 static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
0957 {
0958     int r;
0959 
0960     if (adev->gart.bo) {
0961         WARN(1, "R600 PCIE GART already initialized\n");
0962         return 0;
0963     }
0964     /* Initialize common gart structure */
0965     r = amdgpu_gart_init(adev);
0966     if (r)
0967         return r;
0968     adev->gart.table_size = adev->gart.num_gpu_pages * 8;
0969     adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE;
0970     return amdgpu_gart_table_vram_alloc(adev);
0971 }
0972 
0973 /**
0974  * gmc_v8_0_gart_disable - gart disable
0975  *
0976  * @adev: amdgpu_device pointer
0977  *
0978  * This disables all VM page table (VI).
0979  */
0980 static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
0981 {
0982     u32 tmp;
0983 
0984     /* Disable all tables */
0985     WREG32(mmVM_CONTEXT0_CNTL, 0);
0986     WREG32(mmVM_CONTEXT1_CNTL, 0);
0987     /* Setup TLB control */
0988     tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
0989     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
0990     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
0991     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
0992     WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
0993     /* Setup L2 cache */
0994     tmp = RREG32(mmVM_L2_CNTL);
0995     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
0996     WREG32(mmVM_L2_CNTL, tmp);
0997     WREG32(mmVM_L2_CNTL2, 0);
0998 }
0999 
1000 /**
1001  * gmc_v8_0_vm_decode_fault - print human readable fault info
1002  *
1003  * @adev: amdgpu_device pointer
1004  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
1005  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
1006  * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value
1007  * @pasid: debug logging only - no functional use
1008  *
1009  * Print human readable fault information (VI).
1010  */
1011 static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
1012                      u32 addr, u32 mc_client, unsigned pasid)
1013 {
1014     u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
1015     u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1016                     PROTECTIONS);
1017     char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
1018         (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
1019     u32 mc_id;
1020 
1021     mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1022                   MEMORY_CLIENT_ID);
1023 
1024     dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
1025            protections, vmid, pasid, addr,
1026            REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1027                  MEMORY_CLIENT_RW) ?
1028            "write" : "read", block, mc_client, mc_id);
1029 }
1030 
1031 static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
1032 {
1033     switch (mc_seq_vram_type) {
1034     case MC_SEQ_MISC0__MT__GDDR1:
1035         return AMDGPU_VRAM_TYPE_GDDR1;
1036     case MC_SEQ_MISC0__MT__DDR2:
1037         return AMDGPU_VRAM_TYPE_DDR2;
1038     case MC_SEQ_MISC0__MT__GDDR3:
1039         return AMDGPU_VRAM_TYPE_GDDR3;
1040     case MC_SEQ_MISC0__MT__GDDR4:
1041         return AMDGPU_VRAM_TYPE_GDDR4;
1042     case MC_SEQ_MISC0__MT__GDDR5:
1043         return AMDGPU_VRAM_TYPE_GDDR5;
1044     case MC_SEQ_MISC0__MT__HBM:
1045         return AMDGPU_VRAM_TYPE_HBM;
1046     case MC_SEQ_MISC0__MT__DDR3:
1047         return AMDGPU_VRAM_TYPE_DDR3;
1048     default:
1049         return AMDGPU_VRAM_TYPE_UNKNOWN;
1050     }
1051 }
1052 
1053 static int gmc_v8_0_early_init(void *handle)
1054 {
1055     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1056 
1057     gmc_v8_0_set_gmc_funcs(adev);
1058     gmc_v8_0_set_irq_funcs(adev);
1059 
1060     adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1061     adev->gmc.shared_aperture_end =
1062         adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1063     adev->gmc.private_aperture_start =
1064         adev->gmc.shared_aperture_end + 1;
1065     adev->gmc.private_aperture_end =
1066         adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1067 
1068     return 0;
1069 }
1070 
1071 static int gmc_v8_0_late_init(void *handle)
1072 {
1073     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1074 
1075     if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
1076         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1077     else
1078         return 0;
1079 }
1080 
1081 static unsigned gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev)
1082 {
1083     u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
1084     unsigned size;
1085 
1086     if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1087         size = AMDGPU_VBIOS_VGA_ALLOCATION;
1088     } else {
1089         u32 viewport = RREG32(mmVIEWPORT_SIZE);
1090         size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1091             REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1092             4);
1093     }
1094 
1095     return size;
1096 }
1097 
1098 #define mmMC_SEQ_MISC0_FIJI 0xA71
1099 
1100 static int gmc_v8_0_sw_init(void *handle)
1101 {
1102     int r;
1103     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1104 
1105     adev->num_vmhubs = 1;
1106 
1107     if (adev->flags & AMD_IS_APU) {
1108         adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
1109     } else {
1110         u32 tmp;
1111 
1112         if ((adev->asic_type == CHIP_FIJI) ||
1113             (adev->asic_type == CHIP_VEGAM))
1114             tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
1115         else
1116             tmp = RREG32(mmMC_SEQ_MISC0);
1117         tmp &= MC_SEQ_MISC0__MT__MASK;
1118         adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp);
1119     }
1120 
1121     r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
1122     if (r)
1123         return r;
1124 
1125     r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
1126     if (r)
1127         return r;
1128 
1129     /* Adjust VM size here.
1130      * Currently set to 4GB ((1 << 20) 4k pages).
1131      * Max GPUVM size for cayman and SI is 40 bits.
1132      */
1133     amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
1134 
1135     /* Set the internal MC address mask
1136      * This is the max address of the GPU's
1137      * internal address space.
1138      */
1139     adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1140 
1141     r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
1142     if (r) {
1143         pr_warn("No suitable DMA available\n");
1144         return r;
1145     }
1146     adev->need_swiotlb = drm_need_swiotlb(40);
1147 
1148     r = gmc_v8_0_init_microcode(adev);
1149     if (r) {
1150         DRM_ERROR("Failed to load mc firmware!\n");
1151         return r;
1152     }
1153 
1154     r = gmc_v8_0_mc_init(adev);
1155     if (r)
1156         return r;
1157 
1158     amdgpu_gmc_get_vbios_allocations(adev);
1159 
1160     /* Memory manager */
1161     r = amdgpu_bo_init(adev);
1162     if (r)
1163         return r;
1164 
1165     r = gmc_v8_0_gart_init(adev);
1166     if (r)
1167         return r;
1168 
1169     /*
1170      * number of VMs
1171      * VMID 0 is reserved for System
1172      * amdgpu graphics/compute will use VMIDs 1-7
1173      * amdkfd will use VMIDs 8-15
1174      */
1175     adev->vm_manager.first_kfd_vmid = 8;
1176     amdgpu_vm_manager_init(adev);
1177 
1178     /* base offset of vram pages */
1179     if (adev->flags & AMD_IS_APU) {
1180         u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1181 
1182         tmp <<= 22;
1183         adev->vm_manager.vram_base_offset = tmp;
1184     } else {
1185         adev->vm_manager.vram_base_offset = 0;
1186     }
1187 
1188     adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info),
1189                     GFP_KERNEL);
1190     if (!adev->gmc.vm_fault_info)
1191         return -ENOMEM;
1192     atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1193 
1194     return 0;
1195 }
1196 
1197 static int gmc_v8_0_sw_fini(void *handle)
1198 {
1199     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1200 
1201     amdgpu_gem_force_release(adev);
1202     amdgpu_vm_manager_fini(adev);
1203     kfree(adev->gmc.vm_fault_info);
1204     amdgpu_gart_table_vram_free(adev);
1205     amdgpu_bo_fini(adev);
1206     release_firmware(adev->gmc.fw);
1207     adev->gmc.fw = NULL;
1208 
1209     return 0;
1210 }
1211 
1212 static int gmc_v8_0_hw_init(void *handle)
1213 {
1214     int r;
1215     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1216 
1217     gmc_v8_0_init_golden_registers(adev);
1218 
1219     gmc_v8_0_mc_program(adev);
1220 
1221     if (adev->asic_type == CHIP_TONGA) {
1222         r = gmc_v8_0_tonga_mc_load_microcode(adev);
1223         if (r) {
1224             DRM_ERROR("Failed to load MC firmware!\n");
1225             return r;
1226         }
1227     } else if (adev->asic_type == CHIP_POLARIS11 ||
1228             adev->asic_type == CHIP_POLARIS10 ||
1229             adev->asic_type == CHIP_POLARIS12) {
1230         r = gmc_v8_0_polaris_mc_load_microcode(adev);
1231         if (r) {
1232             DRM_ERROR("Failed to load MC firmware!\n");
1233             return r;
1234         }
1235     }
1236 
1237     r = gmc_v8_0_gart_enable(adev);
1238     if (r)
1239         return r;
1240 
1241     if (amdgpu_emu_mode == 1)
1242         return amdgpu_gmc_vram_checking(adev);
1243     else
1244         return r;
1245 }
1246 
1247 static int gmc_v8_0_hw_fini(void *handle)
1248 {
1249     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1250 
1251     amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1252     gmc_v8_0_gart_disable(adev);
1253 
1254     return 0;
1255 }
1256 
1257 static int gmc_v8_0_suspend(void *handle)
1258 {
1259     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1260 
1261     gmc_v8_0_hw_fini(adev);
1262 
1263     return 0;
1264 }
1265 
1266 static int gmc_v8_0_resume(void *handle)
1267 {
1268     int r;
1269     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1270 
1271     r = gmc_v8_0_hw_init(adev);
1272     if (r)
1273         return r;
1274 
1275     amdgpu_vmid_reset_all(adev);
1276 
1277     return 0;
1278 }
1279 
1280 static bool gmc_v8_0_is_idle(void *handle)
1281 {
1282     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1283     u32 tmp = RREG32(mmSRBM_STATUS);
1284 
1285     if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1286            SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1287         return false;
1288 
1289     return true;
1290 }
1291 
1292 static int gmc_v8_0_wait_for_idle(void *handle)
1293 {
1294     unsigned i;
1295     u32 tmp;
1296     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1297 
1298     for (i = 0; i < adev->usec_timeout; i++) {
1299         /* read MC_STATUS */
1300         tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1301                            SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1302                            SRBM_STATUS__MCC_BUSY_MASK |
1303                            SRBM_STATUS__MCD_BUSY_MASK |
1304                            SRBM_STATUS__VMC_BUSY_MASK |
1305                            SRBM_STATUS__VMC1_BUSY_MASK);
1306         if (!tmp)
1307             return 0;
1308         udelay(1);
1309     }
1310     return -ETIMEDOUT;
1311 
1312 }
1313 
1314 static bool gmc_v8_0_check_soft_reset(void *handle)
1315 {
1316     u32 srbm_soft_reset = 0;
1317     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1318     u32 tmp = RREG32(mmSRBM_STATUS);
1319 
1320     if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1321         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1322                         SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1323 
1324     if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1325            SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1326         if (!(adev->flags & AMD_IS_APU))
1327             srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1328                             SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1329     }
1330     if (srbm_soft_reset) {
1331         adev->gmc.srbm_soft_reset = srbm_soft_reset;
1332         return true;
1333     } else {
1334         adev->gmc.srbm_soft_reset = 0;
1335         return false;
1336     }
1337 }
1338 
1339 static int gmc_v8_0_pre_soft_reset(void *handle)
1340 {
1341     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1342 
1343     if (!adev->gmc.srbm_soft_reset)
1344         return 0;
1345 
1346     gmc_v8_0_mc_stop(adev);
1347     if (gmc_v8_0_wait_for_idle(adev)) {
1348         dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1349     }
1350 
1351     return 0;
1352 }
1353 
1354 static int gmc_v8_0_soft_reset(void *handle)
1355 {
1356     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1357     u32 srbm_soft_reset;
1358 
1359     if (!adev->gmc.srbm_soft_reset)
1360         return 0;
1361     srbm_soft_reset = adev->gmc.srbm_soft_reset;
1362 
1363     if (srbm_soft_reset) {
1364         u32 tmp;
1365 
1366         tmp = RREG32(mmSRBM_SOFT_RESET);
1367         tmp |= srbm_soft_reset;
1368         dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1369         WREG32(mmSRBM_SOFT_RESET, tmp);
1370         tmp = RREG32(mmSRBM_SOFT_RESET);
1371 
1372         udelay(50);
1373 
1374         tmp &= ~srbm_soft_reset;
1375         WREG32(mmSRBM_SOFT_RESET, tmp);
1376         tmp = RREG32(mmSRBM_SOFT_RESET);
1377 
1378         /* Wait a little for things to settle down */
1379         udelay(50);
1380     }
1381 
1382     return 0;
1383 }
1384 
1385 static int gmc_v8_0_post_soft_reset(void *handle)
1386 {
1387     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1388 
1389     if (!adev->gmc.srbm_soft_reset)
1390         return 0;
1391 
1392     gmc_v8_0_mc_resume(adev);
1393     return 0;
1394 }
1395 
1396 static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1397                          struct amdgpu_irq_src *src,
1398                          unsigned type,
1399                          enum amdgpu_interrupt_state state)
1400 {
1401     u32 tmp;
1402     u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1403             VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1404             VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1405             VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1406             VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1407             VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1408             VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1409 
1410     switch (state) {
1411     case AMDGPU_IRQ_STATE_DISABLE:
1412         /* system context */
1413         tmp = RREG32(mmVM_CONTEXT0_CNTL);
1414         tmp &= ~bits;
1415         WREG32(mmVM_CONTEXT0_CNTL, tmp);
1416         /* VMs */
1417         tmp = RREG32(mmVM_CONTEXT1_CNTL);
1418         tmp &= ~bits;
1419         WREG32(mmVM_CONTEXT1_CNTL, tmp);
1420         break;
1421     case AMDGPU_IRQ_STATE_ENABLE:
1422         /* system context */
1423         tmp = RREG32(mmVM_CONTEXT0_CNTL);
1424         tmp |= bits;
1425         WREG32(mmVM_CONTEXT0_CNTL, tmp);
1426         /* VMs */
1427         tmp = RREG32(mmVM_CONTEXT1_CNTL);
1428         tmp |= bits;
1429         WREG32(mmVM_CONTEXT1_CNTL, tmp);
1430         break;
1431     default:
1432         break;
1433     }
1434 
1435     return 0;
1436 }
1437 
1438 static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1439                       struct amdgpu_irq_src *source,
1440                       struct amdgpu_iv_entry *entry)
1441 {
1442     u32 addr, status, mc_client, vmid;
1443 
1444     if (amdgpu_sriov_vf(adev)) {
1445         dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1446             entry->src_id, entry->src_data[0]);
1447         dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
1448         return 0;
1449     }
1450 
1451     addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1452     status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1453     mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1454     /* reset addr and status */
1455     WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1456 
1457     if (!addr && !status)
1458         return 0;
1459 
1460     if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1461         gmc_v8_0_set_fault_enable_default(adev, false);
1462 
1463     if (printk_ratelimit()) {
1464         struct amdgpu_task_info task_info;
1465 
1466         memset(&task_info, 0, sizeof(struct amdgpu_task_info));
1467         amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
1468 
1469         dev_err(adev->dev, "GPU fault detected: %d 0x%08x for process %s pid %d thread %s pid %d\n",
1470             entry->src_id, entry->src_data[0], task_info.process_name,
1471             task_info.tgid, task_info.task_name, task_info.pid);
1472         dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1473             addr);
1474         dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1475             status);
1476         gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client,
1477                      entry->pasid);
1478     }
1479 
1480     vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1481                  VMID);
1482     if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)
1483         && !atomic_read(&adev->gmc.vm_fault_info_updated)) {
1484         struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info;
1485         u32 protections = REG_GET_FIELD(status,
1486                     VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1487                     PROTECTIONS);
1488 
1489         info->vmid = vmid;
1490         info->mc_id = REG_GET_FIELD(status,
1491                         VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1492                         MEMORY_CLIENT_ID);
1493         info->status = status;
1494         info->page_addr = addr;
1495         info->prot_valid = protections & 0x7 ? true : false;
1496         info->prot_read = protections & 0x8 ? true : false;
1497         info->prot_write = protections & 0x10 ? true : false;
1498         info->prot_exec = protections & 0x20 ? true : false;
1499         mb();
1500         atomic_set(&adev->gmc.vm_fault_info_updated, 1);
1501     }
1502 
1503     return 0;
1504 }
1505 
1506 static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1507                              bool enable)
1508 {
1509     uint32_t data;
1510 
1511     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1512         data = RREG32(mmMC_HUB_MISC_HUB_CG);
1513         data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1514         WREG32(mmMC_HUB_MISC_HUB_CG, data);
1515 
1516         data = RREG32(mmMC_HUB_MISC_SIP_CG);
1517         data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1518         WREG32(mmMC_HUB_MISC_SIP_CG, data);
1519 
1520         data = RREG32(mmMC_HUB_MISC_VM_CG);
1521         data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1522         WREG32(mmMC_HUB_MISC_VM_CG, data);
1523 
1524         data = RREG32(mmMC_XPB_CLK_GAT);
1525         data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1526         WREG32(mmMC_XPB_CLK_GAT, data);
1527 
1528         data = RREG32(mmATC_MISC_CG);
1529         data |= ATC_MISC_CG__ENABLE_MASK;
1530         WREG32(mmATC_MISC_CG, data);
1531 
1532         data = RREG32(mmMC_CITF_MISC_WR_CG);
1533         data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1534         WREG32(mmMC_CITF_MISC_WR_CG, data);
1535 
1536         data = RREG32(mmMC_CITF_MISC_RD_CG);
1537         data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1538         WREG32(mmMC_CITF_MISC_RD_CG, data);
1539 
1540         data = RREG32(mmMC_CITF_MISC_VM_CG);
1541         data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1542         WREG32(mmMC_CITF_MISC_VM_CG, data);
1543 
1544         data = RREG32(mmVM_L2_CG);
1545         data |= VM_L2_CG__ENABLE_MASK;
1546         WREG32(mmVM_L2_CG, data);
1547     } else {
1548         data = RREG32(mmMC_HUB_MISC_HUB_CG);
1549         data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1550         WREG32(mmMC_HUB_MISC_HUB_CG, data);
1551 
1552         data = RREG32(mmMC_HUB_MISC_SIP_CG);
1553         data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1554         WREG32(mmMC_HUB_MISC_SIP_CG, data);
1555 
1556         data = RREG32(mmMC_HUB_MISC_VM_CG);
1557         data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1558         WREG32(mmMC_HUB_MISC_VM_CG, data);
1559 
1560         data = RREG32(mmMC_XPB_CLK_GAT);
1561         data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1562         WREG32(mmMC_XPB_CLK_GAT, data);
1563 
1564         data = RREG32(mmATC_MISC_CG);
1565         data &= ~ATC_MISC_CG__ENABLE_MASK;
1566         WREG32(mmATC_MISC_CG, data);
1567 
1568         data = RREG32(mmMC_CITF_MISC_WR_CG);
1569         data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1570         WREG32(mmMC_CITF_MISC_WR_CG, data);
1571 
1572         data = RREG32(mmMC_CITF_MISC_RD_CG);
1573         data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1574         WREG32(mmMC_CITF_MISC_RD_CG, data);
1575 
1576         data = RREG32(mmMC_CITF_MISC_VM_CG);
1577         data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1578         WREG32(mmMC_CITF_MISC_VM_CG, data);
1579 
1580         data = RREG32(mmVM_L2_CG);
1581         data &= ~VM_L2_CG__ENABLE_MASK;
1582         WREG32(mmVM_L2_CG, data);
1583     }
1584 }
1585 
1586 static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1587                        bool enable)
1588 {
1589     uint32_t data;
1590 
1591     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1592         data = RREG32(mmMC_HUB_MISC_HUB_CG);
1593         data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1594         WREG32(mmMC_HUB_MISC_HUB_CG, data);
1595 
1596         data = RREG32(mmMC_HUB_MISC_SIP_CG);
1597         data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1598         WREG32(mmMC_HUB_MISC_SIP_CG, data);
1599 
1600         data = RREG32(mmMC_HUB_MISC_VM_CG);
1601         data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1602         WREG32(mmMC_HUB_MISC_VM_CG, data);
1603 
1604         data = RREG32(mmMC_XPB_CLK_GAT);
1605         data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1606         WREG32(mmMC_XPB_CLK_GAT, data);
1607 
1608         data = RREG32(mmATC_MISC_CG);
1609         data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1610         WREG32(mmATC_MISC_CG, data);
1611 
1612         data = RREG32(mmMC_CITF_MISC_WR_CG);
1613         data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1614         WREG32(mmMC_CITF_MISC_WR_CG, data);
1615 
1616         data = RREG32(mmMC_CITF_MISC_RD_CG);
1617         data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1618         WREG32(mmMC_CITF_MISC_RD_CG, data);
1619 
1620         data = RREG32(mmMC_CITF_MISC_VM_CG);
1621         data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1622         WREG32(mmMC_CITF_MISC_VM_CG, data);
1623 
1624         data = RREG32(mmVM_L2_CG);
1625         data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1626         WREG32(mmVM_L2_CG, data);
1627     } else {
1628         data = RREG32(mmMC_HUB_MISC_HUB_CG);
1629         data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1630         WREG32(mmMC_HUB_MISC_HUB_CG, data);
1631 
1632         data = RREG32(mmMC_HUB_MISC_SIP_CG);
1633         data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1634         WREG32(mmMC_HUB_MISC_SIP_CG, data);
1635 
1636         data = RREG32(mmMC_HUB_MISC_VM_CG);
1637         data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1638         WREG32(mmMC_HUB_MISC_VM_CG, data);
1639 
1640         data = RREG32(mmMC_XPB_CLK_GAT);
1641         data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1642         WREG32(mmMC_XPB_CLK_GAT, data);
1643 
1644         data = RREG32(mmATC_MISC_CG);
1645         data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1646         WREG32(mmATC_MISC_CG, data);
1647 
1648         data = RREG32(mmMC_CITF_MISC_WR_CG);
1649         data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1650         WREG32(mmMC_CITF_MISC_WR_CG, data);
1651 
1652         data = RREG32(mmMC_CITF_MISC_RD_CG);
1653         data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1654         WREG32(mmMC_CITF_MISC_RD_CG, data);
1655 
1656         data = RREG32(mmMC_CITF_MISC_VM_CG);
1657         data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1658         WREG32(mmMC_CITF_MISC_VM_CG, data);
1659 
1660         data = RREG32(mmVM_L2_CG);
1661         data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1662         WREG32(mmVM_L2_CG, data);
1663     }
1664 }
1665 
1666 static int gmc_v8_0_set_clockgating_state(void *handle,
1667                       enum amd_clockgating_state state)
1668 {
1669     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1670 
1671     if (amdgpu_sriov_vf(adev))
1672         return 0;
1673 
1674     switch (adev->asic_type) {
1675     case CHIP_FIJI:
1676         fiji_update_mc_medium_grain_clock_gating(adev,
1677                 state == AMD_CG_STATE_GATE);
1678         fiji_update_mc_light_sleep(adev,
1679                 state == AMD_CG_STATE_GATE);
1680         break;
1681     default:
1682         break;
1683     }
1684     return 0;
1685 }
1686 
1687 static int gmc_v8_0_set_powergating_state(void *handle,
1688                       enum amd_powergating_state state)
1689 {
1690     return 0;
1691 }
1692 
1693 static void gmc_v8_0_get_clockgating_state(void *handle, u64 *flags)
1694 {
1695     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1696     int data;
1697 
1698     if (amdgpu_sriov_vf(adev))
1699         *flags = 0;
1700 
1701     /* AMD_CG_SUPPORT_MC_MGCG */
1702     data = RREG32(mmMC_HUB_MISC_HUB_CG);
1703     if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK)
1704         *flags |= AMD_CG_SUPPORT_MC_MGCG;
1705 
1706     /* AMD_CG_SUPPORT_MC_LS */
1707     if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK)
1708         *flags |= AMD_CG_SUPPORT_MC_LS;
1709 }
1710 
1711 static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1712     .name = "gmc_v8_0",
1713     .early_init = gmc_v8_0_early_init,
1714     .late_init = gmc_v8_0_late_init,
1715     .sw_init = gmc_v8_0_sw_init,
1716     .sw_fini = gmc_v8_0_sw_fini,
1717     .hw_init = gmc_v8_0_hw_init,
1718     .hw_fini = gmc_v8_0_hw_fini,
1719     .suspend = gmc_v8_0_suspend,
1720     .resume = gmc_v8_0_resume,
1721     .is_idle = gmc_v8_0_is_idle,
1722     .wait_for_idle = gmc_v8_0_wait_for_idle,
1723     .check_soft_reset = gmc_v8_0_check_soft_reset,
1724     .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1725     .soft_reset = gmc_v8_0_soft_reset,
1726     .post_soft_reset = gmc_v8_0_post_soft_reset,
1727     .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1728     .set_powergating_state = gmc_v8_0_set_powergating_state,
1729     .get_clockgating_state = gmc_v8_0_get_clockgating_state,
1730 };
1731 
1732 static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
1733     .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
1734     .flush_gpu_tlb_pasid = gmc_v8_0_flush_gpu_tlb_pasid,
1735     .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
1736     .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,
1737     .set_prt = gmc_v8_0_set_prt,
1738     .get_vm_pde = gmc_v8_0_get_vm_pde,
1739     .get_vm_pte = gmc_v8_0_get_vm_pte,
1740     .get_vbios_fb_size = gmc_v8_0_get_vbios_fb_size,
1741 };
1742 
1743 static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1744     .set = gmc_v8_0_vm_fault_interrupt_state,
1745     .process = gmc_v8_0_process_interrupt,
1746 };
1747 
1748 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev)
1749 {
1750     adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs;
1751 }
1752 
1753 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1754 {
1755     adev->gmc.vm_fault.num_types = 1;
1756     adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1757 }
1758 
1759 const struct amdgpu_ip_block_version gmc_v8_0_ip_block =
1760 {
1761     .type = AMD_IP_BLOCK_TYPE_GMC,
1762     .major = 8,
1763     .minor = 0,
1764     .rev = 0,
1765     .funcs = &gmc_v8_0_ip_funcs,
1766 };
1767 
1768 const struct amdgpu_ip_block_version gmc_v8_1_ip_block =
1769 {
1770     .type = AMD_IP_BLOCK_TYPE_GMC,
1771     .major = 8,
1772     .minor = 1,
1773     .rev = 0,
1774     .funcs = &gmc_v8_0_ip_funcs,
1775 };
1776 
1777 const struct amdgpu_ip_block_version gmc_v8_5_ip_block =
1778 {
1779     .type = AMD_IP_BLOCK_TYPE_GMC,
1780     .major = 8,
1781     .minor = 5,
1782     .rev = 0,
1783     .funcs = &gmc_v8_0_ip_funcs,
1784 };
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!