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0001 /*
0002  * Copyright 2014 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #include <linux/firmware.h>
0025 #include <linux/module.h>
0026 #include <linux/pci.h>
0027 
0028 #include <drm/drm_cache.h>
0029 #include "amdgpu.h"
0030 #include "cikd.h"
0031 #include "cik.h"
0032 #include "gmc_v7_0.h"
0033 #include "amdgpu_ucode.h"
0034 #include "amdgpu_amdkfd.h"
0035 #include "amdgpu_gem.h"
0036 
0037 #include "bif/bif_4_1_d.h"
0038 #include "bif/bif_4_1_sh_mask.h"
0039 
0040 #include "gmc/gmc_7_1_d.h"
0041 #include "gmc/gmc_7_1_sh_mask.h"
0042 
0043 #include "oss/oss_2_0_d.h"
0044 #include "oss/oss_2_0_sh_mask.h"
0045 
0046 #include "dce/dce_8_0_d.h"
0047 #include "dce/dce_8_0_sh_mask.h"
0048 
0049 #include "amdgpu_atombios.h"
0050 
0051 #include "ivsrcid/ivsrcid_vislands30.h"
0052 
0053 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev);
0054 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev);
0055 static int gmc_v7_0_wait_for_idle(void *handle);
0056 
0057 MODULE_FIRMWARE("amdgpu/bonaire_mc.bin");
0058 MODULE_FIRMWARE("amdgpu/hawaii_mc.bin");
0059 MODULE_FIRMWARE("amdgpu/topaz_mc.bin");
0060 
0061 static const u32 golden_settings_iceland_a11[] =
0062 {
0063     mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
0064     mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
0065     mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
0066     mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
0067 };
0068 
0069 static const u32 iceland_mgcg_cgcg_init[] =
0070 {
0071     mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
0072 };
0073 
0074 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
0075 {
0076     switch (adev->asic_type) {
0077     case CHIP_TOPAZ:
0078         amdgpu_device_program_register_sequence(adev,
0079                             iceland_mgcg_cgcg_init,
0080                             ARRAY_SIZE(iceland_mgcg_cgcg_init));
0081         amdgpu_device_program_register_sequence(adev,
0082                             golden_settings_iceland_a11,
0083                             ARRAY_SIZE(golden_settings_iceland_a11));
0084         break;
0085     default:
0086         break;
0087     }
0088 }
0089 
0090 static void gmc_v7_0_mc_stop(struct amdgpu_device *adev)
0091 {
0092     u32 blackout;
0093 
0094     gmc_v7_0_wait_for_idle((void *)adev);
0095 
0096     blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
0097     if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
0098         /* Block CPU access */
0099         WREG32(mmBIF_FB_EN, 0);
0100         /* blackout the MC */
0101         blackout = REG_SET_FIELD(blackout,
0102                      MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
0103         WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
0104     }
0105     /* wait for the MC to settle */
0106     udelay(100);
0107 }
0108 
0109 static void gmc_v7_0_mc_resume(struct amdgpu_device *adev)
0110 {
0111     u32 tmp;
0112 
0113     /* unblackout the MC */
0114     tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
0115     tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
0116     WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
0117     /* allow CPU access */
0118     tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
0119     tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
0120     WREG32(mmBIF_FB_EN, tmp);
0121 }
0122 
0123 /**
0124  * gmc_v7_0_init_microcode - load ucode images from disk
0125  *
0126  * @adev: amdgpu_device pointer
0127  *
0128  * Use the firmware interface to load the ucode images into
0129  * the driver (not loaded into hw).
0130  * Returns 0 on success, error on failure.
0131  */
0132 static int gmc_v7_0_init_microcode(struct amdgpu_device *adev)
0133 {
0134     const char *chip_name;
0135     char fw_name[30];
0136     int err;
0137 
0138     DRM_DEBUG("\n");
0139 
0140     switch (adev->asic_type) {
0141     case CHIP_BONAIRE:
0142         chip_name = "bonaire";
0143         break;
0144     case CHIP_HAWAII:
0145         chip_name = "hawaii";
0146         break;
0147     case CHIP_TOPAZ:
0148         chip_name = "topaz";
0149         break;
0150     case CHIP_KAVERI:
0151     case CHIP_KABINI:
0152     case CHIP_MULLINS:
0153         return 0;
0154     default: BUG();
0155     }
0156 
0157     snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
0158 
0159     err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);
0160     if (err)
0161         goto out;
0162     err = amdgpu_ucode_validate(adev->gmc.fw);
0163 
0164 out:
0165     if (err) {
0166         pr_err("cik_mc: Failed to load firmware \"%s\"\n", fw_name);
0167         release_firmware(adev->gmc.fw);
0168         adev->gmc.fw = NULL;
0169     }
0170     return err;
0171 }
0172 
0173 /**
0174  * gmc_v7_0_mc_load_microcode - load MC ucode into the hw
0175  *
0176  * @adev: amdgpu_device pointer
0177  *
0178  * Load the GDDR MC ucode into the hw (CIK).
0179  * Returns 0 on success, error on failure.
0180  */
0181 static int gmc_v7_0_mc_load_microcode(struct amdgpu_device *adev)
0182 {
0183     const struct mc_firmware_header_v1_0 *hdr;
0184     const __le32 *fw_data = NULL;
0185     const __le32 *io_mc_regs = NULL;
0186     u32 running;
0187     int i, ucode_size, regs_size;
0188 
0189     if (!adev->gmc.fw)
0190         return -EINVAL;
0191 
0192     hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
0193     amdgpu_ucode_print_mc_hdr(&hdr->header);
0194 
0195     adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
0196     regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
0197     io_mc_regs = (const __le32 *)
0198         (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
0199     ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
0200     fw_data = (const __le32 *)
0201         (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
0202 
0203     running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
0204 
0205     if (running == 0) {
0206         /* reset the engine and set to writable */
0207         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
0208         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
0209 
0210         /* load mc io regs */
0211         for (i = 0; i < regs_size; i++) {
0212             WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
0213             WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
0214         }
0215         /* load the MC ucode */
0216         for (i = 0; i < ucode_size; i++)
0217             WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
0218 
0219         /* put the engine back into the active state */
0220         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
0221         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
0222         WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
0223 
0224         /* wait for training to complete */
0225         for (i = 0; i < adev->usec_timeout; i++) {
0226             if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
0227                       MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
0228                 break;
0229             udelay(1);
0230         }
0231         for (i = 0; i < adev->usec_timeout; i++) {
0232             if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
0233                       MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
0234                 break;
0235             udelay(1);
0236         }
0237     }
0238 
0239     return 0;
0240 }
0241 
0242 static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev,
0243                        struct amdgpu_gmc *mc)
0244 {
0245     u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
0246     base <<= 24;
0247 
0248     amdgpu_gmc_vram_location(adev, mc, base);
0249     amdgpu_gmc_gart_location(adev, mc);
0250 }
0251 
0252 /**
0253  * gmc_v7_0_mc_program - program the GPU memory controller
0254  *
0255  * @adev: amdgpu_device pointer
0256  *
0257  * Set the location of vram, gart, and AGP in the GPU's
0258  * physical address space (CIK).
0259  */
0260 static void gmc_v7_0_mc_program(struct amdgpu_device *adev)
0261 {
0262     u32 tmp;
0263     int i, j;
0264 
0265     /* Initialize HDP */
0266     for (i = 0, j = 0; i < 32; i++, j += 0x6) {
0267         WREG32((0xb05 + j), 0x00000000);
0268         WREG32((0xb06 + j), 0x00000000);
0269         WREG32((0xb07 + j), 0x00000000);
0270         WREG32((0xb08 + j), 0x00000000);
0271         WREG32((0xb09 + j), 0x00000000);
0272     }
0273     WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
0274 
0275     if (gmc_v7_0_wait_for_idle((void *)adev)) {
0276         dev_warn(adev->dev, "Wait for MC idle timedout !\n");
0277     }
0278     if (adev->mode_info.num_crtc) {
0279         /* Lockout access through VGA aperture*/
0280         tmp = RREG32(mmVGA_HDP_CONTROL);
0281         tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
0282         WREG32(mmVGA_HDP_CONTROL, tmp);
0283 
0284         /* disable VGA render */
0285         tmp = RREG32(mmVGA_RENDER_CONTROL);
0286         tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
0287         WREG32(mmVGA_RENDER_CONTROL, tmp);
0288     }
0289     /* Update configuration */
0290     WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
0291            adev->gmc.vram_start >> 12);
0292     WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
0293            adev->gmc.vram_end >> 12);
0294     WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
0295            adev->vram_scratch.gpu_addr >> 12);
0296     WREG32(mmMC_VM_AGP_BASE, 0);
0297     WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
0298     WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
0299     if (gmc_v7_0_wait_for_idle((void *)adev)) {
0300         dev_warn(adev->dev, "Wait for MC idle timedout !\n");
0301     }
0302 
0303     WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
0304 
0305     tmp = RREG32(mmHDP_MISC_CNTL);
0306     tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
0307     WREG32(mmHDP_MISC_CNTL, tmp);
0308 
0309     tmp = RREG32(mmHDP_HOST_PATH_CNTL);
0310     WREG32(mmHDP_HOST_PATH_CNTL, tmp);
0311 }
0312 
0313 /**
0314  * gmc_v7_0_mc_init - initialize the memory controller driver params
0315  *
0316  * @adev: amdgpu_device pointer
0317  *
0318  * Look up the amount of vram, vram width, and decide how to place
0319  * vram and gart within the GPU's physical address space (CIK).
0320  * Returns 0 for success.
0321  */
0322 static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
0323 {
0324     int r;
0325 
0326     adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
0327     if (!adev->gmc.vram_width) {
0328         u32 tmp;
0329         int chansize, numchan;
0330 
0331         /* Get VRAM informations */
0332         tmp = RREG32(mmMC_ARB_RAMCFG);
0333         if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE)) {
0334             chansize = 64;
0335         } else {
0336             chansize = 32;
0337         }
0338         tmp = RREG32(mmMC_SHARED_CHMAP);
0339         switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
0340         case 0:
0341         default:
0342             numchan = 1;
0343             break;
0344         case 1:
0345             numchan = 2;
0346             break;
0347         case 2:
0348             numchan = 4;
0349             break;
0350         case 3:
0351             numchan = 8;
0352             break;
0353         case 4:
0354             numchan = 3;
0355             break;
0356         case 5:
0357             numchan = 6;
0358             break;
0359         case 6:
0360             numchan = 10;
0361             break;
0362         case 7:
0363             numchan = 12;
0364             break;
0365         case 8:
0366             numchan = 16;
0367             break;
0368         }
0369         adev->gmc.vram_width = numchan * chansize;
0370     }
0371     /* size in MB on si */
0372     adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
0373     adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
0374 
0375     if (!(adev->flags & AMD_IS_APU)) {
0376         r = amdgpu_device_resize_fb_bar(adev);
0377         if (r)
0378             return r;
0379     }
0380     adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
0381     adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
0382 
0383 #ifdef CONFIG_X86_64
0384     if ((adev->flags & AMD_IS_APU) &&
0385         adev->gmc.real_vram_size > adev->gmc.aper_size &&
0386         !amdgpu_passthrough(adev)) {
0387         adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
0388         adev->gmc.aper_size = adev->gmc.real_vram_size;
0389     }
0390 #endif
0391 
0392     /* In case the PCI BAR is larger than the actual amount of vram */
0393     adev->gmc.visible_vram_size = adev->gmc.aper_size;
0394     if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
0395         adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
0396 
0397     /* set the gart size */
0398     if (amdgpu_gart_size == -1) {
0399         switch (adev->asic_type) {
0400         case CHIP_TOPAZ:     /* no MM engines */
0401         default:
0402             adev->gmc.gart_size = 256ULL << 20;
0403             break;
0404 #ifdef CONFIG_DRM_AMDGPU_CIK
0405         case CHIP_BONAIRE: /* UVD, VCE do not support GPUVM */
0406         case CHIP_HAWAII:  /* UVD, VCE do not support GPUVM */
0407         case CHIP_KAVERI:  /* UVD, VCE do not support GPUVM */
0408         case CHIP_KABINI:  /* UVD, VCE do not support GPUVM */
0409         case CHIP_MULLINS: /* UVD, VCE do not support GPUVM */
0410             adev->gmc.gart_size = 1024ULL << 20;
0411             break;
0412 #endif
0413         }
0414     } else {
0415         adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
0416     }
0417 
0418     adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
0419     gmc_v7_0_vram_gtt_location(adev, &adev->gmc);
0420 
0421     return 0;
0422 }
0423 
0424 /**
0425  * gmc_v7_0_flush_gpu_tlb_pasid - tlb flush via pasid
0426  *
0427  * @adev: amdgpu_device pointer
0428  * @pasid: pasid to be flush
0429  * @flush_type: type of flush
0430  * @all_hub: flush all hubs
0431  *
0432  * Flush the TLB for the requested pasid.
0433  */
0434 static int gmc_v7_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
0435                     uint16_t pasid, uint32_t flush_type,
0436                     bool all_hub)
0437 {
0438     int vmid;
0439     unsigned int tmp;
0440 
0441     if (amdgpu_in_reset(adev))
0442         return -EIO;
0443 
0444     for (vmid = 1; vmid < 16; vmid++) {
0445 
0446         tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
0447         if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
0448             (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) {
0449             WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
0450             RREG32(mmVM_INVALIDATE_RESPONSE);
0451             break;
0452         }
0453     }
0454 
0455     return 0;
0456 }
0457 
0458 /*
0459  * GART
0460  * VMID 0 is the physical GPU addresses as used by the kernel.
0461  * VMIDs 1-15 are used for userspace clients and are handled
0462  * by the amdgpu vm/hsa code.
0463  */
0464 
0465 /**
0466  * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback
0467  *
0468  * @adev: amdgpu_device pointer
0469  * @vmid: vm instance to flush
0470  * @vmhub: which hub to flush
0471  * @flush_type: type of flush
0472  * *
0473  * Flush the TLB for the requested page table (CIK).
0474  */
0475 static void gmc_v7_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
0476                     uint32_t vmhub, uint32_t flush_type)
0477 {
0478     /* bits 0-15 are the VM contexts0-15 */
0479     WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
0480 }
0481 
0482 static uint64_t gmc_v7_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
0483                         unsigned vmid, uint64_t pd_addr)
0484 {
0485     uint32_t reg;
0486 
0487     if (vmid < 8)
0488         reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
0489     else
0490         reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
0491     amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
0492 
0493     /* bits 0-15 are the VM contexts0-15 */
0494     amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
0495 
0496     return pd_addr;
0497 }
0498 
0499 static void gmc_v7_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
0500                     unsigned pasid)
0501 {
0502     amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
0503 }
0504 
0505 static void gmc_v7_0_get_vm_pde(struct amdgpu_device *adev, int level,
0506                 uint64_t *addr, uint64_t *flags)
0507 {
0508     BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
0509 }
0510 
0511 static void gmc_v7_0_get_vm_pte(struct amdgpu_device *adev,
0512                 struct amdgpu_bo_va_mapping *mapping,
0513                 uint64_t *flags)
0514 {
0515     *flags &= ~AMDGPU_PTE_EXECUTABLE;
0516     *flags &= ~AMDGPU_PTE_PRT;
0517 }
0518 
0519 /**
0520  * gmc_v7_0_set_fault_enable_default - update VM fault handling
0521  *
0522  * @adev: amdgpu_device pointer
0523  * @value: true redirects VM faults to the default page
0524  */
0525 static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
0526                           bool value)
0527 {
0528     u32 tmp;
0529 
0530     tmp = RREG32(mmVM_CONTEXT1_CNTL);
0531     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0532                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0533     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0534                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0535     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0536                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0537     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0538                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0539     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0540                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0541     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0542                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0543     WREG32(mmVM_CONTEXT1_CNTL, tmp);
0544 }
0545 
0546 /**
0547  * gmc_v7_0_set_prt - set PRT VM fault
0548  *
0549  * @adev: amdgpu_device pointer
0550  * @enable: enable/disable VM fault handling for PRT
0551  */
0552 static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
0553 {
0554     uint32_t tmp;
0555 
0556     if (enable && !adev->gmc.prt_warning) {
0557         dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
0558         adev->gmc.prt_warning = true;
0559     }
0560 
0561     tmp = RREG32(mmVM_PRT_CNTL);
0562     tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
0563                 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
0564     tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
0565                 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
0566     tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
0567                 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
0568     tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
0569                 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
0570     tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
0571                 L2_CACHE_STORE_INVALID_ENTRIES, enable);
0572     tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
0573                 L1_TLB_STORE_INVALID_ENTRIES, enable);
0574     tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
0575                 MASK_PDE0_FAULT, enable);
0576     WREG32(mmVM_PRT_CNTL, tmp);
0577 
0578     if (enable) {
0579         uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
0580         uint32_t high = adev->vm_manager.max_pfn -
0581             (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
0582 
0583         WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
0584         WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
0585         WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
0586         WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
0587         WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
0588         WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
0589         WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
0590         WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
0591     } else {
0592         WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
0593         WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
0594         WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
0595         WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
0596         WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
0597         WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
0598         WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
0599         WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
0600     }
0601 }
0602 
0603 /**
0604  * gmc_v7_0_gart_enable - gart enable
0605  *
0606  * @adev: amdgpu_device pointer
0607  *
0608  * This sets up the TLBs, programs the page tables for VMID0,
0609  * sets up the hw for VMIDs 1-15 which are allocated on
0610  * demand, and sets up the global locations for the LDS, GDS,
0611  * and GPUVM for FSA64 clients (CIK).
0612  * Returns 0 for success, errors for failure.
0613  */
0614 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
0615 {
0616     uint64_t table_addr;
0617     u32 tmp, field;
0618     int i;
0619 
0620     if (adev->gart.bo == NULL) {
0621         dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
0622         return -EINVAL;
0623     }
0624     amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
0625     table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
0626 
0627     /* Setup TLB control */
0628     tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
0629     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
0630     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
0631     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
0632     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
0633     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
0634     WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
0635     /* Setup L2 cache */
0636     tmp = RREG32(mmVM_L2_CNTL);
0637     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
0638     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
0639     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
0640     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
0641     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
0642     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
0643     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
0644     WREG32(mmVM_L2_CNTL, tmp);
0645     tmp = REG_SET_FIELD(0, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
0646     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
0647     WREG32(mmVM_L2_CNTL2, tmp);
0648 
0649     field = adev->vm_manager.fragment_size;
0650     tmp = RREG32(mmVM_L2_CNTL3);
0651     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
0652     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
0653     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
0654     WREG32(mmVM_L2_CNTL3, tmp);
0655     /* setup context0 */
0656     WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
0657     WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
0658     WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
0659     WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
0660             (u32)(adev->dummy_page_addr >> 12));
0661     WREG32(mmVM_CONTEXT0_CNTL2, 0);
0662     tmp = RREG32(mmVM_CONTEXT0_CNTL);
0663     tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
0664     tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
0665     tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0666     WREG32(mmVM_CONTEXT0_CNTL, tmp);
0667 
0668     WREG32(0x575, 0);
0669     WREG32(0x576, 0);
0670     WREG32(0x577, 0);
0671 
0672     /* empty context1-15 */
0673     /* FIXME start with 4G, once using 2 level pt switch to full
0674      * vm size space
0675      */
0676     /* set vm size, must be a multiple of 4 */
0677     WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
0678     WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
0679     for (i = 1; i < AMDGPU_NUM_VMID; i++) {
0680         if (i < 8)
0681             WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
0682                    table_addr >> 12);
0683         else
0684             WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
0685                    table_addr >> 12);
0686     }
0687 
0688     /* enable context1-15 */
0689     WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
0690            (u32)(adev->dummy_page_addr >> 12));
0691     WREG32(mmVM_CONTEXT1_CNTL2, 4);
0692     tmp = RREG32(mmVM_CONTEXT1_CNTL);
0693     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
0694     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
0695     tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
0696                 adev->vm_manager.block_size - 9);
0697     WREG32(mmVM_CONTEXT1_CNTL, tmp);
0698     if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
0699         gmc_v7_0_set_fault_enable_default(adev, false);
0700     else
0701         gmc_v7_0_set_fault_enable_default(adev, true);
0702 
0703     if (adev->asic_type == CHIP_KAVERI) {
0704         tmp = RREG32(mmCHUB_CONTROL);
0705         tmp &= ~BYPASS_VM;
0706         WREG32(mmCHUB_CONTROL, tmp);
0707     }
0708 
0709     gmc_v7_0_flush_gpu_tlb(adev, 0, 0, 0);
0710     DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
0711          (unsigned)(adev->gmc.gart_size >> 20),
0712          (unsigned long long)table_addr);
0713     return 0;
0714 }
0715 
0716 static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
0717 {
0718     int r;
0719 
0720     if (adev->gart.bo) {
0721         WARN(1, "R600 PCIE GART already initialized\n");
0722         return 0;
0723     }
0724     /* Initialize common gart structure */
0725     r = amdgpu_gart_init(adev);
0726     if (r)
0727         return r;
0728     adev->gart.table_size = adev->gart.num_gpu_pages * 8;
0729     adev->gart.gart_pte_flags = 0;
0730     return amdgpu_gart_table_vram_alloc(adev);
0731 }
0732 
0733 /**
0734  * gmc_v7_0_gart_disable - gart disable
0735  *
0736  * @adev: amdgpu_device pointer
0737  *
0738  * This disables all VM page table (CIK).
0739  */
0740 static void gmc_v7_0_gart_disable(struct amdgpu_device *adev)
0741 {
0742     u32 tmp;
0743 
0744     /* Disable all tables */
0745     WREG32(mmVM_CONTEXT0_CNTL, 0);
0746     WREG32(mmVM_CONTEXT1_CNTL, 0);
0747     /* Setup TLB control */
0748     tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
0749     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
0750     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
0751     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
0752     WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
0753     /* Setup L2 cache */
0754     tmp = RREG32(mmVM_L2_CNTL);
0755     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
0756     WREG32(mmVM_L2_CNTL, tmp);
0757     WREG32(mmVM_L2_CNTL2, 0);
0758 }
0759 
0760 /**
0761  * gmc_v7_0_vm_decode_fault - print human readable fault info
0762  *
0763  * @adev: amdgpu_device pointer
0764  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
0765  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
0766  * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value
0767  * @pasid: debug logging only - no functional use
0768  *
0769  * Print human readable fault information (CIK).
0770  */
0771 static void gmc_v7_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
0772                      u32 addr, u32 mc_client, unsigned pasid)
0773 {
0774     u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
0775     u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
0776                     PROTECTIONS);
0777     char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
0778         (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
0779     u32 mc_id;
0780 
0781     mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
0782                   MEMORY_CLIENT_ID);
0783 
0784     dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
0785            protections, vmid, pasid, addr,
0786            REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
0787                  MEMORY_CLIENT_RW) ?
0788            "write" : "read", block, mc_client, mc_id);
0789 }
0790 
0791 
0792 static const u32 mc_cg_registers[] = {
0793     mmMC_HUB_MISC_HUB_CG,
0794     mmMC_HUB_MISC_SIP_CG,
0795     mmMC_HUB_MISC_VM_CG,
0796     mmMC_XPB_CLK_GAT,
0797     mmATC_MISC_CG,
0798     mmMC_CITF_MISC_WR_CG,
0799     mmMC_CITF_MISC_RD_CG,
0800     mmMC_CITF_MISC_VM_CG,
0801     mmVM_L2_CG,
0802 };
0803 
0804 static const u32 mc_cg_ls_en[] = {
0805     MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
0806     MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
0807     MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
0808     MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
0809     ATC_MISC_CG__MEM_LS_ENABLE_MASK,
0810     MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
0811     MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
0812     MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
0813     VM_L2_CG__MEM_LS_ENABLE_MASK,
0814 };
0815 
0816 static const u32 mc_cg_en[] = {
0817     MC_HUB_MISC_HUB_CG__ENABLE_MASK,
0818     MC_HUB_MISC_SIP_CG__ENABLE_MASK,
0819     MC_HUB_MISC_VM_CG__ENABLE_MASK,
0820     MC_XPB_CLK_GAT__ENABLE_MASK,
0821     ATC_MISC_CG__ENABLE_MASK,
0822     MC_CITF_MISC_WR_CG__ENABLE_MASK,
0823     MC_CITF_MISC_RD_CG__ENABLE_MASK,
0824     MC_CITF_MISC_VM_CG__ENABLE_MASK,
0825     VM_L2_CG__ENABLE_MASK,
0826 };
0827 
0828 static void gmc_v7_0_enable_mc_ls(struct amdgpu_device *adev,
0829                   bool enable)
0830 {
0831     int i;
0832     u32 orig, data;
0833 
0834     for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
0835         orig = data = RREG32(mc_cg_registers[i]);
0836         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
0837             data |= mc_cg_ls_en[i];
0838         else
0839             data &= ~mc_cg_ls_en[i];
0840         if (data != orig)
0841             WREG32(mc_cg_registers[i], data);
0842     }
0843 }
0844 
0845 static void gmc_v7_0_enable_mc_mgcg(struct amdgpu_device *adev,
0846                     bool enable)
0847 {
0848     int i;
0849     u32 orig, data;
0850 
0851     for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
0852         orig = data = RREG32(mc_cg_registers[i]);
0853         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
0854             data |= mc_cg_en[i];
0855         else
0856             data &= ~mc_cg_en[i];
0857         if (data != orig)
0858             WREG32(mc_cg_registers[i], data);
0859     }
0860 }
0861 
0862 static void gmc_v7_0_enable_bif_mgls(struct amdgpu_device *adev,
0863                      bool enable)
0864 {
0865     u32 orig, data;
0866 
0867     orig = data = RREG32_PCIE(ixPCIE_CNTL2);
0868 
0869     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
0870         data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
0871         data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
0872         data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
0873         data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
0874     } else {
0875         data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
0876         data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
0877         data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
0878         data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
0879     }
0880 
0881     if (orig != data)
0882         WREG32_PCIE(ixPCIE_CNTL2, data);
0883 }
0884 
0885 static void gmc_v7_0_enable_hdp_mgcg(struct amdgpu_device *adev,
0886                      bool enable)
0887 {
0888     u32 orig, data;
0889 
0890     orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
0891 
0892     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
0893         data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
0894     else
0895         data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
0896 
0897     if (orig != data)
0898         WREG32(mmHDP_HOST_PATH_CNTL, data);
0899 }
0900 
0901 static void gmc_v7_0_enable_hdp_ls(struct amdgpu_device *adev,
0902                    bool enable)
0903 {
0904     u32 orig, data;
0905 
0906     orig = data = RREG32(mmHDP_MEM_POWER_LS);
0907 
0908     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
0909         data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
0910     else
0911         data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
0912 
0913     if (orig != data)
0914         WREG32(mmHDP_MEM_POWER_LS, data);
0915 }
0916 
0917 static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type)
0918 {
0919     switch (mc_seq_vram_type) {
0920     case MC_SEQ_MISC0__MT__GDDR1:
0921         return AMDGPU_VRAM_TYPE_GDDR1;
0922     case MC_SEQ_MISC0__MT__DDR2:
0923         return AMDGPU_VRAM_TYPE_DDR2;
0924     case MC_SEQ_MISC0__MT__GDDR3:
0925         return AMDGPU_VRAM_TYPE_GDDR3;
0926     case MC_SEQ_MISC0__MT__GDDR4:
0927         return AMDGPU_VRAM_TYPE_GDDR4;
0928     case MC_SEQ_MISC0__MT__GDDR5:
0929         return AMDGPU_VRAM_TYPE_GDDR5;
0930     case MC_SEQ_MISC0__MT__HBM:
0931         return AMDGPU_VRAM_TYPE_HBM;
0932     case MC_SEQ_MISC0__MT__DDR3:
0933         return AMDGPU_VRAM_TYPE_DDR3;
0934     default:
0935         return AMDGPU_VRAM_TYPE_UNKNOWN;
0936     }
0937 }
0938 
0939 static int gmc_v7_0_early_init(void *handle)
0940 {
0941     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0942 
0943     gmc_v7_0_set_gmc_funcs(adev);
0944     gmc_v7_0_set_irq_funcs(adev);
0945 
0946     adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
0947     adev->gmc.shared_aperture_end =
0948         adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
0949     adev->gmc.private_aperture_start =
0950         adev->gmc.shared_aperture_end + 1;
0951     adev->gmc.private_aperture_end =
0952         adev->gmc.private_aperture_start + (4ULL << 30) - 1;
0953 
0954     return 0;
0955 }
0956 
0957 static int gmc_v7_0_late_init(void *handle)
0958 {
0959     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0960 
0961     if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
0962         return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
0963     else
0964         return 0;
0965 }
0966 
0967 static unsigned gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev)
0968 {
0969     u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
0970     unsigned size;
0971 
0972     if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
0973         size = AMDGPU_VBIOS_VGA_ALLOCATION;
0974     } else {
0975         u32 viewport = RREG32(mmVIEWPORT_SIZE);
0976         size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
0977             REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
0978             4);
0979     }
0980 
0981     return size;
0982 }
0983 
0984 static int gmc_v7_0_sw_init(void *handle)
0985 {
0986     int r;
0987     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0988 
0989     adev->num_vmhubs = 1;
0990 
0991     if (adev->flags & AMD_IS_APU) {
0992         adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
0993     } else {
0994         u32 tmp = RREG32(mmMC_SEQ_MISC0);
0995         tmp &= MC_SEQ_MISC0__MT__MASK;
0996         adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp);
0997     }
0998 
0999     r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
1000     if (r)
1001         return r;
1002 
1003     r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
1004     if (r)
1005         return r;
1006 
1007     /* Adjust VM size here.
1008      * Currently set to 4GB ((1 << 20) 4k pages).
1009      * Max GPUVM size for cayman and SI is 40 bits.
1010      */
1011     amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
1012 
1013     /* Set the internal MC address mask
1014      * This is the max address of the GPU's
1015      * internal address space.
1016      */
1017     adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1018 
1019     r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(40));
1020     if (r) {
1021         pr_warn("No suitable DMA available\n");
1022         return r;
1023     }
1024     adev->need_swiotlb = drm_need_swiotlb(40);
1025 
1026     r = gmc_v7_0_init_microcode(adev);
1027     if (r) {
1028         DRM_ERROR("Failed to load mc firmware!\n");
1029         return r;
1030     }
1031 
1032     r = gmc_v7_0_mc_init(adev);
1033     if (r)
1034         return r;
1035 
1036     amdgpu_gmc_get_vbios_allocations(adev);
1037 
1038     /* Memory manager */
1039     r = amdgpu_bo_init(adev);
1040     if (r)
1041         return r;
1042 
1043     r = gmc_v7_0_gart_init(adev);
1044     if (r)
1045         return r;
1046 
1047     /*
1048      * number of VMs
1049      * VMID 0 is reserved for System
1050      * amdgpu graphics/compute will use VMIDs 1-7
1051      * amdkfd will use VMIDs 8-15
1052      */
1053     adev->vm_manager.first_kfd_vmid = 8;
1054     amdgpu_vm_manager_init(adev);
1055 
1056     /* base offset of vram pages */
1057     if (adev->flags & AMD_IS_APU) {
1058         u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1059 
1060         tmp <<= 22;
1061         adev->vm_manager.vram_base_offset = tmp;
1062     } else {
1063         adev->vm_manager.vram_base_offset = 0;
1064     }
1065 
1066     adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info),
1067                     GFP_KERNEL);
1068     if (!adev->gmc.vm_fault_info)
1069         return -ENOMEM;
1070     atomic_set(&adev->gmc.vm_fault_info_updated, 0);
1071 
1072     return 0;
1073 }
1074 
1075 static int gmc_v7_0_sw_fini(void *handle)
1076 {
1077     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1078 
1079     amdgpu_gem_force_release(adev);
1080     amdgpu_vm_manager_fini(adev);
1081     kfree(adev->gmc.vm_fault_info);
1082     amdgpu_gart_table_vram_free(adev);
1083     amdgpu_bo_fini(adev);
1084     release_firmware(adev->gmc.fw);
1085     adev->gmc.fw = NULL;
1086 
1087     return 0;
1088 }
1089 
1090 static int gmc_v7_0_hw_init(void *handle)
1091 {
1092     int r;
1093     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1094 
1095     gmc_v7_0_init_golden_registers(adev);
1096 
1097     gmc_v7_0_mc_program(adev);
1098 
1099     if (!(adev->flags & AMD_IS_APU)) {
1100         r = gmc_v7_0_mc_load_microcode(adev);
1101         if (r) {
1102             DRM_ERROR("Failed to load MC firmware!\n");
1103             return r;
1104         }
1105     }
1106 
1107     r = gmc_v7_0_gart_enable(adev);
1108     if (r)
1109         return r;
1110 
1111     if (amdgpu_emu_mode == 1)
1112         return amdgpu_gmc_vram_checking(adev);
1113     else
1114         return r;
1115 }
1116 
1117 static int gmc_v7_0_hw_fini(void *handle)
1118 {
1119     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1120 
1121     amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1122     gmc_v7_0_gart_disable(adev);
1123 
1124     return 0;
1125 }
1126 
1127 static int gmc_v7_0_suspend(void *handle)
1128 {
1129     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1130 
1131     gmc_v7_0_hw_fini(adev);
1132 
1133     return 0;
1134 }
1135 
1136 static int gmc_v7_0_resume(void *handle)
1137 {
1138     int r;
1139     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1140 
1141     r = gmc_v7_0_hw_init(adev);
1142     if (r)
1143         return r;
1144 
1145     amdgpu_vmid_reset_all(adev);
1146 
1147     return 0;
1148 }
1149 
1150 static bool gmc_v7_0_is_idle(void *handle)
1151 {
1152     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1153     u32 tmp = RREG32(mmSRBM_STATUS);
1154 
1155     if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1156            SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1157         return false;
1158 
1159     return true;
1160 }
1161 
1162 static int gmc_v7_0_wait_for_idle(void *handle)
1163 {
1164     unsigned i;
1165     u32 tmp;
1166     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1167 
1168     for (i = 0; i < adev->usec_timeout; i++) {
1169         /* read MC_STATUS */
1170         tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1171                            SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1172                            SRBM_STATUS__MCC_BUSY_MASK |
1173                            SRBM_STATUS__MCD_BUSY_MASK |
1174                            SRBM_STATUS__VMC_BUSY_MASK);
1175         if (!tmp)
1176             return 0;
1177         udelay(1);
1178     }
1179     return -ETIMEDOUT;
1180 
1181 }
1182 
1183 static int gmc_v7_0_soft_reset(void *handle)
1184 {
1185     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1186     u32 srbm_soft_reset = 0;
1187     u32 tmp = RREG32(mmSRBM_STATUS);
1188 
1189     if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1190         srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1191                         SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1192 
1193     if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1194            SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1195         if (!(adev->flags & AMD_IS_APU))
1196             srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1197                             SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1198     }
1199 
1200     if (srbm_soft_reset) {
1201         gmc_v7_0_mc_stop(adev);
1202         if (gmc_v7_0_wait_for_idle((void *)adev)) {
1203             dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1204         }
1205 
1206 
1207         tmp = RREG32(mmSRBM_SOFT_RESET);
1208         tmp |= srbm_soft_reset;
1209         dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1210         WREG32(mmSRBM_SOFT_RESET, tmp);
1211         tmp = RREG32(mmSRBM_SOFT_RESET);
1212 
1213         udelay(50);
1214 
1215         tmp &= ~srbm_soft_reset;
1216         WREG32(mmSRBM_SOFT_RESET, tmp);
1217         tmp = RREG32(mmSRBM_SOFT_RESET);
1218 
1219         /* Wait a little for things to settle down */
1220         udelay(50);
1221 
1222         gmc_v7_0_mc_resume(adev);
1223         udelay(50);
1224     }
1225 
1226     return 0;
1227 }
1228 
1229 static int gmc_v7_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1230                          struct amdgpu_irq_src *src,
1231                          unsigned type,
1232                          enum amdgpu_interrupt_state state)
1233 {
1234     u32 tmp;
1235     u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1236             VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1237             VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1238             VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1239             VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1240             VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1241 
1242     switch (state) {
1243     case AMDGPU_IRQ_STATE_DISABLE:
1244         /* system context */
1245         tmp = RREG32(mmVM_CONTEXT0_CNTL);
1246         tmp &= ~bits;
1247         WREG32(mmVM_CONTEXT0_CNTL, tmp);
1248         /* VMs */
1249         tmp = RREG32(mmVM_CONTEXT1_CNTL);
1250         tmp &= ~bits;
1251         WREG32(mmVM_CONTEXT1_CNTL, tmp);
1252         break;
1253     case AMDGPU_IRQ_STATE_ENABLE:
1254         /* system context */
1255         tmp = RREG32(mmVM_CONTEXT0_CNTL);
1256         tmp |= bits;
1257         WREG32(mmVM_CONTEXT0_CNTL, tmp);
1258         /* VMs */
1259         tmp = RREG32(mmVM_CONTEXT1_CNTL);
1260         tmp |= bits;
1261         WREG32(mmVM_CONTEXT1_CNTL, tmp);
1262         break;
1263     default:
1264         break;
1265     }
1266 
1267     return 0;
1268 }
1269 
1270 static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
1271                       struct amdgpu_irq_src *source,
1272                       struct amdgpu_iv_entry *entry)
1273 {
1274     u32 addr, status, mc_client, vmid;
1275 
1276     addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1277     status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1278     mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1279     /* reset addr and status */
1280     WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1281 
1282     if (!addr && !status)
1283         return 0;
1284 
1285     if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1286         gmc_v7_0_set_fault_enable_default(adev, false);
1287 
1288     if (printk_ratelimit()) {
1289         dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1290             entry->src_id, entry->src_data[0]);
1291         dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1292             addr);
1293         dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1294             status);
1295         gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client,
1296                      entry->pasid);
1297     }
1298 
1299     vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1300                  VMID);
1301     if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)
1302         && !atomic_read(&adev->gmc.vm_fault_info_updated)) {
1303         struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info;
1304         u32 protections = REG_GET_FIELD(status,
1305                     VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1306                     PROTECTIONS);
1307 
1308         info->vmid = vmid;
1309         info->mc_id = REG_GET_FIELD(status,
1310                         VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1311                         MEMORY_CLIENT_ID);
1312         info->status = status;
1313         info->page_addr = addr;
1314         info->prot_valid = protections & 0x7 ? true : false;
1315         info->prot_read = protections & 0x8 ? true : false;
1316         info->prot_write = protections & 0x10 ? true : false;
1317         info->prot_exec = protections & 0x20 ? true : false;
1318         mb();
1319         atomic_set(&adev->gmc.vm_fault_info_updated, 1);
1320     }
1321 
1322     return 0;
1323 }
1324 
1325 static int gmc_v7_0_set_clockgating_state(void *handle,
1326                       enum amd_clockgating_state state)
1327 {
1328     bool gate = false;
1329     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1330 
1331     if (state == AMD_CG_STATE_GATE)
1332         gate = true;
1333 
1334     if (!(adev->flags & AMD_IS_APU)) {
1335         gmc_v7_0_enable_mc_mgcg(adev, gate);
1336         gmc_v7_0_enable_mc_ls(adev, gate);
1337     }
1338     gmc_v7_0_enable_bif_mgls(adev, gate);
1339     gmc_v7_0_enable_hdp_mgcg(adev, gate);
1340     gmc_v7_0_enable_hdp_ls(adev, gate);
1341 
1342     return 0;
1343 }
1344 
1345 static int gmc_v7_0_set_powergating_state(void *handle,
1346                       enum amd_powergating_state state)
1347 {
1348     return 0;
1349 }
1350 
1351 static const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1352     .name = "gmc_v7_0",
1353     .early_init = gmc_v7_0_early_init,
1354     .late_init = gmc_v7_0_late_init,
1355     .sw_init = gmc_v7_0_sw_init,
1356     .sw_fini = gmc_v7_0_sw_fini,
1357     .hw_init = gmc_v7_0_hw_init,
1358     .hw_fini = gmc_v7_0_hw_fini,
1359     .suspend = gmc_v7_0_suspend,
1360     .resume = gmc_v7_0_resume,
1361     .is_idle = gmc_v7_0_is_idle,
1362     .wait_for_idle = gmc_v7_0_wait_for_idle,
1363     .soft_reset = gmc_v7_0_soft_reset,
1364     .set_clockgating_state = gmc_v7_0_set_clockgating_state,
1365     .set_powergating_state = gmc_v7_0_set_powergating_state,
1366 };
1367 
1368 static const struct amdgpu_gmc_funcs gmc_v7_0_gmc_funcs = {
1369     .flush_gpu_tlb = gmc_v7_0_flush_gpu_tlb,
1370     .flush_gpu_tlb_pasid = gmc_v7_0_flush_gpu_tlb_pasid,
1371     .emit_flush_gpu_tlb = gmc_v7_0_emit_flush_gpu_tlb,
1372     .emit_pasid_mapping = gmc_v7_0_emit_pasid_mapping,
1373     .set_prt = gmc_v7_0_set_prt,
1374     .get_vm_pde = gmc_v7_0_get_vm_pde,
1375     .get_vm_pte = gmc_v7_0_get_vm_pte,
1376     .get_vbios_fb_size = gmc_v7_0_get_vbios_fb_size,
1377 };
1378 
1379 static const struct amdgpu_irq_src_funcs gmc_v7_0_irq_funcs = {
1380     .set = gmc_v7_0_vm_fault_interrupt_state,
1381     .process = gmc_v7_0_process_interrupt,
1382 };
1383 
1384 static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev)
1385 {
1386     adev->gmc.gmc_funcs = &gmc_v7_0_gmc_funcs;
1387 }
1388 
1389 static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1390 {
1391     adev->gmc.vm_fault.num_types = 1;
1392     adev->gmc.vm_fault.funcs = &gmc_v7_0_irq_funcs;
1393 }
1394 
1395 const struct amdgpu_ip_block_version gmc_v7_0_ip_block =
1396 {
1397     .type = AMD_IP_BLOCK_TYPE_GMC,
1398     .major = 7,
1399     .minor = 0,
1400     .rev = 0,
1401     .funcs = &gmc_v7_0_ip_funcs,
1402 };
1403 
1404 const struct amdgpu_ip_block_version gmc_v7_4_ip_block =
1405 {
1406     .type = AMD_IP_BLOCK_TYPE_GMC,
1407     .major = 7,
1408     .minor = 4,
1409     .rev = 0,
1410     .funcs = &gmc_v7_0_ip_funcs,
1411 };
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