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0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include <linux/firmware.h>
0024 #include <linux/pci.h>
0025 
0026 #include <drm/drm_cache.h>
0027 
0028 #include "amdgpu.h"
0029 #include "amdgpu_atomfirmware.h"
0030 #include "gmc_v10_0.h"
0031 #include "umc_v8_7.h"
0032 
0033 #include "athub/athub_2_0_0_sh_mask.h"
0034 #include "athub/athub_2_0_0_offset.h"
0035 #include "dcn/dcn_2_0_0_offset.h"
0036 #include "dcn/dcn_2_0_0_sh_mask.h"
0037 #include "oss/osssys_5_0_0_offset.h"
0038 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
0039 #include "navi10_enum.h"
0040 
0041 #include "soc15.h"
0042 #include "soc15d.h"
0043 #include "soc15_common.h"
0044 
0045 #include "nbio_v2_3.h"
0046 
0047 #include "gfxhub_v2_0.h"
0048 #include "gfxhub_v2_1.h"
0049 #include "mmhub_v2_0.h"
0050 #include "mmhub_v2_3.h"
0051 #include "athub_v2_0.h"
0052 #include "athub_v2_1.h"
0053 
0054 #include "amdgpu_reset.h"
0055 
0056 #if 0
0057 static const struct soc15_reg_golden golden_settings_navi10_hdp[] =
0058 {
0059     /* TODO add golden setting for hdp */
0060 };
0061 #endif
0062 
0063 static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev,
0064                      struct amdgpu_irq_src *src,
0065                      unsigned type,
0066                      enum amdgpu_interrupt_state state)
0067 {
0068     return 0;
0069 }
0070 
0071 static int
0072 gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
0073                    struct amdgpu_irq_src *src, unsigned type,
0074                    enum amdgpu_interrupt_state state)
0075 {
0076     switch (state) {
0077     case AMDGPU_IRQ_STATE_DISABLE:
0078         /* MM HUB */
0079         amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false);
0080         /* GFX HUB */
0081         amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false);
0082         break;
0083     case AMDGPU_IRQ_STATE_ENABLE:
0084         /* MM HUB */
0085         amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true);
0086         /* GFX HUB */
0087         amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true);
0088         break;
0089     default:
0090         break;
0091     }
0092 
0093     return 0;
0094 }
0095 
0096 static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
0097                        struct amdgpu_irq_src *source,
0098                        struct amdgpu_iv_entry *entry)
0099 {
0100     bool retry_fault = !!(entry->src_data[1] & 0x80);
0101     bool write_fault = !!(entry->src_data[1] & 0x20);
0102     struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
0103     struct amdgpu_task_info task_info;
0104     uint32_t status = 0;
0105     u64 addr;
0106 
0107     addr = (u64)entry->src_data[0] << 12;
0108     addr |= ((u64)entry->src_data[1] & 0xf) << 44;
0109 
0110     if (retry_fault) {
0111         /* Returning 1 here also prevents sending the IV to the KFD */
0112 
0113         /* Process it onyl if it's the first fault for this address */
0114         if (entry->ih != &adev->irq.ih_soft &&
0115             amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid,
0116                          entry->timestamp))
0117             return 1;
0118 
0119         /* Delegate it to a different ring if the hardware hasn't
0120          * already done it.
0121          */
0122         if (entry->ih == &adev->irq.ih) {
0123             amdgpu_irq_delegate(adev, entry, 8);
0124             return 1;
0125         }
0126 
0127         /* Try to handle the recoverable page faults by filling page
0128          * tables
0129          */
0130         if (amdgpu_vm_handle_fault(adev, entry->pasid, addr, write_fault))
0131             return 1;
0132     }
0133 
0134     if (!amdgpu_sriov_vf(adev)) {
0135         /*
0136          * Issue a dummy read to wait for the status register to
0137          * be updated to avoid reading an incorrect value due to
0138          * the new fast GRBM interface.
0139          */
0140         if ((entry->vmid_src == AMDGPU_GFXHUB_0) &&
0141             (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)))
0142             RREG32(hub->vm_l2_pro_fault_status);
0143 
0144         status = RREG32(hub->vm_l2_pro_fault_status);
0145         WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
0146     }
0147 
0148     if (!printk_ratelimit())
0149         return 0;
0150 
0151     memset(&task_info, 0, sizeof(struct amdgpu_task_info));
0152     amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
0153 
0154     dev_err(adev->dev,
0155         "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, "
0156         "for process %s pid %d thread %s pid %d)\n",
0157         entry->vmid_src ? "mmhub" : "gfxhub",
0158         entry->src_id, entry->ring_id, entry->vmid,
0159         entry->pasid, task_info.process_name, task_info.tgid,
0160         task_info.task_name, task_info.pid);
0161     dev_err(adev->dev, "  in page starting at address 0x%016llx from client 0x%x (%s)\n",
0162         addr, entry->client_id,
0163         soc15_ih_clientid_name[entry->client_id]);
0164 
0165     if (!amdgpu_sriov_vf(adev))
0166         hub->vmhub_funcs->print_l2_protection_fault_status(adev,
0167                                    status);
0168 
0169     return 0;
0170 }
0171 
0172 static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = {
0173     .set = gmc_v10_0_vm_fault_interrupt_state,
0174     .process = gmc_v10_0_process_interrupt,
0175 };
0176 
0177 static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = {
0178     .set = gmc_v10_0_ecc_interrupt_state,
0179     .process = amdgpu_umc_process_ecc_irq,
0180 };
0181 
0182 static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
0183 {
0184     adev->gmc.vm_fault.num_types = 1;
0185     adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;
0186 
0187     if (!amdgpu_sriov_vf(adev)) {
0188         adev->gmc.ecc_irq.num_types = 1;
0189         adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs;
0190     }
0191 }
0192 
0193 /**
0194  * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore
0195  *
0196  * @adev: amdgpu_device pointer
0197  * @vmhub: vmhub type
0198  *
0199  */
0200 static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
0201                        uint32_t vmhub)
0202 {
0203     return ((vmhub == AMDGPU_MMHUB_0 ||
0204          vmhub == AMDGPU_MMHUB_1) &&
0205         (!amdgpu_sriov_vf(adev)));
0206 }
0207 
0208 static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info(
0209                     struct amdgpu_device *adev,
0210                     uint8_t vmid, uint16_t *p_pasid)
0211 {
0212     uint32_t value;
0213 
0214     value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
0215              + vmid);
0216     *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
0217 
0218     return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
0219 }
0220 
0221 /*
0222  * GART
0223  * VMID 0 is the physical GPU addresses as used by the kernel.
0224  * VMIDs 1-15 are used for userspace clients and are handled
0225  * by the amdgpu vm/hsa code.
0226  */
0227 
0228 static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
0229                    unsigned int vmhub, uint32_t flush_type)
0230 {
0231     bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub);
0232     struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
0233     u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
0234     u32 tmp;
0235     /* Use register 17 for GART */
0236     const unsigned eng = 17;
0237     unsigned int i;
0238     unsigned char hub_ip = 0;
0239 
0240     hub_ip = (vmhub == AMDGPU_GFXHUB_0) ?
0241            GC_HWIP : MMHUB_HWIP;
0242 
0243     spin_lock(&adev->gmc.invalidate_lock);
0244     /*
0245      * It may lose gpuvm invalidate acknowldege state across power-gating
0246      * off cycle, add semaphore acquire before invalidation and semaphore
0247      * release after invalidation to avoid entering power gated state
0248      * to WA the Issue
0249      */
0250 
0251     /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
0252     if (use_semaphore) {
0253         for (i = 0; i < adev->usec_timeout; i++) {
0254             /* a read return value of 1 means semaphore acuqire */
0255             tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
0256                      hub->eng_distance * eng, hub_ip);
0257 
0258             if (tmp & 0x1)
0259                 break;
0260             udelay(1);
0261         }
0262 
0263         if (i >= adev->usec_timeout)
0264             DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
0265     }
0266 
0267     WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
0268               hub->eng_distance * eng,
0269               inv_req, hub_ip);
0270 
0271     /*
0272      * Issue a dummy read to wait for the ACK register to be cleared
0273      * to avoid a false ACK due to the new fast GRBM interface.
0274      */
0275     if ((vmhub == AMDGPU_GFXHUB_0) &&
0276         (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0)))
0277         RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
0278                   hub->eng_distance * eng, hub_ip);
0279 
0280     /* Wait for ACK with a delay.*/
0281     for (i = 0; i < adev->usec_timeout; i++) {
0282         tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack +
0283                   hub->eng_distance * eng, hub_ip);
0284 
0285         tmp &= 1 << vmid;
0286         if (tmp)
0287             break;
0288 
0289         udelay(1);
0290     }
0291 
0292     /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
0293     if (use_semaphore)
0294         /*
0295          * add semaphore release after invalidation,
0296          * write with 0 means semaphore release
0297          */
0298         WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
0299                   hub->eng_distance * eng, 0, hub_ip);
0300 
0301     spin_unlock(&adev->gmc.invalidate_lock);
0302 
0303     if (i < adev->usec_timeout)
0304         return;
0305 
0306     DRM_ERROR("Timeout waiting for VM flush hub: %d!\n", vmhub);
0307 }
0308 
0309 /**
0310  * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback
0311  *
0312  * @adev: amdgpu_device pointer
0313  * @vmid: vm instance to flush
0314  * @vmhub: vmhub type
0315  * @flush_type: the flush type
0316  *
0317  * Flush the TLB for the requested page table.
0318  */
0319 static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
0320                     uint32_t vmhub, uint32_t flush_type)
0321 {
0322     struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
0323     struct dma_fence *fence;
0324     struct amdgpu_job *job;
0325 
0326     int r;
0327 
0328     /* flush hdp cache */
0329     adev->hdp.funcs->flush_hdp(adev, NULL);
0330 
0331     /* For SRIOV run time, driver shouldn't access the register through MMIO
0332      * Directly use kiq to do the vm invalidation instead
0333      */
0334     if (adev->gfx.kiq.ring.sched.ready && !adev->enable_mes &&
0335         (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
0336         down_read_trylock(&adev->reset_domain->sem)) {
0337         struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
0338         const unsigned eng = 17;
0339         u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
0340         u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
0341         u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
0342 
0343         amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
0344                 1 << vmid);
0345 
0346         up_read(&adev->reset_domain->sem);
0347         return;
0348     }
0349 
0350     mutex_lock(&adev->mman.gtt_window_lock);
0351 
0352     if (vmhub == AMDGPU_MMHUB_0) {
0353         gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
0354         mutex_unlock(&adev->mman.gtt_window_lock);
0355         return;
0356     }
0357 
0358     BUG_ON(vmhub != AMDGPU_GFXHUB_0);
0359 
0360     if (!adev->mman.buffer_funcs_enabled ||
0361         !adev->ib_pool_ready ||
0362         amdgpu_in_reset(adev) ||
0363         ring->sched.ready == false) {
0364         gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
0365         mutex_unlock(&adev->mman.gtt_window_lock);
0366         return;
0367     }
0368 
0369     /* The SDMA on Navi has a bug which can theoretically result in memory
0370      * corruption if an invalidation happens at the same time as an VA
0371      * translation. Avoid this by doing the invalidation from the SDMA
0372      * itself.
0373      */
0374     r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
0375                      &job);
0376     if (r)
0377         goto error_alloc;
0378 
0379     job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
0380     job->vm_needs_flush = true;
0381     job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
0382     amdgpu_ring_pad_ib(ring, &job->ibs[0]);
0383     r = amdgpu_job_submit(job, &adev->mman.entity,
0384                   AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
0385     if (r)
0386         goto error_submit;
0387 
0388     mutex_unlock(&adev->mman.gtt_window_lock);
0389 
0390     dma_fence_wait(fence, false);
0391     dma_fence_put(fence);
0392 
0393     return;
0394 
0395 error_submit:
0396     amdgpu_job_free(job);
0397 
0398 error_alloc:
0399     mutex_unlock(&adev->mman.gtt_window_lock);
0400     DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
0401 }
0402 
0403 /**
0404  * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid
0405  *
0406  * @adev: amdgpu_device pointer
0407  * @pasid: pasid to be flush
0408  * @flush_type: the flush type
0409  * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB()
0410  *
0411  * Flush the TLB for the requested pasid.
0412  */
0413 static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
0414                     uint16_t pasid, uint32_t flush_type,
0415                     bool all_hub)
0416 {
0417     int vmid, i;
0418     signed long r;
0419     uint32_t seq;
0420     uint16_t queried_pasid;
0421     bool ret;
0422     u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : adev->usec_timeout;
0423     struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
0424     struct amdgpu_kiq *kiq = &adev->gfx.kiq;
0425 
0426     if (amdgpu_emu_mode == 0 && ring->sched.ready) {
0427         spin_lock(&adev->gfx.kiq.ring_lock);
0428         /* 2 dwords flush + 8 dwords fence */
0429         amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8);
0430         kiq->pmf->kiq_invalidate_tlbs(ring,
0431                     pasid, flush_type, all_hub);
0432         r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
0433         if (r) {
0434             amdgpu_ring_undo(ring);
0435             spin_unlock(&adev->gfx.kiq.ring_lock);
0436             return -ETIME;
0437         }
0438 
0439         amdgpu_ring_commit(ring);
0440         spin_unlock(&adev->gfx.kiq.ring_lock);
0441         r = amdgpu_fence_wait_polling(ring, seq, usec_timeout);
0442         if (r < 1) {
0443             dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);
0444             return -ETIME;
0445         }
0446 
0447         return 0;
0448     }
0449 
0450     for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
0451 
0452         ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
0453                 &queried_pasid);
0454         if (ret && queried_pasid == pasid) {
0455             if (all_hub) {
0456                 for (i = 0; i < adev->num_vmhubs; i++)
0457                     gmc_v10_0_flush_gpu_tlb(adev, vmid,
0458                             i, flush_type);
0459             } else {
0460                 gmc_v10_0_flush_gpu_tlb(adev, vmid,
0461                         AMDGPU_GFXHUB_0, flush_type);
0462             }
0463             if (!adev->enable_mes)
0464                 break;
0465         }
0466     }
0467 
0468     return 0;
0469 }
0470 
0471 static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
0472                          unsigned vmid, uint64_t pd_addr)
0473 {
0474     bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
0475     struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
0476     uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
0477     unsigned eng = ring->vm_inv_eng;
0478 
0479     /*
0480      * It may lose gpuvm invalidate acknowldege state across power-gating
0481      * off cycle, add semaphore acquire before invalidation and semaphore
0482      * release after invalidation to avoid entering power gated state
0483      * to WA the Issue
0484      */
0485 
0486     /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
0487     if (use_semaphore)
0488         /* a read return value of 1 means semaphore acuqire */
0489         amdgpu_ring_emit_reg_wait(ring,
0490                       hub->vm_inv_eng0_sem +
0491                       hub->eng_distance * eng, 0x1, 0x1);
0492 
0493     amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
0494                   (hub->ctx_addr_distance * vmid),
0495                   lower_32_bits(pd_addr));
0496 
0497     amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
0498                   (hub->ctx_addr_distance * vmid),
0499                   upper_32_bits(pd_addr));
0500 
0501     amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
0502                         hub->eng_distance * eng,
0503                         hub->vm_inv_eng0_ack +
0504                         hub->eng_distance * eng,
0505                         req, 1 << vmid);
0506 
0507     /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
0508     if (use_semaphore)
0509         /*
0510          * add semaphore release after invalidation,
0511          * write with 0 means semaphore release
0512          */
0513         amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
0514                       hub->eng_distance * eng, 0);
0515 
0516     return pd_addr;
0517 }
0518 
0519 static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
0520                      unsigned pasid)
0521 {
0522     struct amdgpu_device *adev = ring->adev;
0523     uint32_t reg;
0524 
0525     /* MES fw manages IH_VMID_x_LUT updating */
0526     if (ring->is_mes_queue)
0527         return;
0528 
0529     if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
0530         reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
0531     else
0532         reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
0533 
0534     amdgpu_ring_emit_wreg(ring, reg, pasid);
0535 }
0536 
0537 /*
0538  * PTE format on NAVI 10:
0539  * 63:59 reserved
0540  * 58 reserved and for sienna_cichlid is used for MALL noalloc
0541  * 57 reserved
0542  * 56 F
0543  * 55 L
0544  * 54 reserved
0545  * 53:52 SW
0546  * 51 T
0547  * 50:48 mtype
0548  * 47:12 4k physical page base address
0549  * 11:7 fragment
0550  * 6 write
0551  * 5 read
0552  * 4 exe
0553  * 3 Z
0554  * 2 snooped
0555  * 1 system
0556  * 0 valid
0557  *
0558  * PDE format on NAVI 10:
0559  * 63:59 block fragment size
0560  * 58:55 reserved
0561  * 54 P
0562  * 53:48 reserved
0563  * 47:6 physical base address of PD or PTE
0564  * 5:3 reserved
0565  * 2 C
0566  * 1 system
0567  * 0 valid
0568  */
0569 
0570 static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
0571 {
0572     switch (flags) {
0573     case AMDGPU_VM_MTYPE_DEFAULT:
0574         return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
0575     case AMDGPU_VM_MTYPE_NC:
0576         return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
0577     case AMDGPU_VM_MTYPE_WC:
0578         return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);
0579     case AMDGPU_VM_MTYPE_CC:
0580         return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);
0581     case AMDGPU_VM_MTYPE_UC:
0582         return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
0583     default:
0584         return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
0585     }
0586 }
0587 
0588 static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,
0589                  uint64_t *addr, uint64_t *flags)
0590 {
0591     if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
0592         *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
0593     BUG_ON(*addr & 0xFFFF00000000003FULL);
0594 
0595     if (!adev->gmc.translate_further)
0596         return;
0597 
0598     if (level == AMDGPU_VM_PDB1) {
0599         /* Set the block fragment size */
0600         if (!(*flags & AMDGPU_PDE_PTE))
0601             *flags |= AMDGPU_PDE_BFS(0x9);
0602 
0603     } else if (level == AMDGPU_VM_PDB0) {
0604         if (*flags & AMDGPU_PDE_PTE)
0605             *flags &= ~AMDGPU_PDE_PTE;
0606         else
0607             *flags |= AMDGPU_PTE_TF;
0608     }
0609 }
0610 
0611 static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
0612                  struct amdgpu_bo_va_mapping *mapping,
0613                  uint64_t *flags)
0614 {
0615     *flags &= ~AMDGPU_PTE_EXECUTABLE;
0616     *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
0617 
0618     *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
0619     *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
0620 
0621     *flags &= ~AMDGPU_PTE_NOALLOC;
0622     *flags |= (mapping->flags & AMDGPU_PTE_NOALLOC);
0623 
0624     if (mapping->flags & AMDGPU_PTE_PRT) {
0625         *flags |= AMDGPU_PTE_PRT;
0626         *flags |= AMDGPU_PTE_SNOOPED;
0627         *flags |= AMDGPU_PTE_LOG;
0628         *flags |= AMDGPU_PTE_SYSTEM;
0629         *flags &= ~AMDGPU_PTE_VALID;
0630     }
0631 }
0632 
0633 static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
0634 {
0635     u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
0636     unsigned size;
0637 
0638     if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
0639         size = AMDGPU_VBIOS_VGA_ALLOCATION;
0640     } else {
0641         u32 viewport;
0642         u32 pitch;
0643 
0644         viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
0645         pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH);
0646         size = (REG_GET_FIELD(viewport,
0647                     HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
0648                 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
0649                 4);
0650     }
0651 
0652     return size;
0653 }
0654 
0655 static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
0656     .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
0657     .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid,
0658     .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
0659     .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
0660     .map_mtype = gmc_v10_0_map_mtype,
0661     .get_vm_pde = gmc_v10_0_get_vm_pde,
0662     .get_vm_pte = gmc_v10_0_get_vm_pte,
0663     .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size,
0664 };
0665 
0666 static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
0667 {
0668     if (adev->gmc.gmc_funcs == NULL)
0669         adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs;
0670 }
0671 
0672 static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
0673 {
0674     switch (adev->ip_versions[UMC_HWIP][0]) {
0675     case IP_VERSION(8, 7, 0):
0676         adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;
0677         adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;
0678         adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM;
0679         adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA;
0680         adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0];
0681         adev->umc.ras = &umc_v8_7_ras;
0682         break;
0683     default:
0684         break;
0685     }
0686     if (adev->umc.ras) {
0687         amdgpu_ras_register_ras_block(adev, &adev->umc.ras->ras_block);
0688 
0689         strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc");
0690         adev->umc.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC;
0691         adev->umc.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
0692         adev->umc.ras_if = &adev->umc.ras->ras_block.ras_comm;
0693 
0694         /* If don't define special ras_late_init function, use default ras_late_init */
0695         if (!adev->umc.ras->ras_block.ras_late_init)
0696                 adev->umc.ras->ras_block.ras_late_init = amdgpu_umc_ras_late_init;
0697 
0698         /* If not defined special ras_cb function, use default ras_cb */
0699         if (!adev->umc.ras->ras_block.ras_cb)
0700             adev->umc.ras->ras_block.ras_cb = amdgpu_umc_process_ras_data_cb;
0701     }
0702 }
0703 
0704 
0705 static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
0706 {
0707     switch (adev->ip_versions[MMHUB_HWIP][0]) {
0708     case IP_VERSION(2, 3, 0):
0709     case IP_VERSION(2, 4, 0):
0710     case IP_VERSION(2, 4, 1):
0711         adev->mmhub.funcs = &mmhub_v2_3_funcs;
0712         break;
0713     default:
0714         adev->mmhub.funcs = &mmhub_v2_0_funcs;
0715         break;
0716     }
0717 }
0718 
0719 static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)
0720 {
0721     switch (adev->ip_versions[GC_HWIP][0]) {
0722     case IP_VERSION(10, 3, 0):
0723     case IP_VERSION(10, 3, 2):
0724     case IP_VERSION(10, 3, 1):
0725     case IP_VERSION(10, 3, 4):
0726     case IP_VERSION(10, 3, 5):
0727     case IP_VERSION(10, 3, 6):
0728     case IP_VERSION(10, 3, 3):
0729     case IP_VERSION(10, 3, 7):
0730         adev->gfxhub.funcs = &gfxhub_v2_1_funcs;
0731         break;
0732     default:
0733         adev->gfxhub.funcs = &gfxhub_v2_0_funcs;
0734         break;
0735     }
0736 }
0737 
0738 
0739 static int gmc_v10_0_early_init(void *handle)
0740 {
0741     int r;
0742     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0743 
0744     gmc_v10_0_set_mmhub_funcs(adev);
0745     gmc_v10_0_set_gfxhub_funcs(adev);
0746     gmc_v10_0_set_gmc_funcs(adev);
0747     gmc_v10_0_set_irq_funcs(adev);
0748     gmc_v10_0_set_umc_funcs(adev);
0749 
0750     adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
0751     adev->gmc.shared_aperture_end =
0752         adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
0753     adev->gmc.private_aperture_start = 0x1000000000000000ULL;
0754     adev->gmc.private_aperture_end =
0755         adev->gmc.private_aperture_start + (4ULL << 30) - 1;
0756 
0757     r = amdgpu_gmc_ras_early_init(adev);
0758     if (r)
0759         return r;
0760 
0761     return 0;
0762 }
0763 
0764 static int gmc_v10_0_late_init(void *handle)
0765 {
0766     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0767     int r;
0768 
0769     r = amdgpu_gmc_allocate_vm_inv_eng(adev);
0770     if (r)
0771         return r;
0772 
0773     r = amdgpu_gmc_ras_late_init(adev);
0774     if (r)
0775         return r;
0776 
0777     return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
0778 }
0779 
0780 static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
0781                     struct amdgpu_gmc *mc)
0782 {
0783     u64 base = 0;
0784 
0785     base = adev->gfxhub.funcs->get_fb_location(adev);
0786 
0787     /* add the xgmi offset of the physical node */
0788     base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
0789 
0790     amdgpu_gmc_vram_location(adev, &adev->gmc, base);
0791     amdgpu_gmc_gart_location(adev, mc);
0792     amdgpu_gmc_agp_location(adev, mc);
0793 
0794     /* base offset of vram pages */
0795     adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);
0796 
0797     /* add the xgmi offset of the physical node */
0798     adev->vm_manager.vram_base_offset +=
0799         adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
0800 }
0801 
0802 /**
0803  * gmc_v10_0_mc_init - initialize the memory controller driver params
0804  *
0805  * @adev: amdgpu_device pointer
0806  *
0807  * Look up the amount of vram, vram width, and decide how to place
0808  * vram and gart within the GPU's physical address space.
0809  * Returns 0 for success.
0810  */
0811 static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
0812 {
0813     int r;
0814 
0815     /* size in MB on si */
0816     adev->gmc.mc_vram_size =
0817         adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
0818     adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
0819 
0820     if (!(adev->flags & AMD_IS_APU)) {
0821         r = amdgpu_device_resize_fb_bar(adev);
0822         if (r)
0823             return r;
0824     }
0825     adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
0826     adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
0827 
0828 #ifdef CONFIG_X86_64
0829     if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) {
0830         adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev);
0831         adev->gmc.aper_size = adev->gmc.real_vram_size;
0832     }
0833 #endif
0834 
0835     /* In case the PCI BAR is larger than the actual amount of vram */
0836     adev->gmc.visible_vram_size = adev->gmc.aper_size;
0837     if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
0838         adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
0839 
0840     /* set the gart size */
0841     if (amdgpu_gart_size == -1) {
0842         switch (adev->ip_versions[GC_HWIP][0]) {
0843         default:
0844             adev->gmc.gart_size = 512ULL << 20;
0845             break;
0846         case IP_VERSION(10, 3, 1):   /* DCE SG support */
0847         case IP_VERSION(10, 3, 3):   /* DCE SG support */
0848         case IP_VERSION(10, 3, 6):   /* DCE SG support */
0849         case IP_VERSION(10, 3, 7):   /* DCE SG support */
0850             adev->gmc.gart_size = 1024ULL << 20;
0851             break;
0852         }
0853     } else {
0854         adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
0855     }
0856 
0857     gmc_v10_0_vram_gtt_location(adev, &adev->gmc);
0858 
0859     return 0;
0860 }
0861 
0862 static int gmc_v10_0_gart_init(struct amdgpu_device *adev)
0863 {
0864     int r;
0865 
0866     if (adev->gart.bo) {
0867         WARN(1, "NAVI10 PCIE GART already initialized\n");
0868         return 0;
0869     }
0870 
0871     /* Initialize common gart structure */
0872     r = amdgpu_gart_init(adev);
0873     if (r)
0874         return r;
0875 
0876     adev->gart.table_size = adev->gart.num_gpu_pages * 8;
0877     adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |
0878                  AMDGPU_PTE_EXECUTABLE;
0879 
0880     return amdgpu_gart_table_vram_alloc(adev);
0881 }
0882 
0883 static int gmc_v10_0_sw_init(void *handle)
0884 {
0885     int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
0886     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0887 
0888     adev->gfxhub.funcs->init(adev);
0889 
0890     adev->mmhub.funcs->init(adev);
0891 
0892     spin_lock_init(&adev->gmc.invalidate_lock);
0893 
0894     if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) {
0895         adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;
0896         adev->gmc.vram_width = 64;
0897     } else if (amdgpu_emu_mode == 1) {
0898         adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6;
0899         adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
0900     } else {
0901         r = amdgpu_atomfirmware_get_vram_info(adev,
0902                 &vram_width, &vram_type, &vram_vendor);
0903         adev->gmc.vram_width = vram_width;
0904 
0905         adev->gmc.vram_type = vram_type;
0906         adev->gmc.vram_vendor = vram_vendor;
0907     }
0908 
0909     switch (adev->ip_versions[GC_HWIP][0]) {
0910     case IP_VERSION(10, 3, 0):
0911         adev->gmc.mall_size = 128 * 1024 * 1024;
0912         break;
0913     case IP_VERSION(10, 3, 2):
0914         adev->gmc.mall_size = 96 * 1024 * 1024;
0915         break;
0916     case IP_VERSION(10, 3, 4):
0917         adev->gmc.mall_size = 32 * 1024 * 1024;
0918         break;
0919     case IP_VERSION(10, 3, 5):
0920         adev->gmc.mall_size = 16 * 1024 * 1024;
0921         break;
0922     default:
0923         adev->gmc.mall_size = 0;
0924         break;
0925     }
0926 
0927     switch (adev->ip_versions[GC_HWIP][0]) {
0928     case IP_VERSION(10, 1, 10):
0929     case IP_VERSION(10, 1, 1):
0930     case IP_VERSION(10, 1, 2):
0931     case IP_VERSION(10, 1, 3):
0932     case IP_VERSION(10, 1, 4):
0933     case IP_VERSION(10, 3, 0):
0934     case IP_VERSION(10, 3, 2):
0935     case IP_VERSION(10, 3, 1):
0936     case IP_VERSION(10, 3, 4):
0937     case IP_VERSION(10, 3, 5):
0938     case IP_VERSION(10, 3, 6):
0939     case IP_VERSION(10, 3, 3):
0940     case IP_VERSION(10, 3, 7):
0941         adev->num_vmhubs = 2;
0942         /*
0943          * To fulfill 4-level page support,
0944          * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12,
0945          * block size 512 (9bit)
0946          */
0947         amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
0948         break;
0949     default:
0950         break;
0951     }
0952 
0953     /* This interrupt is VMC page fault.*/
0954     r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC,
0955                   VMC_1_0__SRCID__VM_FAULT,
0956                   &adev->gmc.vm_fault);
0957 
0958     if (r)
0959         return r;
0960 
0961     r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2,
0962                   UTCL2_1_0__SRCID__FAULT,
0963                   &adev->gmc.vm_fault);
0964     if (r)
0965         return r;
0966 
0967     if (!amdgpu_sriov_vf(adev)) {
0968         /* interrupt sent to DF. */
0969         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
0970                       &adev->gmc.ecc_irq);
0971         if (r)
0972             return r;
0973     }
0974 
0975     /*
0976      * Set the internal MC address mask This is the max address of the GPU's
0977      * internal address space.
0978      */
0979     adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
0980 
0981     r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
0982     if (r) {
0983         printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
0984         return r;
0985     }
0986 
0987     adev->need_swiotlb = drm_need_swiotlb(44);
0988 
0989     r = gmc_v10_0_mc_init(adev);
0990     if (r)
0991         return r;
0992 
0993     amdgpu_gmc_get_vbios_allocations(adev);
0994 
0995     /* Memory manager */
0996     r = amdgpu_bo_init(adev);
0997     if (r)
0998         return r;
0999 
1000     r = gmc_v10_0_gart_init(adev);
1001     if (r)
1002         return r;
1003 
1004     /*
1005      * number of VMs
1006      * VMID 0 is reserved for System
1007      * amdgpu graphics/compute will use VMIDs 1-7
1008      * amdkfd will use VMIDs 8-15
1009      */
1010     adev->vm_manager.first_kfd_vmid = 8;
1011 
1012     amdgpu_vm_manager_init(adev);
1013 
1014     return 0;
1015 }
1016 
1017 /**
1018  * gmc_v10_0_gart_fini - vm fini callback
1019  *
1020  * @adev: amdgpu_device pointer
1021  *
1022  * Tears down the driver GART/VM setup (CIK).
1023  */
1024 static void gmc_v10_0_gart_fini(struct amdgpu_device *adev)
1025 {
1026     amdgpu_gart_table_vram_free(adev);
1027 }
1028 
1029 static int gmc_v10_0_sw_fini(void *handle)
1030 {
1031     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1032 
1033     amdgpu_vm_manager_fini(adev);
1034     gmc_v10_0_gart_fini(adev);
1035     amdgpu_gem_force_release(adev);
1036     amdgpu_bo_fini(adev);
1037 
1038     return 0;
1039 }
1040 
1041 static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
1042 {
1043 }
1044 
1045 /**
1046  * gmc_v10_0_gart_enable - gart enable
1047  *
1048  * @adev: amdgpu_device pointer
1049  */
1050 static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
1051 {
1052     int r;
1053     bool value;
1054 
1055     if (adev->gart.bo == NULL) {
1056         dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1057         return -EINVAL;
1058     }
1059 
1060     amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
1061     r = adev->gfxhub.funcs->gart_enable(adev);
1062     if (r)
1063         return r;
1064 
1065     r = adev->mmhub.funcs->gart_enable(adev);
1066     if (r)
1067         return r;
1068 
1069     adev->hdp.funcs->init_registers(adev);
1070 
1071     /* Flush HDP after it is initialized */
1072     adev->hdp.funcs->flush_hdp(adev, NULL);
1073 
1074     value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
1075         false : true;
1076 
1077     adev->gfxhub.funcs->set_fault_enable_default(adev, value);
1078     adev->mmhub.funcs->set_fault_enable_default(adev, value);
1079     gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
1080     gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
1081 
1082     DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1083          (unsigned)(adev->gmc.gart_size >> 20),
1084          (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1085 
1086     return 0;
1087 }
1088 
1089 static int gmc_v10_0_hw_init(void *handle)
1090 {
1091     int r;
1092     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1093 
1094     /* The sequence of these two function calls matters.*/
1095     gmc_v10_0_init_golden_registers(adev);
1096 
1097     /*
1098      * harvestable groups in gc_utcl2 need to be programmed before any GFX block
1099      * register setup within GMC, or else system hang when harvesting SA.
1100      */
1101     if (adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest)
1102         adev->gfxhub.funcs->utcl2_harvest(adev);
1103 
1104     r = gmc_v10_0_gart_enable(adev);
1105     if (r)
1106         return r;
1107 
1108     if (amdgpu_emu_mode == 1) {
1109         r = amdgpu_gmc_vram_checking(adev);
1110         if (r)
1111             return r;
1112     }
1113 
1114     if (adev->umc.funcs && adev->umc.funcs->init_registers)
1115         adev->umc.funcs->init_registers(adev);
1116 
1117     return 0;
1118 }
1119 
1120 /**
1121  * gmc_v10_0_gart_disable - gart disable
1122  *
1123  * @adev: amdgpu_device pointer
1124  *
1125  * This disables all VM page table.
1126  */
1127 static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)
1128 {
1129     adev->gfxhub.funcs->gart_disable(adev);
1130     adev->mmhub.funcs->gart_disable(adev);
1131 }
1132 
1133 static int gmc_v10_0_hw_fini(void *handle)
1134 {
1135     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1136 
1137     gmc_v10_0_gart_disable(adev);
1138 
1139     if (amdgpu_sriov_vf(adev)) {
1140         /* full access mode, so don't touch any GMC register */
1141         DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1142         return 0;
1143     }
1144 
1145     amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
1146     amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1147 
1148     return 0;
1149 }
1150 
1151 static int gmc_v10_0_suspend(void *handle)
1152 {
1153     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1154 
1155     gmc_v10_0_hw_fini(adev);
1156 
1157     return 0;
1158 }
1159 
1160 static int gmc_v10_0_resume(void *handle)
1161 {
1162     int r;
1163     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1164 
1165     r = gmc_v10_0_hw_init(adev);
1166     if (r)
1167         return r;
1168 
1169     amdgpu_vmid_reset_all(adev);
1170 
1171     return 0;
1172 }
1173 
1174 static bool gmc_v10_0_is_idle(void *handle)
1175 {
1176     /* MC is always ready in GMC v10.*/
1177     return true;
1178 }
1179 
1180 static int gmc_v10_0_wait_for_idle(void *handle)
1181 {
1182     /* There is no need to wait for MC idle in GMC v10.*/
1183     return 0;
1184 }
1185 
1186 static int gmc_v10_0_soft_reset(void *handle)
1187 {
1188     return 0;
1189 }
1190 
1191 static int gmc_v10_0_set_clockgating_state(void *handle,
1192                        enum amd_clockgating_state state)
1193 {
1194     int r;
1195     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1196 
1197     /*
1198      * The issue mmhub can't disconnect from DF with MMHUB clock gating being disabled
1199      * is a new problem observed at DF 3.0.3, however with the same suspend sequence not
1200      * seen any issue on the DF 3.0.2 series platform.
1201      */
1202     if (adev->in_s0ix && adev->ip_versions[DF_HWIP][0] > IP_VERSION(3, 0, 2)) {
1203         dev_dbg(adev->dev, "keep mmhub clock gating being enabled for s0ix\n");
1204         return 0;
1205     }
1206 
1207     r = adev->mmhub.funcs->set_clockgating(adev, state);
1208     if (r)
1209         return r;
1210 
1211     if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0))
1212         return athub_v2_1_set_clockgating(adev, state);
1213     else
1214         return athub_v2_0_set_clockgating(adev, state);
1215 }
1216 
1217 static void gmc_v10_0_get_clockgating_state(void *handle, u64 *flags)
1218 {
1219     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1220 
1221     if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 3) ||
1222         adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 4))
1223         return;
1224 
1225     adev->mmhub.funcs->get_clockgating(adev, flags);
1226 
1227     if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0))
1228         athub_v2_1_get_clockgating(adev, flags);
1229     else
1230         athub_v2_0_get_clockgating(adev, flags);
1231 }
1232 
1233 static int gmc_v10_0_set_powergating_state(void *handle,
1234                        enum amd_powergating_state state)
1235 {
1236     return 0;
1237 }
1238 
1239 const struct amd_ip_funcs gmc_v10_0_ip_funcs = {
1240     .name = "gmc_v10_0",
1241     .early_init = gmc_v10_0_early_init,
1242     .late_init = gmc_v10_0_late_init,
1243     .sw_init = gmc_v10_0_sw_init,
1244     .sw_fini = gmc_v10_0_sw_fini,
1245     .hw_init = gmc_v10_0_hw_init,
1246     .hw_fini = gmc_v10_0_hw_fini,
1247     .suspend = gmc_v10_0_suspend,
1248     .resume = gmc_v10_0_resume,
1249     .is_idle = gmc_v10_0_is_idle,
1250     .wait_for_idle = gmc_v10_0_wait_for_idle,
1251     .soft_reset = gmc_v10_0_soft_reset,
1252     .set_clockgating_state = gmc_v10_0_set_clockgating_state,
1253     .set_powergating_state = gmc_v10_0_set_powergating_state,
1254     .get_clockgating_state = gmc_v10_0_get_clockgating_state,
1255 };
1256 
1257 const struct amdgpu_ip_block_version gmc_v10_0_ip_block =
1258 {
1259     .type = AMD_IP_BLOCK_TYPE_GMC,
1260     .major = 10,
1261     .minor = 0,
1262     .rev = 0,
1263     .funcs = &gmc_v10_0_ip_funcs,
1264 };
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