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OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #include "amdgpu.h"
0025 #include "gfxhub_v3_0.h"
0026 
0027 #include "gc/gc_11_0_0_offset.h"
0028 #include "gc/gc_11_0_0_sh_mask.h"
0029 #include "gc/gc_11_0_0_default.h"
0030 #include "navi10_enum.h"
0031 #include "soc15_common.h"
0032 
0033 static const char *gfxhub_client_ids[] = {
0034     "CB/DB",
0035     "Reserved",
0036     "GE1",
0037     "GE2",
0038     "CPF",
0039     "CPC",
0040     "CPG",
0041     "RLC",
0042     "TCP",
0043     "SQC (inst)",
0044     "SQC (data)",
0045     "SQG",
0046     "Reserved",
0047     "SDMA0",
0048     "SDMA1",
0049     "GCR",
0050     "SDMA2",
0051     "SDMA3",
0052 };
0053 
0054 static uint32_t gfxhub_v3_0_get_invalidate_req(unsigned int vmid,
0055                            uint32_t flush_type)
0056 {
0057     u32 req = 0;
0058 
0059     /* invalidate using legacy mode on vmid*/
0060     req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
0061                 PER_VMID_INVALIDATE_REQ, 1 << vmid);
0062     req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
0063     req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
0064     req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
0065     req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
0066     req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
0067     req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
0068     req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
0069                 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
0070 
0071     return req;
0072 }
0073 
0074 static void
0075 gfxhub_v3_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
0076                          uint32_t status)
0077 {
0078     u32 cid = REG_GET_FIELD(status,
0079                 GCVM_L2_PROTECTION_FAULT_STATUS, CID);
0080 
0081     dev_err(adev->dev,
0082         "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
0083         status);
0084     dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
0085         cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid],
0086         cid);
0087     dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
0088         REG_GET_FIELD(status,
0089         GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
0090     dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
0091         REG_GET_FIELD(status,
0092         GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
0093     dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
0094         REG_GET_FIELD(status,
0095         GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
0096     dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
0097         REG_GET_FIELD(status,
0098         GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
0099     dev_err(adev->dev, "\t RW: 0x%lx\n",
0100         REG_GET_FIELD(status,
0101         GCVM_L2_PROTECTION_FAULT_STATUS, RW));
0102 }
0103 
0104 static u64 gfxhub_v3_0_get_fb_location(struct amdgpu_device *adev)
0105 {
0106     u64 base = RREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE);
0107 
0108     base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
0109     base <<= 24;
0110 
0111     return base;
0112 }
0113 
0114 static u64 gfxhub_v3_0_get_mc_fb_offset(struct amdgpu_device *adev)
0115 {
0116     return (u64)RREG32_SOC15(GC, 0, regGCMC_VM_FB_OFFSET) << 24;
0117 }
0118 
0119 static void gfxhub_v3_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
0120                 uint64_t page_table_base)
0121 {
0122     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
0123 
0124     WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
0125                 hub->ctx_addr_distance * vmid,
0126                 lower_32_bits(page_table_base));
0127 
0128     WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
0129                 hub->ctx_addr_distance * vmid,
0130                 upper_32_bits(page_table_base));
0131 }
0132 
0133 static void gfxhub_v3_0_init_gart_aperture_regs(struct amdgpu_device *adev)
0134 {
0135     uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
0136 
0137     gfxhub_v3_0_setup_vm_pt_regs(adev, 0, pt_base);
0138 
0139     WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
0140              (u32)(adev->gmc.gart_start >> 12));
0141     WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
0142              (u32)(adev->gmc.gart_start >> 44));
0143 
0144     WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
0145              (u32)(adev->gmc.gart_end >> 12));
0146     WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
0147              (u32)(adev->gmc.gart_end >> 44));
0148 }
0149 
0150 static void gfxhub_v3_0_init_system_aperture_regs(struct amdgpu_device *adev)
0151 {
0152     uint64_t value;
0153 
0154     /* Disable AGP. */
0155     WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0);
0156     WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, 0);
0157     WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BOT, 0x00FFFFFF);
0158 
0159     /* Program the system aperture low logical page number. */
0160     WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
0161              adev->gmc.vram_start >> 18);
0162     WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
0163              adev->gmc.vram_end >> 18);
0164 
0165     /* Set default page address. */
0166     value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
0167         + adev->vm_manager.vram_base_offset;
0168     WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
0169              (u32)(value >> 12));
0170     WREG32_SOC15(GC, 0, regGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
0171              (u32)(value >> 44));
0172 
0173     /* Program "protection fault". */
0174     WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
0175              (u32)(adev->dummy_page_addr >> 12));
0176     WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
0177              (u32)((u64)adev->dummy_page_addr >> 44));
0178 
0179     WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,
0180                ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
0181 }
0182 
0183 
0184 static void gfxhub_v3_0_init_tlb_regs(struct amdgpu_device *adev)
0185 {
0186     uint32_t tmp;
0187 
0188     /* Setup TLB control */
0189     tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);
0190 
0191     tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
0192     tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
0193     tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
0194                 ENABLE_ADVANCED_DRIVER_MODEL, 1);
0195     tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
0196                 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
0197     tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
0198     tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
0199                 MTYPE, MTYPE_UC); /* UC, uncached */
0200 
0201     WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);
0202 }
0203 
0204 static void gfxhub_v3_0_init_cache_regs(struct amdgpu_device *adev)
0205 {
0206     uint32_t tmp;
0207 
0208     /* These registers are not accessible to VF-SRIOV.
0209      * The PF will program them instead.
0210      */
0211     if (amdgpu_sriov_vf(adev))
0212         return;
0213 
0214     /* Setup L2 cache */
0215     tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL);
0216     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
0217     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
0218     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
0219                 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
0220     /* XXX for emulation, Refer to closed source code.*/
0221     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
0222                 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
0223     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
0224     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
0225     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
0226     WREG32_SOC15(GC, 0, regGCVM_L2_CNTL, tmp);
0227 
0228     tmp = RREG32_SOC15(GC, 0, regGCVM_L2_CNTL2);
0229     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
0230     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
0231     WREG32_SOC15(GC, 0, regGCVM_L2_CNTL2, tmp);
0232 
0233     tmp = regGCVM_L2_CNTL3_DEFAULT;
0234     if (adev->gmc.translate_further) {
0235         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
0236         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
0237                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
0238     } else {
0239         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
0240         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
0241                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
0242     }
0243     WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, tmp);
0244 
0245     tmp = regGCVM_L2_CNTL4_DEFAULT;
0246     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
0247     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
0248     WREG32_SOC15(GC, 0, regGCVM_L2_CNTL4, tmp);
0249 
0250     tmp = regGCVM_L2_CNTL5_DEFAULT;
0251     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
0252     WREG32_SOC15(GC, 0, regGCVM_L2_CNTL5, tmp);
0253 }
0254 
0255 static void gfxhub_v3_0_enable_system_domain(struct amdgpu_device *adev)
0256 {
0257     uint32_t tmp;
0258 
0259     tmp = RREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL);
0260     tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
0261     tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
0262     tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
0263                 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
0264     WREG32_SOC15(GC, 0, regGCVM_CONTEXT0_CNTL, tmp);
0265 }
0266 
0267 static void gfxhub_v3_0_disable_identity_aperture(struct amdgpu_device *adev)
0268 {
0269     /* These registers are not accessible to VF-SRIOV.
0270      * The PF will program them instead.
0271      */
0272     if (amdgpu_sriov_vf(adev))
0273         return;
0274 
0275     WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
0276              0xFFFFFFFF);
0277     WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
0278              0x0000000F);
0279 
0280     WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
0281              0);
0282     WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
0283              0);
0284 
0285     WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
0286     WREG32_SOC15(GC, 0, regGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
0287 
0288 }
0289 
0290 static void gfxhub_v3_0_setup_vmid_config(struct amdgpu_device *adev)
0291 {
0292     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
0293     int i;
0294     uint32_t tmp;
0295 
0296     for (i = 0; i <= 14; i++) {
0297         tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i);
0298         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
0299         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
0300                     adev->vm_manager.num_level);
0301         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0302                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0303         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0304                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0305         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0306                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0307         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0308                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0309         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0310                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0311         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0312                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0313         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0314                 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0315         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0316                 PAGE_TABLE_BLOCK_SIZE,
0317                 adev->vm_manager.block_size - 9);
0318         /* Send no-retry XNACK on fault to suppress VM fault storm. */
0319         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0320                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
0321                     !amdgpu_noretry);
0322         WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL,
0323                     i * hub->ctx_distance, tmp);
0324         WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
0325                     i * hub->ctx_addr_distance, 0);
0326         WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
0327                     i * hub->ctx_addr_distance, 0);
0328         WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
0329                     i * hub->ctx_addr_distance,
0330                     lower_32_bits(adev->vm_manager.max_pfn - 1));
0331         WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
0332                     i * hub->ctx_addr_distance,
0333                     upper_32_bits(adev->vm_manager.max_pfn - 1));
0334     }
0335 
0336     hub->vm_cntx_cntl = tmp;
0337 }
0338 
0339 static void gfxhub_v3_0_program_invalidation(struct amdgpu_device *adev)
0340 {
0341     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
0342     unsigned i;
0343 
0344     for (i = 0 ; i < 18; ++i) {
0345         WREG32_SOC15_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
0346                     i * hub->eng_addr_distance, 0xffffffff);
0347         WREG32_SOC15_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
0348                     i * hub->eng_addr_distance, 0x1f);
0349     }
0350 }
0351 
0352 static int gfxhub_v3_0_gart_enable(struct amdgpu_device *adev)
0353 {
0354     if (amdgpu_sriov_vf(adev)) {
0355         /*
0356          * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
0357          * VF copy registers so vbios post doesn't program them, for
0358          * SRIOV driver need to program them
0359          */
0360         WREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_BASE,
0361                  adev->gmc.vram_start >> 24);
0362         WREG32_SOC15(GC, 0, regGCMC_VM_FB_LOCATION_TOP,
0363                  adev->gmc.vram_end >> 24);
0364     }
0365 
0366     /* GART Enable. */
0367     gfxhub_v3_0_init_gart_aperture_regs(adev);
0368     gfxhub_v3_0_init_system_aperture_regs(adev);
0369     gfxhub_v3_0_init_tlb_regs(adev);
0370     gfxhub_v3_0_init_cache_regs(adev);
0371 
0372     gfxhub_v3_0_enable_system_domain(adev);
0373     gfxhub_v3_0_disable_identity_aperture(adev);
0374     gfxhub_v3_0_setup_vmid_config(adev);
0375     gfxhub_v3_0_program_invalidation(adev);
0376 
0377     return 0;
0378 }
0379 
0380 static void gfxhub_v3_0_gart_disable(struct amdgpu_device *adev)
0381 {
0382     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
0383     u32 tmp;
0384     u32 i;
0385 
0386     /* Disable all tables */
0387     for (i = 0; i < 16; i++)
0388         WREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL,
0389                     i * hub->ctx_distance, 0);
0390 
0391     /* Setup TLB control */
0392     tmp = RREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL);
0393     tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
0394     tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
0395                 ENABLE_ADVANCED_DRIVER_MODEL, 0);
0396     WREG32_SOC15(GC, 0, regGCMC_VM_MX_L1_TLB_CNTL, tmp);
0397 
0398     /* Setup L2 cache */
0399     WREG32_FIELD15_PREREG(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
0400     WREG32_SOC15(GC, 0, regGCVM_L2_CNTL3, 0);
0401 }
0402 
0403 /**
0404  * gfxhub_v3_0_set_fault_enable_default - update GART/VM fault handling
0405  *
0406  * @adev: amdgpu_device pointer
0407  * @value: true redirects VM faults to the default page
0408  */
0409 static void gfxhub_v3_0_set_fault_enable_default(struct amdgpu_device *adev,
0410                       bool value)
0411 {
0412     u32 tmp;
0413 
0414     /* NO halt CP when page fault */
0415     tmp = RREG32_SOC15(GC, 0, regCP_DEBUG);
0416     tmp = REG_SET_FIELD(tmp, CP_DEBUG, CPG_UTCL1_ERROR_HALT_DISABLE, 1);
0417     WREG32_SOC15(GC, 0, regCP_DEBUG, tmp);
0418 
0419     /**
0420      * Set GRBM_GFX_INDEX in broad cast mode
0421      * before programming GL1C_UTCL0_CNTL1 and SQG_CONFIG
0422      */
0423     WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, regGRBM_GFX_INDEX_DEFAULT);
0424 
0425     /**
0426      * Retry respond mode: RETRY
0427      * Error (no retry) respond mode: SUCCESS
0428      */
0429     tmp = RREG32_SOC15(GC, 0, regGL1C_UTCL0_CNTL1);
0430     tmp = REG_SET_FIELD(tmp, GL1C_UTCL0_CNTL1, RESP_MODE, 0);
0431     tmp = REG_SET_FIELD(tmp, GL1C_UTCL0_CNTL1, RESP_FAULT_MODE, 0x2);
0432     WREG32_SOC15(GC, 0, regGL1C_UTCL0_CNTL1, tmp);
0433 
0434     /* These registers are not accessible to VF-SRIOV.
0435      * The PF will program them instead.
0436      */
0437     if (amdgpu_sriov_vf(adev))
0438         return;
0439 
0440     /* Disable SQ XNACK interrupt for all VMIDs */
0441     tmp = RREG32_SOC15(GC, 0, regSQG_CONFIG);
0442     tmp = REG_SET_FIELD(tmp, SQG_CONFIG, XNACK_INTR_MASK,
0443                 SQG_CONFIG__XNACK_INTR_MASK_MASK >>
0444                 SQG_CONFIG__XNACK_INTR_MASK__SHIFT);
0445     WREG32_SOC15(GC, 0, regSQG_CONFIG, tmp);
0446 
0447     tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
0448     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0449                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0450     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0451                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0452     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0453                 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0454     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0455                 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0456     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0457                 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
0458                 value);
0459     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0460                 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0461     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0462                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0463     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0464                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0465     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0466                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0467     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0468                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0469     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0470                 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0471     if (!value) {
0472         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0473                 CRASH_ON_NO_RETRY_FAULT, 1);
0474         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0475                 CRASH_ON_RETRY_FAULT, 1);
0476     }
0477     WREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
0478 }
0479 
0480 static const struct amdgpu_vmhub_funcs gfxhub_v3_0_vmhub_funcs = {
0481     .print_l2_protection_fault_status = gfxhub_v3_0_print_l2_protection_fault_status,
0482     .get_invalidate_req = gfxhub_v3_0_get_invalidate_req,
0483 };
0484 
0485 static void gfxhub_v3_0_init(struct amdgpu_device *adev)
0486 {
0487     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
0488 
0489     hub->ctx0_ptb_addr_lo32 =
0490         SOC15_REG_OFFSET(GC, 0,
0491                  regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
0492     hub->ctx0_ptb_addr_hi32 =
0493         SOC15_REG_OFFSET(GC, 0,
0494                  regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
0495     hub->vm_inv_eng0_sem =
0496         SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_SEM);
0497     hub->vm_inv_eng0_req =
0498         SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_REQ);
0499     hub->vm_inv_eng0_ack =
0500         SOC15_REG_OFFSET(GC, 0, regGCVM_INVALIDATE_ENG0_ACK);
0501     hub->vm_context0_cntl =
0502         SOC15_REG_OFFSET(GC, 0, regGCVM_CONTEXT0_CNTL);
0503     hub->vm_l2_pro_fault_status =
0504         SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS);
0505     hub->vm_l2_pro_fault_cntl =
0506         SOC15_REG_OFFSET(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
0507 
0508     hub->ctx_distance = regGCVM_CONTEXT1_CNTL - regGCVM_CONTEXT0_CNTL;
0509     hub->ctx_addr_distance = regGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
0510         regGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
0511     hub->eng_distance = regGCVM_INVALIDATE_ENG1_REQ -
0512         regGCVM_INVALIDATE_ENG0_REQ;
0513     hub->eng_addr_distance = regGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
0514         regGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
0515 
0516     hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0517         GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0518         GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0519         GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0520         GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0521         GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0522         GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
0523 
0524     hub->vmhub_funcs = &gfxhub_v3_0_vmhub_funcs;
0525 }
0526 
0527 const struct amdgpu_gfxhub_funcs gfxhub_v3_0_funcs = {
0528     .get_fb_location = gfxhub_v3_0_get_fb_location,
0529     .get_mc_fb_offset = gfxhub_v3_0_get_mc_fb_offset,
0530     .setup_vm_pt_regs = gfxhub_v3_0_setup_vm_pt_regs,
0531     .gart_enable = gfxhub_v3_0_gart_enable,
0532     .gart_disable = gfxhub_v3_0_gart_disable,
0533     .set_fault_enable_default = gfxhub_v3_0_set_fault_enable_default,
0534     .init = gfxhub_v3_0_init,
0535 };
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