Back to home page

OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #include "amdgpu.h"
0025 #include "gfxhub_v2_1.h"
0026 
0027 #include "gc/gc_10_3_0_offset.h"
0028 #include "gc/gc_10_3_0_sh_mask.h"
0029 #include "gc/gc_10_3_0_default.h"
0030 #include "navi10_enum.h"
0031 
0032 #include "soc15_common.h"
0033 
0034 #define mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP             0x16f8
0035 #define mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP_BASE_IDX    0
0036 
0037 static const char *gfxhub_client_ids[] = {
0038     "CB/DB",
0039     "Reserved",
0040     "GE1",
0041     "GE2",
0042     "CPF",
0043     "CPC",
0044     "CPG",
0045     "RLC",
0046     "TCP",
0047     "SQC (inst)",
0048     "SQC (data)",
0049     "SQG",
0050     "Reserved",
0051     "SDMA0",
0052     "SDMA1",
0053     "GCR",
0054     "SDMA2",
0055     "SDMA3",
0056 };
0057 
0058 static uint32_t gfxhub_v2_1_get_invalidate_req(unsigned int vmid,
0059                            uint32_t flush_type)
0060 {
0061     u32 req = 0;
0062 
0063     /* invalidate using legacy mode on vmid*/
0064     req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
0065                 PER_VMID_INVALIDATE_REQ, 1 << vmid);
0066     req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
0067     req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
0068     req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
0069     req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
0070     req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
0071     req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
0072     req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
0073                 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
0074 
0075     return req;
0076 }
0077 
0078 static void
0079 gfxhub_v2_1_print_l2_protection_fault_status(struct amdgpu_device *adev,
0080                          uint32_t status)
0081 {
0082     u32 cid = REG_GET_FIELD(status,
0083                 GCVM_L2_PROTECTION_FAULT_STATUS, CID);
0084 
0085     dev_err(adev->dev,
0086         "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
0087         status);
0088     dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
0089         cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid],
0090         cid);
0091     dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
0092         REG_GET_FIELD(status,
0093         GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
0094     dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
0095         REG_GET_FIELD(status,
0096         GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
0097     dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
0098         REG_GET_FIELD(status,
0099         GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
0100     dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
0101         REG_GET_FIELD(status,
0102         GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
0103     dev_err(adev->dev, "\t RW: 0x%lx\n",
0104         REG_GET_FIELD(status,
0105         GCVM_L2_PROTECTION_FAULT_STATUS, RW));
0106 }
0107 
0108 static u64 gfxhub_v2_1_get_fb_location(struct amdgpu_device *adev)
0109 {
0110     u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);
0111 
0112     base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
0113     base <<= 24;
0114 
0115     return base;
0116 }
0117 
0118 static u64 gfxhub_v2_1_get_mc_fb_offset(struct amdgpu_device *adev)
0119 {
0120     return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;
0121 }
0122 
0123 static void gfxhub_v2_1_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
0124                 uint64_t page_table_base)
0125 {
0126     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
0127 
0128     WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
0129                 hub->ctx_addr_distance * vmid,
0130                 lower_32_bits(page_table_base));
0131 
0132     WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
0133                 hub->ctx_addr_distance * vmid,
0134                 upper_32_bits(page_table_base));
0135 }
0136 
0137 static void gfxhub_v2_1_init_gart_aperture_regs(struct amdgpu_device *adev)
0138 {
0139     uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
0140 
0141     gfxhub_v2_1_setup_vm_pt_regs(adev, 0, pt_base);
0142 
0143     WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
0144              (u32)(adev->gmc.gart_start >> 12));
0145     WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
0146              (u32)(adev->gmc.gart_start >> 44));
0147 
0148     WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
0149              (u32)(adev->gmc.gart_end >> 12));
0150     WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
0151              (u32)(adev->gmc.gart_end >> 44));
0152 }
0153 
0154 static void gfxhub_v2_1_init_system_aperture_regs(struct amdgpu_device *adev)
0155 {
0156     uint64_t value;
0157 
0158     /* Program the AGP BAR */
0159     WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0);
0160     WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
0161     WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
0162 
0163     /* Program the system aperture low logical page number. */
0164     WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
0165              min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
0166     WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
0167              max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
0168 
0169     /* Set default page address. */
0170     value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
0171     WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
0172              (u32)(value >> 12));
0173     WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
0174              (u32)(value >> 44));
0175 
0176     /* Program "protection fault". */
0177     WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
0178              (u32)(adev->dummy_page_addr >> 12));
0179     WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
0180              (u32)((u64)adev->dummy_page_addr >> 44));
0181 
0182     WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,
0183                ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
0184 }
0185 
0186 
0187 static void gfxhub_v2_1_init_tlb_regs(struct amdgpu_device *adev)
0188 {
0189     uint32_t tmp;
0190 
0191     /* Setup TLB control */
0192     tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
0193 
0194     tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
0195     tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
0196     tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
0197                 ENABLE_ADVANCED_DRIVER_MODEL, 1);
0198     tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
0199                 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
0200     tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
0201                 MTYPE, MTYPE_UC); /* UC, uncached */
0202 
0203     WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
0204 }
0205 
0206 static void gfxhub_v2_1_init_cache_regs(struct amdgpu_device *adev)
0207 {
0208     uint32_t tmp;
0209 
0210     /* These registers are not accessible to VF-SRIOV.
0211      * The PF will program them instead.
0212      */
0213     if (amdgpu_sriov_vf(adev))
0214         return;
0215 
0216     /* Setup L2 cache */
0217     tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
0218     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
0219     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
0220     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
0221                 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
0222     /* XXX for emulation, Refer to closed source code.*/
0223     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
0224                 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
0225     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
0226     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
0227     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
0228     WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp);
0229 
0230     tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);
0231     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
0232     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
0233     WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);
0234 
0235     tmp = mmGCVM_L2_CNTL3_DEFAULT;
0236     if (adev->gmc.translate_further) {
0237         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
0238         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
0239                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
0240     } else {
0241         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
0242         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
0243                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
0244     }
0245     WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);
0246 
0247     tmp = mmGCVM_L2_CNTL4_DEFAULT;
0248     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
0249     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
0250     WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp);
0251 
0252     tmp = mmGCVM_L2_CNTL5_DEFAULT;
0253     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
0254     WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp);
0255 }
0256 
0257 static void gfxhub_v2_1_enable_system_domain(struct amdgpu_device *adev)
0258 {
0259     uint32_t tmp;
0260 
0261     tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);
0262     tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
0263     tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
0264     tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
0265                 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
0266     WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp);
0267 }
0268 
0269 static void gfxhub_v2_1_disable_identity_aperture(struct amdgpu_device *adev)
0270 {
0271     /* These registers are not accessible to VF-SRIOV.
0272      * The PF will program them instead.
0273      */
0274     if (amdgpu_sriov_vf(adev))
0275         return;
0276 
0277     WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
0278              0xFFFFFFFF);
0279     WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
0280              0x0000000F);
0281 
0282     WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
0283              0);
0284     WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
0285              0);
0286 
0287     WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
0288     WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
0289 
0290 }
0291 
0292 static void gfxhub_v2_1_setup_vmid_config(struct amdgpu_device *adev)
0293 {
0294     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
0295     int i;
0296     uint32_t tmp;
0297 
0298     for (i = 0; i <= 14; i++) {
0299         tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i);
0300         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
0301         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
0302                     adev->vm_manager.num_level);
0303         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0304                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0305         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0306                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0307         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0308                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0309         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0310                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0311         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0312                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0313         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0314                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0315         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0316                 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0317         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0318                 PAGE_TABLE_BLOCK_SIZE,
0319                 adev->vm_manager.block_size - 9);
0320         /* Send no-retry XNACK on fault to suppress VM fault storm. */
0321         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0322                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
0323                     !adev->gmc.noretry);
0324         WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL,
0325                     i * hub->ctx_distance, tmp);
0326         WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
0327                     i * hub->ctx_addr_distance, 0);
0328         WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
0329                     i * hub->ctx_addr_distance, 0);
0330         WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
0331                     i * hub->ctx_addr_distance,
0332                     lower_32_bits(adev->vm_manager.max_pfn - 1));
0333         WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
0334                     i * hub->ctx_addr_distance,
0335                     upper_32_bits(adev->vm_manager.max_pfn - 1));
0336     }
0337 
0338     hub->vm_cntx_cntl = tmp;
0339 }
0340 
0341 static void gfxhub_v2_1_program_invalidation(struct amdgpu_device *adev)
0342 {
0343     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
0344     unsigned i;
0345 
0346     for (i = 0 ; i < 18; ++i) {
0347         WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
0348                     i * hub->eng_addr_distance, 0xffffffff);
0349         WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
0350                     i * hub->eng_addr_distance, 0x1f);
0351     }
0352 }
0353 
0354 static int gfxhub_v2_1_gart_enable(struct amdgpu_device *adev)
0355 {
0356     if (amdgpu_sriov_vf(adev)) {
0357         /*
0358          * GCMC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
0359          * VF copy registers so vbios post doesn't program them, for
0360          * SRIOV driver need to program them
0361          */
0362         WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE,
0363                  adev->gmc.vram_start >> 24);
0364         WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP,
0365                  adev->gmc.vram_end >> 24);
0366     }
0367 
0368     /* GART Enable. */
0369     gfxhub_v2_1_init_gart_aperture_regs(adev);
0370     gfxhub_v2_1_init_system_aperture_regs(adev);
0371     gfxhub_v2_1_init_tlb_regs(adev);
0372     gfxhub_v2_1_init_cache_regs(adev);
0373 
0374     gfxhub_v2_1_enable_system_domain(adev);
0375     gfxhub_v2_1_disable_identity_aperture(adev);
0376     gfxhub_v2_1_setup_vmid_config(adev);
0377     gfxhub_v2_1_program_invalidation(adev);
0378 
0379     return 0;
0380 }
0381 
0382 static void gfxhub_v2_1_gart_disable(struct amdgpu_device *adev)
0383 {
0384     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
0385     u32 tmp;
0386     u32 i;
0387 
0388     /* Disable all tables */
0389     for (i = 0; i < 16; i++)
0390         WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL,
0391                     i * hub->ctx_distance, 0);
0392 
0393     /* Setup TLB control */
0394     tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
0395     tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
0396     tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
0397                 ENABLE_ADVANCED_DRIVER_MODEL, 0);
0398     WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
0399 
0400     /* Setup L2 cache */
0401     WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
0402     WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);
0403 }
0404 
0405 /**
0406  * gfxhub_v2_1_set_fault_enable_default - update GART/VM fault handling
0407  *
0408  * @adev: amdgpu_device pointer
0409  * @value: true redirects VM faults to the default page
0410  */
0411 static void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev,
0412                       bool value)
0413 {
0414     u32 tmp;
0415 
0416     /* These registers are not accessible to VF-SRIOV.
0417      * The PF will program them instead.
0418      */
0419     if (amdgpu_sriov_vf(adev))
0420         return;
0421 
0422     tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
0423     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0424                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0425     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0426                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0427     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0428                 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0429     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0430                 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0431     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0432                 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
0433                 value);
0434     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0435                 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0436     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0437                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0438     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0439                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0440     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0441                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0442     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0443                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0444     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0445                 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0446     if (!value) {
0447         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0448                 CRASH_ON_NO_RETRY_FAULT, 1);
0449         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0450                 CRASH_ON_RETRY_FAULT, 1);
0451     }
0452     WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
0453 }
0454 
0455 static const struct amdgpu_vmhub_funcs gfxhub_v2_1_vmhub_funcs = {
0456     .print_l2_protection_fault_status = gfxhub_v2_1_print_l2_protection_fault_status,
0457     .get_invalidate_req = gfxhub_v2_1_get_invalidate_req,
0458 };
0459 
0460 static void gfxhub_v2_1_init(struct amdgpu_device *adev)
0461 {
0462     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
0463 
0464     hub->ctx0_ptb_addr_lo32 =
0465         SOC15_REG_OFFSET(GC, 0,
0466                  mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
0467     hub->ctx0_ptb_addr_hi32 =
0468         SOC15_REG_OFFSET(GC, 0,
0469                  mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
0470     hub->vm_inv_eng0_sem =
0471         SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM);
0472     hub->vm_inv_eng0_req =
0473         SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ);
0474     hub->vm_inv_eng0_ack =
0475         SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK);
0476     hub->vm_context0_cntl =
0477         SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL);
0478     hub->vm_l2_pro_fault_status =
0479         SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS);
0480     hub->vm_l2_pro_fault_cntl =
0481         SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
0482 
0483     hub->ctx_distance = mmGCVM_CONTEXT1_CNTL - mmGCVM_CONTEXT0_CNTL;
0484     hub->ctx_addr_distance = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
0485         mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
0486     hub->eng_distance = mmGCVM_INVALIDATE_ENG1_REQ -
0487         mmGCVM_INVALIDATE_ENG0_REQ;
0488     hub->eng_addr_distance = mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
0489         mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
0490 
0491     hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0492         GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0493         GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0494         GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0495         GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0496         GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0497         GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
0498 
0499     hub->vmhub_funcs = &gfxhub_v2_1_vmhub_funcs;
0500 }
0501 
0502 static int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)
0503 {
0504     u32 xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_CNTL);
0505     u32 max_region =
0506         REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);
0507     u32 max_num_physical_nodes   = 0;
0508     u32 max_physical_node_id     = 0;
0509 
0510     switch (adev->ip_versions[XGMI_HWIP][0]) {
0511     case IP_VERSION(4, 8, 0):
0512         max_num_physical_nodes   = 4;
0513         max_physical_node_id     = 3;
0514         break;
0515     default:
0516         return -EINVAL;
0517     }
0518 
0519     /* PF_MAX_REGION=0 means xgmi is disabled */
0520     if (max_region) {
0521         adev->gmc.xgmi.num_physical_nodes = max_region + 1;
0522         if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes)
0523             return -EINVAL;
0524 
0525         adev->gmc.xgmi.physical_node_id =
0526             REG_GET_FIELD(xgmi_lfb_cntl, GCMC_VM_XGMI_LFB_CNTL, PF_LFB_REGION);
0527         if (adev->gmc.xgmi.physical_node_id > max_physical_node_id)
0528             return -EINVAL;
0529 
0530         adev->gmc.xgmi.node_segment_size = REG_GET_FIELD(
0531             RREG32_SOC15(GC, 0, mmGCMC_VM_XGMI_LFB_SIZE),
0532             GCMC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;
0533     }
0534 
0535     return 0;
0536 }
0537 
0538 static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev)
0539 {
0540     int i;
0541     u32 tmp = 0, disabled_sa = 0;
0542     u32 efuse_setting, vbios_setting;
0543 
0544     u32 max_sa_mask = amdgpu_gfx_create_bitmask(
0545         adev->gfx.config.max_sh_per_se *
0546         adev->gfx.config.max_shader_engines);
0547 
0548     switch (adev->ip_versions[GC_HWIP][0]) {
0549     case IP_VERSION(10, 3, 1):
0550     case IP_VERSION(10, 3, 3):
0551         /* Get SA disabled bitmap from eFuse setting */
0552         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
0553         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
0554         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
0555 
0556         /* Get SA disabled bitmap from VBIOS setting */
0557         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
0558         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
0559         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
0560 
0561         disabled_sa |= efuse_setting | vbios_setting;
0562         /* Make sure not to report harvested SAs beyond the max SA count */
0563         disabled_sa &= max_sa_mask;
0564 
0565         for (i = 0; disabled_sa > 0; i++) {
0566             if (disabled_sa & 1)
0567                 tmp |= 0x3 << (i * 2);
0568             disabled_sa >>= 1;
0569         }
0570         disabled_sa = tmp;
0571 
0572         WREG32_SOC15(GC, 0, mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP, disabled_sa);
0573         break;
0574     default:
0575         break;
0576     }
0577 }
0578 
0579 const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {
0580     .get_fb_location = gfxhub_v2_1_get_fb_location,
0581     .get_mc_fb_offset = gfxhub_v2_1_get_mc_fb_offset,
0582     .setup_vm_pt_regs = gfxhub_v2_1_setup_vm_pt_regs,
0583     .gart_enable = gfxhub_v2_1_gart_enable,
0584     .gart_disable = gfxhub_v2_1_gart_disable,
0585     .set_fault_enable_default = gfxhub_v2_1_set_fault_enable_default,
0586     .init = gfxhub_v2_1_init,
0587     .get_xgmi_info = gfxhub_v2_1_get_xgmi_info,
0588     .utcl2_harvest = gfxhub_v2_1_utcl2_harvest,
0589 };
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!