amd/amdgpu/gfxhub_v2_0.c

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #include "amdgpu.h"
0025 #include "gfxhub_v2_0.h"
0026
0027 #include "gc/gc_10_1_0_offset.h"
0028 #include "gc/gc_10_1_0_sh_mask.h"
0029 #include "gc/gc_10_1_0_default.h"
0030 #include "navi10_enum.h"
0031
0032 #include "soc15_common.h"
0033
0034 static const char *gfxhub_client_ids[] = {
0035     "CB/DB",
0036     "Reserved",
0037     "GE1",
0038     "GE2",
0039     "CPF",
0040     "CPC",
0041     "CPG",
0042     "RLC",
0043     "TCP",
0044     "SQC (inst)",
0045     "SQC (data)",
0046     "SQG",
0047     "Reserved",
0048     "SDMA0",
0049     "SDMA1",
0050     "GCR",
0051     "SDMA2",
0052     "SDMA3",
0053 };
0054
0055 static uint32_t gfxhub_v2_0_get_invalidate_req(unsigned int vmid,
0056                            uint32_t flush_type)
0057 {
0058     u32 req = 0;
0059
0060     /* invalidate using legacy mode on vmid*/
0061     req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
0062                 PER_VMID_INVALIDATE_REQ, 1 << vmid);
0063     req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
0064     req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
0065     req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
0066     req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
0067     req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
0068     req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
0069     req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
0070                 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
0071
0072     return req;
0073 }
0074
0075 static void
0076 gfxhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
0077                          uint32_t status)
0078 {
0079     u32 cid = REG_GET_FIELD(status,
0080                 GCVM_L2_PROTECTION_FAULT_STATUS, CID);
0081
0082     dev_err(adev->dev,
0083         "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
0084         status);
0085     dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
0086         cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" : gfxhub_client_ids[cid],
0087         cid);
0088     dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
0089         REG_GET_FIELD(status,
0090         GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
0091     dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
0092         REG_GET_FIELD(status,
0093         GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
0094     dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
0095         REG_GET_FIELD(status,
0096         GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
0097     dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
0098         REG_GET_FIELD(status,
0099         GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
0100     dev_err(adev->dev, "\t RW: 0x%lx\n",
0101         REG_GET_FIELD(status,
0102         GCVM_L2_PROTECTION_FAULT_STATUS, RW));
0103 }
0104
0105 static u64 gfxhub_v2_0_get_fb_location(struct amdgpu_device *adev)
0106 {
0107     u64 base = RREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE);
0108
0109     base &= GCMC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
0110     base <<= 24;
0111
0112     return base;
0113 }
0114
0115 static u64 gfxhub_v2_0_get_mc_fb_offset(struct amdgpu_device *adev)
0116 {
0117     return (u64)RREG32_SOC15(GC, 0, mmGCMC_VM_FB_OFFSET) << 24;
0118 }
0119
0120 static void gfxhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
0121                 uint64_t page_table_base)
0122 {
0123     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
0124
0125     WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
0126                 hub->ctx_addr_distance * vmid,
0127                 lower_32_bits(page_table_base));
0128
0129     WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
0130                 hub->ctx_addr_distance * vmid,
0131                 upper_32_bits(page_table_base));
0132 }
0133
0134 static void gfxhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)
0135 {
0136     uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
0137
0138     gfxhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);
0139
0140     WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
0141              (u32)(adev->gmc.gart_start >> 12));
0142     WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
0143              (u32)(adev->gmc.gart_start >> 44));
0144
0145     WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
0146              (u32)(adev->gmc.gart_end >> 12));
0147     WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
0148              (u32)(adev->gmc.gart_end >> 44));
0149 }
0150
0151 static void gfxhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
0152 {
0153     uint64_t value;
0154
0155     if (!amdgpu_sriov_vf(adev)) {
0156         /* Program the AGP BAR */
0157         WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BASE, 0);
0158         WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
0159         WREG32_SOC15(GC, 0, mmGCMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
0160
0161         /* Program the system aperture low logical page number. */
0162         WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_LOW_ADDR,
0163                  min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
0164         WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
0165                  max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
0166
0167         /* Set default page address. */
0168         value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
0169         WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
0170                  (u32)(value >> 12));
0171         WREG32_SOC15(GC, 0, mmGCMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
0172                  (u32)(value >> 44));
0173     }
0174
0175     /* Program "protection fault". */
0176     WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
0177              (u32)(adev->dummy_page_addr >> 12));
0178     WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
0179              (u32)((u64)adev->dummy_page_addr >> 44));
0180
0181     WREG32_FIELD15(GC, 0, GCVM_L2_PROTECTION_FAULT_CNTL2,
0182                ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
0183 }
0184
0185
0186 static void gfxhub_v2_0_init_tlb_regs(struct amdgpu_device *adev)
0187 {
0188     uint32_t tmp;
0189
0190     /* Setup TLB control */
0191     tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
0192
0193     tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
0194     tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
0195     tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
0196                 ENABLE_ADVANCED_DRIVER_MODEL, 1);
0197     tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
0198                 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
0199     tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
0200                 MTYPE, MTYPE_UC); /* UC, uncached */
0201
0202     WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
0203 }
0204
0205 static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
0206 {
0207     uint32_t tmp;
0208
0209     /* These regs are not accessible for VF, PF will program these in SRIOV */
0210     if (amdgpu_sriov_vf(adev))
0211         return;
0212
0213     /* Setup L2 cache */
0214     tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
0215     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
0216     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
0217     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
0218                 ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
0219     /* XXX for emulation, Refer to closed source code.*/
0220     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,
0221                 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
0222     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
0223     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
0224     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
0225     WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, tmp);
0226
0227     tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);
0228     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
0229     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
0230     WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp);
0231
0232     tmp = mmGCVM_L2_CNTL3_DEFAULT;
0233     if (adev->gmc.translate_further) {
0234         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
0235         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
0236                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
0237     } else {
0238         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
0239         tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3,
0240                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
0241     }
0242     WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp);
0243
0244     tmp = mmGCVM_L2_CNTL4_DEFAULT;
0245     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
0246     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
0247     WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL4, tmp);
0248
0249     tmp = mmGCVM_L2_CNTL5_DEFAULT;
0250     tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
0251     WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL5, tmp);
0252 }
0253
0254 static void gfxhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
0255 {
0256     uint32_t tmp;
0257
0258     tmp = RREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL);
0259     tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
0260     tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
0261     tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT0_CNTL,
0262                 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
0263     WREG32_SOC15(GC, 0, mmGCVM_CONTEXT0_CNTL, tmp);
0264 }
0265
0266 static void gfxhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
0267 {
0268     WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
0269              0xFFFFFFFF);
0270     WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
0271              0x0000000F);
0272
0273     WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
0274              0);
0275     WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
0276              0);
0277
0278     WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
0279     WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
0280
0281 }
0282
0283 static void gfxhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
0284 {
0285     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
0286     int i;
0287     uint32_t tmp;
0288
0289     for (i = 0; i <= 14; i++) {
0290         tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i);
0291         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
0292         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
0293                     adev->vm_manager.num_level);
0294         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0295                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0296         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0297                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0298         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0299                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0300         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0301                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0302         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0303                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0304         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0305                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0306         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0307                 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0308         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0309                 PAGE_TABLE_BLOCK_SIZE,
0310                 adev->vm_manager.block_size - 9);
0311         /* Send no-retry XNACK on fault to suppress VM fault storm. */
0312         tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL,
0313                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
0314                     !adev->gmc.noretry);
0315         WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL,
0316                     i * hub->ctx_distance, tmp);
0317         WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
0318                     i * hub->ctx_addr_distance, 0);
0319         WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
0320                     i * hub->ctx_addr_distance, 0);
0321         WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
0322                     i * hub->ctx_addr_distance,
0323                     lower_32_bits(adev->vm_manager.max_pfn - 1));
0324         WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
0325                     i * hub->ctx_addr_distance,
0326                     upper_32_bits(adev->vm_manager.max_pfn - 1));
0327     }
0328
0329     hub->vm_cntx_cntl = tmp;
0330 }
0331
0332 static void gfxhub_v2_0_program_invalidation(struct amdgpu_device *adev)
0333 {
0334     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
0335     unsigned i;
0336
0337     for (i = 0 ; i < 18; ++i) {
0338         WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
0339                     i * hub->eng_addr_distance, 0xffffffff);
0340         WREG32_SOC15_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
0341                     i * hub->eng_addr_distance, 0x1f);
0342     }
0343 }
0344
0345 static int gfxhub_v2_0_gart_enable(struct amdgpu_device *adev)
0346 {
0347     /* GART Enable. */
0348     gfxhub_v2_0_init_gart_aperture_regs(adev);
0349     gfxhub_v2_0_init_system_aperture_regs(adev);
0350     gfxhub_v2_0_init_tlb_regs(adev);
0351     gfxhub_v2_0_init_cache_regs(adev);
0352
0353     gfxhub_v2_0_enable_system_domain(adev);
0354     gfxhub_v2_0_disable_identity_aperture(adev);
0355     gfxhub_v2_0_setup_vmid_config(adev);
0356     gfxhub_v2_0_program_invalidation(adev);
0357
0358     return 0;
0359 }
0360
0361 static void gfxhub_v2_0_gart_disable(struct amdgpu_device *adev)
0362 {
0363     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
0364     u32 tmp;
0365     u32 i;
0366
0367     /* Disable all tables */
0368     for (i = 0; i < 16; i++)
0369         WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL,
0370                     i * hub->ctx_distance, 0);
0371
0372     /* Setup TLB control */
0373     tmp = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
0374     tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
0375     tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL,
0376                 ENABLE_ADVANCED_DRIVER_MODEL, 0);
0377     WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, tmp);
0378
0379     if (!amdgpu_sriov_vf(adev)) {
0380         /* Setup L2 cache */
0381         WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0);
0382         WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, 0);
0383     }
0384 }
0385
0386 /**
0387  * gfxhub_v2_0_set_fault_enable_default - update GART/VM fault handling
0388  *
0389  * @adev: amdgpu_device pointer
0390  * @value: true redirects VM faults to the default page
0391  */
0392 static void gfxhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev,
0393                       bool value)
0394 {
0395     u32 tmp;
0396     tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
0397     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0398                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0399     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0400                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0401     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0402                 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0403     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0404                 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0405     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0406                 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
0407                 value);
0408     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0409                 NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0410     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0411                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0412     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0413                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0414     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0415                 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0416     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0417                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0418     tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0419                 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0420     if (!value) {
0421         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0422                 CRASH_ON_NO_RETRY_FAULT, 1);
0423         tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
0424                 CRASH_ON_RETRY_FAULT, 1);
0425     }
0426     WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, tmp);
0427 }
0428
0429 static const struct amdgpu_vmhub_funcs gfxhub_v2_0_vmhub_funcs = {
0430     .print_l2_protection_fault_status = gfxhub_v2_0_print_l2_protection_fault_status,
0431     .get_invalidate_req = gfxhub_v2_0_get_invalidate_req,
0432 };
0433
0434 static void gfxhub_v2_0_init(struct amdgpu_device *adev)
0435 {
0436     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
0437
0438     hub->ctx0_ptb_addr_lo32 =
0439         SOC15_REG_OFFSET(GC, 0,
0440                  mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
0441     hub->ctx0_ptb_addr_hi32 =
0442         SOC15_REG_OFFSET(GC, 0,
0443                  mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
0444     hub->vm_inv_eng0_sem =
0445         SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_SEM);
0446     hub->vm_inv_eng0_req =
0447         SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_REQ);
0448     hub->vm_inv_eng0_ack =
0449         SOC15_REG_OFFSET(GC, 0, mmGCVM_INVALIDATE_ENG0_ACK);
0450     hub->vm_context0_cntl =
0451         SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL);
0452     hub->vm_l2_pro_fault_status =
0453         SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_STATUS);
0454     hub->vm_l2_pro_fault_cntl =
0455         SOC15_REG_OFFSET(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
0456
0457     hub->ctx_distance = mmGCVM_CONTEXT1_CNTL - mmGCVM_CONTEXT0_CNTL;
0458     hub->ctx_addr_distance = mmGCVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
0459         mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
0460     hub->eng_distance = mmGCVM_INVALIDATE_ENG1_REQ -
0461         mmGCVM_INVALIDATE_ENG0_REQ;
0462     hub->eng_addr_distance = mmGCVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
0463         mmGCVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
0464
0465     hub->vm_cntx_cntl_vm_fault = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0466         GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0467         GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0468         GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0469         GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0470         GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
0471         GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
0472
0473     hub->vmhub_funcs = &gfxhub_v2_0_vmhub_funcs;
0474 }
0475
0476 const struct amdgpu_gfxhub_funcs gfxhub_v2_0_funcs = {
0477     .get_fb_location = gfxhub_v2_0_get_fb_location,
0478     .get_mc_fb_offset = gfxhub_v2_0_get_mc_fb_offset,
0479     .setup_vm_pt_regs = gfxhub_v2_0_setup_vm_pt_regs,
0480     .gart_enable = gfxhub_v2_0_gart_enable,
0481     .gart_disable = gfxhub_v2_0_gart_disable,
0482     .set_fault_enable_default = gfxhub_v2_0_set_fault_enable_default,
0483     .init = gfxhub_v2_0_init,
0484 };