amd/amdgpu/gfxhub_v1_1.c

0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include "amdgpu.h"
0024 #include "gfxhub_v1_1.h"
0025
0026 #include "gc/gc_9_2_1_offset.h"
0027 #include "gc/gc_9_2_1_sh_mask.h"
0028
0029 #include "soc15_common.h"
0030
0031 #define mmMC_VM_XGMI_LFB_CNTL_ALDE          0x0978
0032 #define mmMC_VM_XGMI_LFB_CNTL_ALDE_BASE_IDX     0
0033 #define mmMC_VM_XGMI_LFB_SIZE_ALDE          0x0979
0034 #define mmMC_VM_XGMI_LFB_SIZE_ALDE_BASE_IDX     0
0035 //MC_VM_XGMI_LFB_CNTL
0036 #define MC_VM_XGMI_LFB_CNTL_ALDE__PF_LFB_REGION__SHIFT  0x0
0037 #define MC_VM_XGMI_LFB_CNTL_ALDE__PF_MAX_REGION__SHIFT  0x4
0038 #define MC_VM_XGMI_LFB_CNTL_ALDE__PF_LFB_REGION_MASK    0x0000000FL
0039 #define MC_VM_XGMI_LFB_CNTL_ALDE__PF_MAX_REGION_MASK    0x000000F0L
0040 //MC_VM_XGMI_LFB_SIZE
0041 #define MC_VM_XGMI_LFB_SIZE_ALDE__PF_LFB_SIZE__SHIFT    0x0
0042 #define MC_VM_XGMI_LFB_SIZE_ALDE__PF_LFB_SIZE_MASK  0x0001FFFFL
0043
0044 int gfxhub_v1_1_get_xgmi_info(struct amdgpu_device *adev)
0045 {
0046     u32 max_num_physical_nodes;
0047     u32 max_physical_node_id;
0048     u32 xgmi_lfb_cntl;
0049     u32 max_region;
0050     u64 seg_size;
0051
0052     if (adev->asic_type == CHIP_ALDEBARAN) {
0053         xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL_ALDE);
0054         seg_size = REG_GET_FIELD(
0055             RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE_ALDE),
0056             MC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;
0057         max_region =
0058             REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL_ALDE, PF_MAX_REGION);
0059     } else {
0060         xgmi_lfb_cntl = RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_CNTL);
0061         seg_size = REG_GET_FIELD(
0062             RREG32_SOC15(GC, 0, mmMC_VM_XGMI_LFB_SIZE),
0063             MC_VM_XGMI_LFB_SIZE, PF_LFB_SIZE) << 24;
0064         max_region =
0065             REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION);
0066     }
0067
0068
0069
0070     switch (adev->asic_type) {
0071     case CHIP_VEGA20:
0072         max_num_physical_nodes   = 4;
0073         max_physical_node_id     = 3;
0074         break;
0075     case CHIP_ARCTURUS:
0076         max_num_physical_nodes   = 8;
0077         max_physical_node_id     = 7;
0078         break;
0079     case CHIP_ALDEBARAN:
0080         max_num_physical_nodes   = 16;
0081         max_physical_node_id     = 15;
0082         break;
0083     default:
0084         return -EINVAL;
0085     }
0086
0087     /* PF_MAX_REGION=0 means xgmi is disabled */
0088     if (max_region || adev->gmc.xgmi.connected_to_cpu) {
0089         adev->gmc.xgmi.num_physical_nodes = max_region + 1;
0090
0091         if (adev->gmc.xgmi.num_physical_nodes > max_num_physical_nodes)
0092             return -EINVAL;
0093
0094         if (adev->asic_type == CHIP_ALDEBARAN) {
0095             adev->gmc.xgmi.physical_node_id =
0096                 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL_ALDE,
0097                         PF_LFB_REGION);
0098         } else {
0099             adev->gmc.xgmi.physical_node_id =
0100                 REG_GET_FIELD(xgmi_lfb_cntl, MC_VM_XGMI_LFB_CNTL,
0101                         PF_LFB_REGION);
0102         }
0103
0104         if (adev->gmc.xgmi.physical_node_id > max_physical_node_id)
0105             return -EINVAL;
0106
0107         adev->gmc.xgmi.node_segment_size = seg_size;
0108     }
0109
0110     return 0;
0111 }