amd/amdgpu/gfxhub_v1_0.c

0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include "amdgpu.h"
0024 #include "gfxhub_v1_0.h"
0025 #include "gfxhub_v1_1.h"
0026
0027 #include "gc/gc_9_0_offset.h"
0028 #include "gc/gc_9_0_sh_mask.h"
0029 #include "gc/gc_9_0_default.h"
0030 #include "vega10_enum.h"
0031
0032 #include "soc15_common.h"
0033
0034 static u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
0035 {
0036     return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24;
0037 }
0038
0039 static void gfxhub_v1_0_setup_vm_pt_regs(struct amdgpu_device *adev,
0040                      uint32_t vmid,
0041                      uint64_t page_table_base)
0042 {
0043     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
0044
0045     WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
0046                 hub->ctx_addr_distance * vmid,
0047                 lower_32_bits(page_table_base));
0048
0049     WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
0050                 hub->ctx_addr_distance * vmid,
0051                 upper_32_bits(page_table_base));
0052 }
0053
0054 static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
0055 {
0056     uint64_t pt_base;
0057
0058     if (adev->gmc.pdb0_bo)
0059         pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo);
0060     else
0061         pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
0062
0063     gfxhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base);
0064
0065     /* If use GART for FB translation, vmid0 page table covers both
0066      * vram and system memory (gart)
0067      */
0068     if (adev->gmc.pdb0_bo) {
0069         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
0070                 (u32)(adev->gmc.fb_start >> 12));
0071         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
0072                 (u32)(adev->gmc.fb_start >> 44));
0073
0074         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
0075                 (u32)(adev->gmc.gart_end >> 12));
0076         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
0077                 (u32)(adev->gmc.gart_end >> 44));
0078     } else {
0079         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
0080                 (u32)(adev->gmc.gart_start >> 12));
0081         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
0082                 (u32)(adev->gmc.gart_start >> 44));
0083
0084         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
0085                 (u32)(adev->gmc.gart_end >> 12));
0086         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
0087                 (u32)(adev->gmc.gart_end >> 44));
0088     }
0089 }
0090
0091 static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
0092 {
0093     uint64_t value;
0094
0095     /* Program the AGP BAR */
0096     WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BASE, 0);
0097     WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
0098     WREG32_SOC15_RLC(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
0099
0100     if (!amdgpu_sriov_vf(adev) || adev->asic_type <= CHIP_VEGA10) {
0101         /* Program the system aperture low logical page number. */
0102         WREG32_SOC15_RLC(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
0103             min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
0104
0105         if (adev->apu_flags & AMD_APU_IS_RAVEN2)
0106             /*
0107             * Raven2 has a HW issue that it is unable to use the
0108             * vram which is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR.
0109             * So here is the workaround that increase system
0110             * aperture high address (add 1) to get rid of the VM
0111             * fault and hardware hang.
0112             */
0113             WREG32_SOC15_RLC(GC, 0,
0114                      mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
0115                      max((adev->gmc.fb_end >> 18) + 0x1,
0116                          adev->gmc.agp_end >> 18));
0117         else
0118             WREG32_SOC15_RLC(
0119                 GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
0120                 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
0121
0122         /* Set default page address. */
0123         value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
0124         WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
0125                  (u32)(value >> 12));
0126         WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
0127                  (u32)(value >> 44));
0128
0129         /* Program "protection fault". */
0130         WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
0131                  (u32)(adev->dummy_page_addr >> 12));
0132         WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
0133                  (u32)((u64)adev->dummy_page_addr >> 44));
0134
0135         WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2,
0136                    ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
0137     }
0138
0139     /* In the case squeezing vram into GART aperture, we don't use
0140      * FB aperture and AGP aperture. Disable them.
0141      */
0142     if (adev->gmc.pdb0_bo) {
0143         WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP, 0);
0144         WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);
0145         WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
0146         WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFF);
0147         WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);
0148         WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);
0149     }
0150 }
0151
0152 static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
0153 {
0154     uint32_t tmp;
0155
0156     /* Setup TLB control */
0157     tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
0158
0159     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
0160     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
0161     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
0162                 ENABLE_ADVANCED_DRIVER_MODEL, 1);
0163     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
0164                 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
0165     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
0166                 MTYPE, MTYPE_UC);/* XXX for emulation. */
0167     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
0168
0169     WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
0170 }
0171
0172 static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
0173 {
0174     uint32_t tmp;
0175
0176     /* Setup L2 cache */
0177     tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);
0178     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
0179     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
0180     /* XXX for emulation, Refer to closed source code.*/
0181     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
0182                 0);
0183     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
0184     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
0185     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
0186     WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL, tmp);
0187
0188     tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);
0189     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
0190     tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
0191     WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp);
0192
0193     tmp = mmVM_L2_CNTL3_DEFAULT;
0194     if (adev->gmc.translate_further) {
0195         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
0196         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
0197                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
0198     } else {
0199         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
0200         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
0201                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
0202     }
0203     WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL3, tmp);
0204
0205     tmp = mmVM_L2_CNTL4_DEFAULT;
0206     if (adev->gmc.xgmi.connected_to_cpu) {
0207         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
0208         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
0209     } else {
0210         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
0211         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
0212     }
0213     WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL4, tmp);
0214 }
0215
0216 static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
0217 {
0218     uint32_t tmp;
0219
0220     tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);
0221     tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
0222     tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
0223             adev->gmc.vmid0_page_table_depth);
0224     tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,
0225             adev->gmc.vmid0_page_table_block_size);
0226     tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
0227                 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
0228     WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);
0229 }
0230
0231 static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
0232 {
0233     WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
0234              0XFFFFFFFF);
0235     WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
0236              0x0000000F);
0237
0238     WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
0239              0);
0240     WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
0241              0);
0242
0243     WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
0244     WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
0245
0246 }
0247
0248 static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
0249 {
0250     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
0251     unsigned num_level, block_size;
0252     uint32_t tmp;
0253     int i;
0254
0255     num_level = adev->vm_manager.num_level;
0256     block_size = adev->vm_manager.block_size;
0257     if (adev->gmc.translate_further)
0258         num_level -= 1;
0259     else
0260         block_size -= 9;
0261
0262     for (i = 0; i <= 14; i++) {
0263         tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);
0264         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
0265         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
0266                     num_level);
0267         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0268                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0269         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0270                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
0271                     1);
0272         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0273                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0274         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0275                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0276         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0277                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0278         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0279                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0280         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0281                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
0282         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0283                     PAGE_TABLE_BLOCK_SIZE,
0284                     block_size);
0285         /* Send no-retry XNACK on fault to suppress VM fault storm.
0286          * On Aldebaran, XNACK can be enabled in the SQ per-process.
0287          * Retry faults need to be enabled for that to work.
0288          */
0289         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
0290                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
0291                     !adev->gmc.noretry ||
0292                     adev->asic_type == CHIP_ALDEBARAN);
0293         WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL,
0294                     i * hub->ctx_distance, tmp);
0295         WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
0296                     i * hub->ctx_addr_distance, 0);
0297         WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
0298                     i * hub->ctx_addr_distance, 0);
0299         WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
0300                     i * hub->ctx_addr_distance,
0301                     lower_32_bits(adev->vm_manager.max_pfn - 1));
0302         WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
0303                     i * hub->ctx_addr_distance,
0304                     upper_32_bits(adev->vm_manager.max_pfn - 1));
0305     }
0306 }
0307
0308 static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev)
0309 {
0310     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
0311     unsigned i;
0312
0313     for (i = 0 ; i < 18; ++i) {
0314         WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
0315                     i * hub->eng_addr_distance, 0xffffffff);
0316         WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
0317                     i * hub->eng_addr_distance, 0x1f);
0318     }
0319 }
0320
0321 static int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
0322 {
0323     /* GART Enable. */
0324     gfxhub_v1_0_init_gart_aperture_regs(adev);
0325     gfxhub_v1_0_init_system_aperture_regs(adev);
0326     gfxhub_v1_0_init_tlb_regs(adev);
0327     if (!amdgpu_sriov_vf(adev))
0328         gfxhub_v1_0_init_cache_regs(adev);
0329
0330     gfxhub_v1_0_enable_system_domain(adev);
0331     if (!amdgpu_sriov_vf(adev))
0332         gfxhub_v1_0_disable_identity_aperture(adev);
0333     gfxhub_v1_0_setup_vmid_config(adev);
0334     gfxhub_v1_0_program_invalidation(adev);
0335
0336     return 0;
0337 }
0338
0339 static void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
0340 {
0341     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
0342     u32 tmp;
0343     u32 i;
0344
0345     /* Disable all tables */
0346     for (i = 0; i < 16; i++)
0347         WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL,
0348                     i * hub->ctx_distance, 0);
0349
0350     if (amdgpu_sriov_vf(adev))
0351         /* Avoid write to GMC registers */
0352         return;
0353
0354     /* Setup TLB control */
0355     tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
0356     tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
0357     tmp = REG_SET_FIELD(tmp,
0358                 MC_VM_MX_L1_TLB_CNTL,
0359                 ENABLE_ADVANCED_DRIVER_MODEL,
0360                 0);
0361     WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
0362
0363     /* Setup L2 cache */
0364     WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
0365     WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0);
0366 }
0367
0368 /**
0369  * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling
0370  *
0371  * @adev: amdgpu_device pointer
0372  * @value: true redirects VM faults to the default page
0373  */
0374 static void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
0375                          bool value)
0376 {
0377     u32 tmp;
0378     tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
0379     tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
0380             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0381     tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
0382             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0383     tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
0384             PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0385     tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
0386             PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0387     tmp = REG_SET_FIELD(tmp,
0388             VM_L2_PROTECTION_FAULT_CNTL,
0389             TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
0390             value);
0391     tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
0392             NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0393     tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
0394             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0395     tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
0396             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0397     tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
0398             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0399     tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
0400             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0401     tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
0402             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
0403     if (!value) {
0404         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
0405                 CRASH_ON_NO_RETRY_FAULT, 1);
0406         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
0407                 CRASH_ON_RETRY_FAULT, 1);
0408     }
0409     WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
0410 }
0411
0412 static void gfxhub_v1_0_init(struct amdgpu_device *adev)
0413 {
0414     struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB_0];
0415
0416     hub->ctx0_ptb_addr_lo32 =
0417         SOC15_REG_OFFSET(GC, 0,
0418                  mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
0419     hub->ctx0_ptb_addr_hi32 =
0420         SOC15_REG_OFFSET(GC, 0,
0421                  mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
0422     hub->vm_inv_eng0_sem =
0423         SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_SEM);
0424     hub->vm_inv_eng0_req =
0425         SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
0426     hub->vm_inv_eng0_ack =
0427         SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK);
0428     hub->vm_context0_cntl =
0429         SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL);
0430     hub->vm_l2_pro_fault_status =
0431         SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
0432     hub->vm_l2_pro_fault_cntl =
0433         SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
0434
0435     hub->ctx_distance = mmVM_CONTEXT1_CNTL - mmVM_CONTEXT0_CNTL;
0436     hub->ctx_addr_distance = mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
0437         mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
0438     hub->eng_distance = mmVM_INVALIDATE_ENG1_REQ - mmVM_INVALIDATE_ENG0_REQ;
0439     hub->eng_addr_distance = mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
0440         mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
0441 }
0442
0443
0444 const struct amdgpu_gfxhub_funcs gfxhub_v1_0_funcs = {
0445     .get_mc_fb_offset = gfxhub_v1_0_get_mc_fb_offset,
0446     .setup_vm_pt_regs = gfxhub_v1_0_setup_vm_pt_regs,
0447     .gart_enable = gfxhub_v1_0_gart_enable,
0448     .gart_disable = gfxhub_v1_0_gart_disable,
0449     .set_fault_enable_default = gfxhub_v1_0_set_fault_enable_default,
0450     .init = gfxhub_v1_0_init,
0451     .get_xgmi_info = gfxhub_v1_1_get_xgmi_info,
0452 };