amd/amdgpu/gfx_v9_4_2.c

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include "amdgpu.h"
0024 #include "soc15.h"
0025 #include "soc15d.h"
0026
0027 #include "gc/gc_9_4_2_offset.h"
0028 #include "gc/gc_9_4_2_sh_mask.h"
0029 #include "gfx_v9_0.h"
0030
0031 #include "gfx_v9_4_2.h"
0032 #include "amdgpu_ras.h"
0033 #include "amdgpu_gfx.h"
0034
0035 #define SE_ID_MAX 8
0036 #define CU_ID_MAX 16
0037 #define SIMD_ID_MAX 4
0038 #define WAVE_ID_MAX 10
0039
0040 enum gfx_v9_4_2_utc_type {
0041     VML2_MEM,
0042     VML2_WALKER_MEM,
0043     UTCL2_MEM,
0044     ATC_L2_CACHE_2M,
0045     ATC_L2_CACHE_32K,
0046     ATC_L2_CACHE_4K
0047 };
0048
0049 struct gfx_v9_4_2_utc_block {
0050     enum gfx_v9_4_2_utc_type type;
0051     uint32_t num_banks;
0052     uint32_t num_ways;
0053     uint32_t num_mem_blocks;
0054     struct soc15_reg idx_reg;
0055     struct soc15_reg data_reg;
0056     uint32_t sec_count_mask;
0057     uint32_t sec_count_shift;
0058     uint32_t ded_count_mask;
0059     uint32_t ded_count_shift;
0060     uint32_t clear;
0061 };
0062
0063 static const struct soc15_reg_golden golden_settings_gc_9_4_2_alde_die_0[] = {
0064     SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_0, 0x3fffffff, 0x141dc920),
0065     SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_1, 0x3fffffff, 0x3b458b93),
0066     SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_2, 0x3fffffff, 0x1a4f5583),
0067     SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_3, 0x3fffffff, 0x317717f6),
0068     SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_4, 0x3fffffff, 0x107cc1e6),
0069     SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_5, 0x3ff, 0x351),
0070 };
0071
0072 static const struct soc15_reg_golden golden_settings_gc_9_4_2_alde_die_1[] = {
0073     SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_0, 0x3fffffff, 0x2591aa38),
0074     SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_1, 0x3fffffff, 0xac9e88b),
0075     SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_2, 0x3fffffff, 0x2bc3369b),
0076     SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_3, 0x3fffffff, 0xfb74ee),
0077     SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_4, 0x3fffffff, 0x21f0a2fe),
0078     SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CHAN_STEER_5, 0x3ff, 0x49),
0079 };
0080
0081 static const struct soc15_reg_golden golden_settings_gc_9_4_2_alde[] = {
0082     SOC15_REG_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
0083     SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xfffffeef, 0x10b0000),
0084     SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_UTCL1_CNTL1, 0xffffffff, 0x30800400),
0085     SOC15_REG_GOLDEN_VALUE(GC, 0, regTCI_CNTL_3, 0xff, 0x20),
0086 };
0087
0088 /*
0089  * This shader is used to clear VGPRS and LDS, and also write the input
0090  * pattern into the write back buffer, which will be used by driver to
0091  * check whether all SIMDs have been covered.
0092 */
0093 static const u32 vgpr_init_compute_shader_aldebaran[] = {
0094     0xb8840904, 0xb8851a04, 0xb8861344, 0xb8831804, 0x9208ff06, 0x00000280,
0095     0x9209a805, 0x920a8a04, 0x81080908, 0x81080a08, 0x81080308, 0x8e078208,
0096     0x81078407, 0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8a0000, 0xd3d94000,
0097     0x18000080, 0xd3d94001, 0x18000080, 0xd3d94002, 0x18000080, 0xd3d94003,
0098     0x18000080, 0xd3d94004, 0x18000080, 0xd3d94005, 0x18000080, 0xd3d94006,
0099     0x18000080, 0xd3d94007, 0x18000080, 0xd3d94008, 0x18000080, 0xd3d94009,
0100     0x18000080, 0xd3d9400a, 0x18000080, 0xd3d9400b, 0x18000080, 0xd3d9400c,
0101     0x18000080, 0xd3d9400d, 0x18000080, 0xd3d9400e, 0x18000080, 0xd3d9400f,
0102     0x18000080, 0xd3d94010, 0x18000080, 0xd3d94011, 0x18000080, 0xd3d94012,
0103     0x18000080, 0xd3d94013, 0x18000080, 0xd3d94014, 0x18000080, 0xd3d94015,
0104     0x18000080, 0xd3d94016, 0x18000080, 0xd3d94017, 0x18000080, 0xd3d94018,
0105     0x18000080, 0xd3d94019, 0x18000080, 0xd3d9401a, 0x18000080, 0xd3d9401b,
0106     0x18000080, 0xd3d9401c, 0x18000080, 0xd3d9401d, 0x18000080, 0xd3d9401e,
0107     0x18000080, 0xd3d9401f, 0x18000080, 0xd3d94020, 0x18000080, 0xd3d94021,
0108     0x18000080, 0xd3d94022, 0x18000080, 0xd3d94023, 0x18000080, 0xd3d94024,
0109     0x18000080, 0xd3d94025, 0x18000080, 0xd3d94026, 0x18000080, 0xd3d94027,
0110     0x18000080, 0xd3d94028, 0x18000080, 0xd3d94029, 0x18000080, 0xd3d9402a,
0111     0x18000080, 0xd3d9402b, 0x18000080, 0xd3d9402c, 0x18000080, 0xd3d9402d,
0112     0x18000080, 0xd3d9402e, 0x18000080, 0xd3d9402f, 0x18000080, 0xd3d94030,
0113     0x18000080, 0xd3d94031, 0x18000080, 0xd3d94032, 0x18000080, 0xd3d94033,
0114     0x18000080, 0xd3d94034, 0x18000080, 0xd3d94035, 0x18000080, 0xd3d94036,
0115     0x18000080, 0xd3d94037, 0x18000080, 0xd3d94038, 0x18000080, 0xd3d94039,
0116     0x18000080, 0xd3d9403a, 0x18000080, 0xd3d9403b, 0x18000080, 0xd3d9403c,
0117     0x18000080, 0xd3d9403d, 0x18000080, 0xd3d9403e, 0x18000080, 0xd3d9403f,
0118     0x18000080, 0xd3d94040, 0x18000080, 0xd3d94041, 0x18000080, 0xd3d94042,
0119     0x18000080, 0xd3d94043, 0x18000080, 0xd3d94044, 0x18000080, 0xd3d94045,
0120     0x18000080, 0xd3d94046, 0x18000080, 0xd3d94047, 0x18000080, 0xd3d94048,
0121     0x18000080, 0xd3d94049, 0x18000080, 0xd3d9404a, 0x18000080, 0xd3d9404b,
0122     0x18000080, 0xd3d9404c, 0x18000080, 0xd3d9404d, 0x18000080, 0xd3d9404e,
0123     0x18000080, 0xd3d9404f, 0x18000080, 0xd3d94050, 0x18000080, 0xd3d94051,
0124     0x18000080, 0xd3d94052, 0x18000080, 0xd3d94053, 0x18000080, 0xd3d94054,
0125     0x18000080, 0xd3d94055, 0x18000080, 0xd3d94056, 0x18000080, 0xd3d94057,
0126     0x18000080, 0xd3d94058, 0x18000080, 0xd3d94059, 0x18000080, 0xd3d9405a,
0127     0x18000080, 0xd3d9405b, 0x18000080, 0xd3d9405c, 0x18000080, 0xd3d9405d,
0128     0x18000080, 0xd3d9405e, 0x18000080, 0xd3d9405f, 0x18000080, 0xd3d94060,
0129     0x18000080, 0xd3d94061, 0x18000080, 0xd3d94062, 0x18000080, 0xd3d94063,
0130     0x18000080, 0xd3d94064, 0x18000080, 0xd3d94065, 0x18000080, 0xd3d94066,
0131     0x18000080, 0xd3d94067, 0x18000080, 0xd3d94068, 0x18000080, 0xd3d94069,
0132     0x18000080, 0xd3d9406a, 0x18000080, 0xd3d9406b, 0x18000080, 0xd3d9406c,
0133     0x18000080, 0xd3d9406d, 0x18000080, 0xd3d9406e, 0x18000080, 0xd3d9406f,
0134     0x18000080, 0xd3d94070, 0x18000080, 0xd3d94071, 0x18000080, 0xd3d94072,
0135     0x18000080, 0xd3d94073, 0x18000080, 0xd3d94074, 0x18000080, 0xd3d94075,
0136     0x18000080, 0xd3d94076, 0x18000080, 0xd3d94077, 0x18000080, 0xd3d94078,
0137     0x18000080, 0xd3d94079, 0x18000080, 0xd3d9407a, 0x18000080, 0xd3d9407b,
0138     0x18000080, 0xd3d9407c, 0x18000080, 0xd3d9407d, 0x18000080, 0xd3d9407e,
0139     0x18000080, 0xd3d9407f, 0x18000080, 0xd3d94080, 0x18000080, 0xd3d94081,
0140     0x18000080, 0xd3d94082, 0x18000080, 0xd3d94083, 0x18000080, 0xd3d94084,
0141     0x18000080, 0xd3d94085, 0x18000080, 0xd3d94086, 0x18000080, 0xd3d94087,
0142     0x18000080, 0xd3d94088, 0x18000080, 0xd3d94089, 0x18000080, 0xd3d9408a,
0143     0x18000080, 0xd3d9408b, 0x18000080, 0xd3d9408c, 0x18000080, 0xd3d9408d,
0144     0x18000080, 0xd3d9408e, 0x18000080, 0xd3d9408f, 0x18000080, 0xd3d94090,
0145     0x18000080, 0xd3d94091, 0x18000080, 0xd3d94092, 0x18000080, 0xd3d94093,
0146     0x18000080, 0xd3d94094, 0x18000080, 0xd3d94095, 0x18000080, 0xd3d94096,
0147     0x18000080, 0xd3d94097, 0x18000080, 0xd3d94098, 0x18000080, 0xd3d94099,
0148     0x18000080, 0xd3d9409a, 0x18000080, 0xd3d9409b, 0x18000080, 0xd3d9409c,
0149     0x18000080, 0xd3d9409d, 0x18000080, 0xd3d9409e, 0x18000080, 0xd3d9409f,
0150     0x18000080, 0xd3d940a0, 0x18000080, 0xd3d940a1, 0x18000080, 0xd3d940a2,
0151     0x18000080, 0xd3d940a3, 0x18000080, 0xd3d940a4, 0x18000080, 0xd3d940a5,
0152     0x18000080, 0xd3d940a6, 0x18000080, 0xd3d940a7, 0x18000080, 0xd3d940a8,
0153     0x18000080, 0xd3d940a9, 0x18000080, 0xd3d940aa, 0x18000080, 0xd3d940ab,
0154     0x18000080, 0xd3d940ac, 0x18000080, 0xd3d940ad, 0x18000080, 0xd3d940ae,
0155     0x18000080, 0xd3d940af, 0x18000080, 0xd3d940b0, 0x18000080, 0xd3d940b1,
0156     0x18000080, 0xd3d940b2, 0x18000080, 0xd3d940b3, 0x18000080, 0xd3d940b4,
0157     0x18000080, 0xd3d940b5, 0x18000080, 0xd3d940b6, 0x18000080, 0xd3d940b7,
0158     0x18000080, 0xd3d940b8, 0x18000080, 0xd3d940b9, 0x18000080, 0xd3d940ba,
0159     0x18000080, 0xd3d940bb, 0x18000080, 0xd3d940bc, 0x18000080, 0xd3d940bd,
0160     0x18000080, 0xd3d940be, 0x18000080, 0xd3d940bf, 0x18000080, 0xd3d940c0,
0161     0x18000080, 0xd3d940c1, 0x18000080, 0xd3d940c2, 0x18000080, 0xd3d940c3,
0162     0x18000080, 0xd3d940c4, 0x18000080, 0xd3d940c5, 0x18000080, 0xd3d940c6,
0163     0x18000080, 0xd3d940c7, 0x18000080, 0xd3d940c8, 0x18000080, 0xd3d940c9,
0164     0x18000080, 0xd3d940ca, 0x18000080, 0xd3d940cb, 0x18000080, 0xd3d940cc,
0165     0x18000080, 0xd3d940cd, 0x18000080, 0xd3d940ce, 0x18000080, 0xd3d940cf,
0166     0x18000080, 0xd3d940d0, 0x18000080, 0xd3d940d1, 0x18000080, 0xd3d940d2,
0167     0x18000080, 0xd3d940d3, 0x18000080, 0xd3d940d4, 0x18000080, 0xd3d940d5,
0168     0x18000080, 0xd3d940d6, 0x18000080, 0xd3d940d7, 0x18000080, 0xd3d940d8,
0169     0x18000080, 0xd3d940d9, 0x18000080, 0xd3d940da, 0x18000080, 0xd3d940db,
0170     0x18000080, 0xd3d940dc, 0x18000080, 0xd3d940dd, 0x18000080, 0xd3d940de,
0171     0x18000080, 0xd3d940df, 0x18000080, 0xd3d940e0, 0x18000080, 0xd3d940e1,
0172     0x18000080, 0xd3d940e2, 0x18000080, 0xd3d940e3, 0x18000080, 0xd3d940e4,
0173     0x18000080, 0xd3d940e5, 0x18000080, 0xd3d940e6, 0x18000080, 0xd3d940e7,
0174     0x18000080, 0xd3d940e8, 0x18000080, 0xd3d940e9, 0x18000080, 0xd3d940ea,
0175     0x18000080, 0xd3d940eb, 0x18000080, 0xd3d940ec, 0x18000080, 0xd3d940ed,
0176     0x18000080, 0xd3d940ee, 0x18000080, 0xd3d940ef, 0x18000080, 0xd3d940f0,
0177     0x18000080, 0xd3d940f1, 0x18000080, 0xd3d940f2, 0x18000080, 0xd3d940f3,
0178     0x18000080, 0xd3d940f4, 0x18000080, 0xd3d940f5, 0x18000080, 0xd3d940f6,
0179     0x18000080, 0xd3d940f7, 0x18000080, 0xd3d940f8, 0x18000080, 0xd3d940f9,
0180     0x18000080, 0xd3d940fa, 0x18000080, 0xd3d940fb, 0x18000080, 0xd3d940fc,
0181     0x18000080, 0xd3d940fd, 0x18000080, 0xd3d940fe, 0x18000080, 0xd3d940ff,
0182     0x18000080, 0xb07c0000, 0xbe8a00ff, 0x000000f8, 0xbf11080a, 0x7e000280,
0183     0x7e020280, 0x7e040280, 0x7e060280, 0x7e080280, 0x7e0a0280, 0x7e0c0280,
0184     0x7e0e0280, 0x808a880a, 0xbe80320a, 0xbf84fff5, 0xbf9c0000, 0xd28c0001,
0185     0x0001007f, 0xd28d0001, 0x0002027e, 0x10020288, 0xbe8b0004, 0xb78b4000,
0186     0xd1196a01, 0x00001701, 0xbe8a0087, 0xbefc00c1, 0xd89c4000, 0x00020201,
0187     0xd89cc080, 0x00040401, 0x320202ff, 0x00000800, 0x808a810a, 0xbf84fff8,
0188     0xbf810000,
0189 };
0190
0191 const struct soc15_reg_entry vgpr_init_regs_aldebaran[] = {
0192     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
0193     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_X), 0x40 },
0194     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Y), 4 },
0195     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Z), 1 },
0196     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC1), 0xbf },
0197     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC2), 0x400006 },  /* 64KB LDS */
0198     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC3), 0x3F }, /*  63 - accum-offset = 256 */
0199     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff },
0200     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
0201     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
0202     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
0203     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff },
0204     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff },
0205     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff },
0206     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff },
0207 };
0208
0209 /*
0210  * The below shaders are used to clear SGPRS, and also write the input
0211  * pattern into the write back buffer. The first two dispatch should be
0212  * scheduled simultaneously which make sure that all SGPRS could be
0213  * allocated, so the dispatch 1 need check write back buffer before scheduled,
0214  * make sure that waves of dispatch 0 are all dispacthed to all simds
0215  * balanced. both dispatch 0 and dispatch 1 should be halted until all waves
0216  * are dispatched, and then driver write a pattern to the shared memory to make
0217  * all waves continue.
0218 */
0219 static const u32 sgpr112_init_compute_shader_aldebaran[] = {
0220     0xb8840904, 0xb8851a04, 0xb8861344, 0xb8831804, 0x9208ff06, 0x00000280,
0221     0x9209a805, 0x920a8a04, 0x81080908, 0x81080a08, 0x81080308, 0x8e078208,
0222     0x81078407, 0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8e003f, 0xc0030200,
0223     0x00000000, 0xbf8c0000, 0xbf06ff08, 0xdeadbeaf, 0xbf84fff9, 0x81028102,
0224     0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8a0000, 0xbefc0080, 0xbeea0080,
0225     0xbeeb0080, 0xbf00f280, 0xbee60080, 0xbee70080, 0xbee80080, 0xbee90080,
0226     0xbefe0080, 0xbeff0080, 0xbe880080, 0xbe890080, 0xbe8a0080, 0xbe8b0080,
0227     0xbe8c0080, 0xbe8d0080, 0xbe8e0080, 0xbe8f0080, 0xbe900080, 0xbe910080,
0228     0xbe920080, 0xbe930080, 0xbe940080, 0xbe950080, 0xbe960080, 0xbe970080,
0229     0xbe980080, 0xbe990080, 0xbe9a0080, 0xbe9b0080, 0xbe9c0080, 0xbe9d0080,
0230     0xbe9e0080, 0xbe9f0080, 0xbea00080, 0xbea10080, 0xbea20080, 0xbea30080,
0231     0xbea40080, 0xbea50080, 0xbea60080, 0xbea70080, 0xbea80080, 0xbea90080,
0232     0xbeaa0080, 0xbeab0080, 0xbeac0080, 0xbead0080, 0xbeae0080, 0xbeaf0080,
0233     0xbeb00080, 0xbeb10080, 0xbeb20080, 0xbeb30080, 0xbeb40080, 0xbeb50080,
0234     0xbeb60080, 0xbeb70080, 0xbeb80080, 0xbeb90080, 0xbeba0080, 0xbebb0080,
0235     0xbebc0080, 0xbebd0080, 0xbebe0080, 0xbebf0080, 0xbec00080, 0xbec10080,
0236     0xbec20080, 0xbec30080, 0xbec40080, 0xbec50080, 0xbec60080, 0xbec70080,
0237     0xbec80080, 0xbec90080, 0xbeca0080, 0xbecb0080, 0xbecc0080, 0xbecd0080,
0238     0xbece0080, 0xbecf0080, 0xbed00080, 0xbed10080, 0xbed20080, 0xbed30080,
0239     0xbed40080, 0xbed50080, 0xbed60080, 0xbed70080, 0xbed80080, 0xbed90080,
0240     0xbeda0080, 0xbedb0080, 0xbedc0080, 0xbedd0080, 0xbede0080, 0xbedf0080,
0241     0xbee00080, 0xbee10080, 0xbee20080, 0xbee30080, 0xbee40080, 0xbee50080,
0242     0xbf810000
0243 };
0244
0245 const struct soc15_reg_entry sgpr112_init_regs_aldebaran[] = {
0246     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
0247     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_X), 0x40 },
0248     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Y), 8 },
0249     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Z), 1 },
0250     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC1), 0x340 },
0251     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC2), 0x6 },
0252     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC3), 0x0 },
0253     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff },
0254     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
0255     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
0256     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
0257     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff },
0258     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff },
0259     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff },
0260     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff },
0261 };
0262
0263 static const u32 sgpr96_init_compute_shader_aldebaran[] = {
0264     0xb8840904, 0xb8851a04, 0xb8861344, 0xb8831804, 0x9208ff06, 0x00000280,
0265     0x9209a805, 0x920a8a04, 0x81080908, 0x81080a08, 0x81080308, 0x8e078208,
0266     0x81078407, 0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8e003f, 0xc0030200,
0267     0x00000000, 0xbf8c0000, 0xbf06ff08, 0xdeadbeaf, 0xbf84fff9, 0x81028102,
0268     0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8a0000, 0xbefc0080, 0xbeea0080,
0269     0xbeeb0080, 0xbf00f280, 0xbee60080, 0xbee70080, 0xbee80080, 0xbee90080,
0270     0xbefe0080, 0xbeff0080, 0xbe880080, 0xbe890080, 0xbe8a0080, 0xbe8b0080,
0271     0xbe8c0080, 0xbe8d0080, 0xbe8e0080, 0xbe8f0080, 0xbe900080, 0xbe910080,
0272     0xbe920080, 0xbe930080, 0xbe940080, 0xbe950080, 0xbe960080, 0xbe970080,
0273     0xbe980080, 0xbe990080, 0xbe9a0080, 0xbe9b0080, 0xbe9c0080, 0xbe9d0080,
0274     0xbe9e0080, 0xbe9f0080, 0xbea00080, 0xbea10080, 0xbea20080, 0xbea30080,
0275     0xbea40080, 0xbea50080, 0xbea60080, 0xbea70080, 0xbea80080, 0xbea90080,
0276     0xbeaa0080, 0xbeab0080, 0xbeac0080, 0xbead0080, 0xbeae0080, 0xbeaf0080,
0277     0xbeb00080, 0xbeb10080, 0xbeb20080, 0xbeb30080, 0xbeb40080, 0xbeb50080,
0278     0xbeb60080, 0xbeb70080, 0xbeb80080, 0xbeb90080, 0xbeba0080, 0xbebb0080,
0279     0xbebc0080, 0xbebd0080, 0xbebe0080, 0xbebf0080, 0xbec00080, 0xbec10080,
0280     0xbec20080, 0xbec30080, 0xbec40080, 0xbec50080, 0xbec60080, 0xbec70080,
0281     0xbec80080, 0xbec90080, 0xbeca0080, 0xbecb0080, 0xbecc0080, 0xbecd0080,
0282     0xbece0080, 0xbecf0080, 0xbed00080, 0xbed10080, 0xbed20080, 0xbed30080,
0283     0xbed40080, 0xbed50080, 0xbed60080, 0xbed70080, 0xbed80080, 0xbed90080,
0284     0xbf810000,
0285 };
0286
0287 const struct soc15_reg_entry sgpr96_init_regs_aldebaran[] = {
0288     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
0289     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_X), 0x40 },
0290     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Y), 0xc },
0291     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Z), 1 },
0292     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC1), 0x2c0 },
0293     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC2), 0x6 },
0294     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC3), 0x0 },
0295     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff },
0296     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
0297     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
0298     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
0299     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff },
0300     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff },
0301     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff },
0302     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff },
0303 };
0304
0305 /*
0306  * This shader is used to clear the uninitiated sgprs after the above
0307  * two dispatches, because of hardware feature, dispath 0 couldn't clear
0308  * top hole sgprs. Therefore need 4 waves per SIMD to cover these sgprs
0309 */
0310 static const u32 sgpr64_init_compute_shader_aldebaran[] = {
0311     0xb8840904, 0xb8851a04, 0xb8861344, 0xb8831804, 0x9208ff06, 0x00000280,
0312     0x9209a805, 0x920a8a04, 0x81080908, 0x81080a08, 0x81080308, 0x8e078208,
0313     0x81078407, 0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8e003f, 0xc0030200,
0314     0x00000000, 0xbf8c0000, 0xbf06ff08, 0xdeadbeaf, 0xbf84fff9, 0x81028102,
0315     0xc0410080, 0x00000007, 0xbf8c0000, 0xbf8a0000, 0xbefc0080, 0xbeea0080,
0316     0xbeeb0080, 0xbf00f280, 0xbee60080, 0xbee70080, 0xbee80080, 0xbee90080,
0317     0xbefe0080, 0xbeff0080, 0xbe880080, 0xbe890080, 0xbe8a0080, 0xbe8b0080,
0318     0xbe8c0080, 0xbe8d0080, 0xbe8e0080, 0xbe8f0080, 0xbe900080, 0xbe910080,
0319     0xbe920080, 0xbe930080, 0xbe940080, 0xbe950080, 0xbe960080, 0xbe970080,
0320     0xbe980080, 0xbe990080, 0xbe9a0080, 0xbe9b0080, 0xbe9c0080, 0xbe9d0080,
0321     0xbe9e0080, 0xbe9f0080, 0xbea00080, 0xbea10080, 0xbea20080, 0xbea30080,
0322     0xbea40080, 0xbea50080, 0xbea60080, 0xbea70080, 0xbea80080, 0xbea90080,
0323     0xbeaa0080, 0xbeab0080, 0xbeac0080, 0xbead0080, 0xbeae0080, 0xbeaf0080,
0324     0xbeb00080, 0xbeb10080, 0xbeb20080, 0xbeb30080, 0xbeb40080, 0xbeb50080,
0325     0xbeb60080, 0xbeb70080, 0xbeb80080, 0xbeb90080, 0xbf810000,
0326 };
0327
0328 const struct soc15_reg_entry sgpr64_init_regs_aldebaran[] = {
0329     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_RESOURCE_LIMITS), 0x0000000 },
0330     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_X), 0x40 },
0331     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Y), 0x10 },
0332     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_NUM_THREAD_Z), 1 },
0333     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC1), 0x1c0 },
0334     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC2), 0x6 },
0335     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_PGM_RSRC3), 0x0 },
0336     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE0), 0xffffffff },
0337     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE1), 0xffffffff },
0338     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE2), 0xffffffff },
0339     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE3), 0xffffffff },
0340     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE4), 0xffffffff },
0341     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE5), 0xffffffff },
0342     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE6), 0xffffffff },
0343     { SOC15_REG_ENTRY(GC, 0, regCOMPUTE_STATIC_THREAD_MGMT_SE7), 0xffffffff },
0344 };
0345
0346 static int gfx_v9_4_2_run_shader(struct amdgpu_device *adev,
0347                  struct amdgpu_ring *ring,
0348                  struct amdgpu_ib *ib,
0349                  const u32 *shader_ptr, u32 shader_size,
0350                  const struct soc15_reg_entry *init_regs, u32 regs_size,
0351                  u32 compute_dim_x, u64 wb_gpu_addr, u32 pattern,
0352                  struct dma_fence **fence_ptr)
0353 {
0354     int r, i;
0355     uint32_t total_size, shader_offset;
0356     u64 gpu_addr;
0357
0358     total_size = (regs_size * 3 + 4 + 5 + 5) * 4;
0359     total_size = ALIGN(total_size, 256);
0360     shader_offset = total_size;
0361     total_size += ALIGN(shader_size, 256);
0362
0363     /* allocate an indirect buffer to put the commands in */
0364     memset(ib, 0, sizeof(*ib));
0365     r = amdgpu_ib_get(adev, NULL, total_size,
0366                     AMDGPU_IB_POOL_DIRECT, ib);
0367     if (r) {
0368         dev_err(adev->dev, "failed to get ib (%d).\n", r);
0369         return r;
0370     }
0371
0372     /* load the compute shaders */
0373     for (i = 0; i < shader_size/sizeof(u32); i++)
0374         ib->ptr[i + (shader_offset / 4)] = shader_ptr[i];
0375
0376     /* init the ib length to 0 */
0377     ib->length_dw = 0;
0378
0379     /* write the register state for the compute dispatch */
0380     for (i = 0; i < regs_size; i++) {
0381         ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
0382         ib->ptr[ib->length_dw++] = SOC15_REG_ENTRY_OFFSET(init_regs[i])
0383                                 - PACKET3_SET_SH_REG_START;
0384         ib->ptr[ib->length_dw++] = init_regs[i].reg_value;
0385     }
0386
0387     /* write the shader start address: mmCOMPUTE_PGM_LO, mmCOMPUTE_PGM_HI */
0388     gpu_addr = (ib->gpu_addr + (u64)shader_offset) >> 8;
0389     ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2);
0390     ib->ptr[ib->length_dw++] = SOC15_REG_OFFSET(GC, 0, regCOMPUTE_PGM_LO)
0391                             - PACKET3_SET_SH_REG_START;
0392     ib->ptr[ib->length_dw++] = lower_32_bits(gpu_addr);
0393     ib->ptr[ib->length_dw++] = upper_32_bits(gpu_addr);
0394
0395     /* write the wb buffer address */
0396     ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 3);
0397     ib->ptr[ib->length_dw++] = SOC15_REG_OFFSET(GC, 0, regCOMPUTE_USER_DATA_0)
0398                             - PACKET3_SET_SH_REG_START;
0399     ib->ptr[ib->length_dw++] = lower_32_bits(wb_gpu_addr);
0400     ib->ptr[ib->length_dw++] = upper_32_bits(wb_gpu_addr);
0401     ib->ptr[ib->length_dw++] = pattern;
0402
0403     /* write dispatch packet */
0404     ib->ptr[ib->length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3);
0405     ib->ptr[ib->length_dw++] = compute_dim_x; /* x */
0406     ib->ptr[ib->length_dw++] = 1; /* y */
0407     ib->ptr[ib->length_dw++] = 1; /* z */
0408     ib->ptr[ib->length_dw++] =
0409         REG_SET_FIELD(0, COMPUTE_DISPATCH_INITIATOR, COMPUTE_SHADER_EN, 1);
0410
0411     /* shedule the ib on the ring */
0412     r = amdgpu_ib_schedule(ring, 1, ib, NULL, fence_ptr);
0413     if (r) {
0414         dev_err(adev->dev, "ib submit failed (%d).\n", r);
0415         amdgpu_ib_free(adev, ib, NULL);
0416     }
0417     return r;
0418 }
0419
0420 static void gfx_v9_4_2_log_wave_assignment(struct amdgpu_device *adev, uint32_t *wb_ptr)
0421 {
0422     uint32_t se, cu, simd, wave;
0423     uint32_t offset = 0;
0424     char *str;
0425     int size;
0426
0427     str = kmalloc(256, GFP_KERNEL);
0428     if (!str)
0429         return;
0430
0431     dev_dbg(adev->dev, "wave assignment:\n");
0432
0433     for (se = 0; se < adev->gfx.config.max_shader_engines; se++) {
0434         for (cu = 0; cu < CU_ID_MAX; cu++) {
0435             memset(str, 0, 256);
0436             size = sprintf(str, "SE[%02d]CU[%02d]: ", se, cu);
0437             for (simd = 0; simd < SIMD_ID_MAX; simd++) {
0438                 size += sprintf(str + size, "[");
0439                 for (wave = 0; wave < WAVE_ID_MAX; wave++) {
0440                     size += sprintf(str + size, "%x", wb_ptr[offset]);
0441                     offset++;
0442                 }
0443                 size += sprintf(str + size, "]  ");
0444             }
0445             dev_dbg(adev->dev, "%s\n", str);
0446         }
0447     }
0448
0449     kfree(str);
0450 }
0451
0452 static int gfx_v9_4_2_wait_for_waves_assigned(struct amdgpu_device *adev,
0453                           uint32_t *wb_ptr, uint32_t mask,
0454                           uint32_t pattern, uint32_t num_wave, bool wait)
0455 {
0456     uint32_t se, cu, simd, wave;
0457     uint32_t loop = 0;
0458     uint32_t wave_cnt;
0459     uint32_t offset;
0460
0461     do {
0462         wave_cnt = 0;
0463         offset = 0;
0464
0465         for (se = 0; se < adev->gfx.config.max_shader_engines; se++)
0466             for (cu = 0; cu < CU_ID_MAX; cu++)
0467                 for (simd = 0; simd < SIMD_ID_MAX; simd++)
0468                     for (wave = 0; wave < WAVE_ID_MAX; wave++) {
0469                         if (((1 << wave) & mask) &&
0470                             (wb_ptr[offset] == pattern))
0471                             wave_cnt++;
0472
0473                         offset++;
0474                     }
0475
0476         if (wave_cnt == num_wave)
0477             return 0;
0478
0479         mdelay(1);
0480     } while (++loop < 2000 && wait);
0481
0482     dev_err(adev->dev, "actual wave num: %d, expected wave num: %d\n",
0483         wave_cnt, num_wave);
0484
0485     gfx_v9_4_2_log_wave_assignment(adev, wb_ptr);
0486
0487     return -EBADSLT;
0488 }
0489
0490 static int gfx_v9_4_2_do_sgprs_init(struct amdgpu_device *adev)
0491 {
0492     int r;
0493     int wb_size = adev->gfx.config.max_shader_engines *
0494              CU_ID_MAX * SIMD_ID_MAX * WAVE_ID_MAX;
0495     struct amdgpu_ib wb_ib;
0496     struct amdgpu_ib disp_ibs[3];
0497     struct dma_fence *fences[3];
0498     u32 pattern[3] = { 0x1, 0x5, 0xa };
0499
0500     /* bail if the compute ring is not ready */
0501     if (!adev->gfx.compute_ring[0].sched.ready ||
0502          !adev->gfx.compute_ring[1].sched.ready)
0503         return 0;
0504
0505     /* allocate the write-back buffer from IB */
0506     memset(&wb_ib, 0, sizeof(wb_ib));
0507     r = amdgpu_ib_get(adev, NULL, (1 + wb_size) * sizeof(uint32_t),
0508               AMDGPU_IB_POOL_DIRECT, &wb_ib);
0509     if (r) {
0510         dev_err(adev->dev, "failed to get ib (%d) for wb\n", r);
0511         return r;
0512     }
0513     memset(wb_ib.ptr, 0, (1 + wb_size) * sizeof(uint32_t));
0514
0515     r = gfx_v9_4_2_run_shader(adev,
0516             &adev->gfx.compute_ring[0],
0517             &disp_ibs[0],
0518             sgpr112_init_compute_shader_aldebaran,
0519             sizeof(sgpr112_init_compute_shader_aldebaran),
0520             sgpr112_init_regs_aldebaran,
0521             ARRAY_SIZE(sgpr112_init_regs_aldebaran),
0522             adev->gfx.cu_info.number,
0523             wb_ib.gpu_addr, pattern[0], &fences[0]);
0524     if (r) {
0525         dev_err(adev->dev, "failed to clear first 224 sgprs\n");
0526         goto pro_end;
0527     }
0528
0529     r = gfx_v9_4_2_wait_for_waves_assigned(adev,
0530             &wb_ib.ptr[1], 0b11,
0531             pattern[0],
0532             adev->gfx.cu_info.number * SIMD_ID_MAX * 2,
0533             true);
0534     if (r) {
0535         dev_err(adev->dev, "wave coverage failed when clear first 224 sgprs\n");
0536         wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */
0537         goto disp0_failed;
0538     }
0539
0540     r = gfx_v9_4_2_run_shader(adev,
0541             &adev->gfx.compute_ring[1],
0542             &disp_ibs[1],
0543             sgpr96_init_compute_shader_aldebaran,
0544             sizeof(sgpr96_init_compute_shader_aldebaran),
0545             sgpr96_init_regs_aldebaran,
0546             ARRAY_SIZE(sgpr96_init_regs_aldebaran),
0547             adev->gfx.cu_info.number * 2,
0548             wb_ib.gpu_addr, pattern[1], &fences[1]);
0549     if (r) {
0550         dev_err(adev->dev, "failed to clear next 576 sgprs\n");
0551         goto disp0_failed;
0552     }
0553
0554     r = gfx_v9_4_2_wait_for_waves_assigned(adev,
0555             &wb_ib.ptr[1], 0b11111100,
0556             pattern[1], adev->gfx.cu_info.number * SIMD_ID_MAX * 6,
0557             true);
0558     if (r) {
0559         dev_err(adev->dev, "wave coverage failed when clear first 576 sgprs\n");
0560         wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */
0561         goto disp1_failed;
0562     }
0563
0564     wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */
0565
0566     /* wait for the GPU to finish processing the IB */
0567     r = dma_fence_wait(fences[0], false);
0568     if (r) {
0569         dev_err(adev->dev, "timeout to clear first 224 sgprs\n");
0570         goto disp1_failed;
0571     }
0572
0573     r = dma_fence_wait(fences[1], false);
0574     if (r) {
0575         dev_err(adev->dev, "timeout to clear first 576 sgprs\n");
0576         goto disp1_failed;
0577     }
0578
0579     memset(wb_ib.ptr, 0, (1 + wb_size) * sizeof(uint32_t));
0580     r = gfx_v9_4_2_run_shader(adev,
0581             &adev->gfx.compute_ring[0],
0582             &disp_ibs[2],
0583             sgpr64_init_compute_shader_aldebaran,
0584             sizeof(sgpr64_init_compute_shader_aldebaran),
0585             sgpr64_init_regs_aldebaran,
0586             ARRAY_SIZE(sgpr64_init_regs_aldebaran),
0587             adev->gfx.cu_info.number,
0588             wb_ib.gpu_addr, pattern[2], &fences[2]);
0589     if (r) {
0590         dev_err(adev->dev, "failed to clear first 256 sgprs\n");
0591         goto disp1_failed;
0592     }
0593
0594     r = gfx_v9_4_2_wait_for_waves_assigned(adev,
0595             &wb_ib.ptr[1], 0b1111,
0596             pattern[2],
0597             adev->gfx.cu_info.number * SIMD_ID_MAX * 4,
0598             true);
0599     if (r) {
0600         dev_err(adev->dev, "wave coverage failed when clear first 256 sgprs\n");
0601         wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */
0602         goto disp2_failed;
0603     }
0604
0605     wb_ib.ptr[0] = 0xdeadbeaf; /* stop waves */
0606
0607     r = dma_fence_wait(fences[2], false);
0608     if (r) {
0609         dev_err(adev->dev, "timeout to clear first 256 sgprs\n");
0610         goto disp2_failed;
0611     }
0612
0613 disp2_failed:
0614     amdgpu_ib_free(adev, &disp_ibs[2], NULL);
0615     dma_fence_put(fences[2]);
0616 disp1_failed:
0617     amdgpu_ib_free(adev, &disp_ibs[1], NULL);
0618     dma_fence_put(fences[1]);
0619 disp0_failed:
0620     amdgpu_ib_free(adev, &disp_ibs[0], NULL);
0621     dma_fence_put(fences[0]);
0622 pro_end:
0623     amdgpu_ib_free(adev, &wb_ib, NULL);
0624
0625     if (r)
0626         dev_info(adev->dev, "Init SGPRS Failed\n");
0627     else
0628         dev_info(adev->dev, "Init SGPRS Successfully\n");
0629
0630     return r;
0631 }
0632
0633 static int gfx_v9_4_2_do_vgprs_init(struct amdgpu_device *adev)
0634 {
0635     int r;
0636     /* CU_ID: 0~15, SIMD_ID: 0~3, WAVE_ID: 0 ~ 9 */
0637     int wb_size = adev->gfx.config.max_shader_engines *
0638              CU_ID_MAX * SIMD_ID_MAX * WAVE_ID_MAX;
0639     struct amdgpu_ib wb_ib;
0640     struct amdgpu_ib disp_ib;
0641     struct dma_fence *fence;
0642     u32 pattern = 0xa;
0643
0644     /* bail if the compute ring is not ready */
0645     if (!adev->gfx.compute_ring[0].sched.ready)
0646         return 0;
0647
0648     /* allocate the write-back buffer from IB */
0649     memset(&wb_ib, 0, sizeof(wb_ib));
0650     r = amdgpu_ib_get(adev, NULL, (1 + wb_size) * sizeof(uint32_t),
0651               AMDGPU_IB_POOL_DIRECT, &wb_ib);
0652     if (r) {
0653         dev_err(adev->dev, "failed to get ib (%d) for wb.\n", r);
0654         return r;
0655     }
0656     memset(wb_ib.ptr, 0, (1 + wb_size) * sizeof(uint32_t));
0657
0658     r = gfx_v9_4_2_run_shader(adev,
0659             &adev->gfx.compute_ring[0],
0660             &disp_ib,
0661             vgpr_init_compute_shader_aldebaran,
0662             sizeof(vgpr_init_compute_shader_aldebaran),
0663             vgpr_init_regs_aldebaran,
0664             ARRAY_SIZE(vgpr_init_regs_aldebaran),
0665             adev->gfx.cu_info.number,
0666             wb_ib.gpu_addr, pattern, &fence);
0667     if (r) {
0668         dev_err(adev->dev, "failed to clear vgprs\n");
0669         goto pro_end;
0670     }
0671
0672     /* wait for the GPU to finish processing the IB */
0673     r = dma_fence_wait(fence, false);
0674     if (r) {
0675         dev_err(adev->dev, "timeout to clear vgprs\n");
0676         goto disp_failed;
0677     }
0678
0679     r = gfx_v9_4_2_wait_for_waves_assigned(adev,
0680             &wb_ib.ptr[1], 0b1,
0681             pattern,
0682             adev->gfx.cu_info.number * SIMD_ID_MAX,
0683             false);
0684     if (r) {
0685         dev_err(adev->dev, "failed to cover all simds when clearing vgprs\n");
0686         goto disp_failed;
0687     }
0688
0689 disp_failed:
0690     amdgpu_ib_free(adev, &disp_ib, NULL);
0691     dma_fence_put(fence);
0692 pro_end:
0693     amdgpu_ib_free(adev, &wb_ib, NULL);
0694
0695     if (r)
0696         dev_info(adev->dev, "Init VGPRS Failed\n");
0697     else
0698         dev_info(adev->dev, "Init VGPRS Successfully\n");
0699
0700     return r;
0701 }
0702
0703 int gfx_v9_4_2_do_edc_gpr_workarounds(struct amdgpu_device *adev)
0704 {
0705     /* only support when RAS is enabled */
0706     if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
0707         return 0;
0708
0709     /* Workaround for ALDEBARAN, skip GPRs init in GPU reset.
0710        Will remove it once GPRs init algorithm works for all CU settings. */
0711     if (amdgpu_in_reset(adev))
0712         return 0;
0713
0714     gfx_v9_4_2_do_sgprs_init(adev);
0715
0716     gfx_v9_4_2_do_vgprs_init(adev);
0717
0718     return 0;
0719 }
0720
0721 static void gfx_v9_4_2_query_sq_timeout_status(struct amdgpu_device *adev);
0722 static void gfx_v9_4_2_reset_sq_timeout_status(struct amdgpu_device *adev);
0723
0724 void gfx_v9_4_2_init_golden_registers(struct amdgpu_device *adev,
0725                       uint32_t die_id)
0726 {
0727     soc15_program_register_sequence(adev,
0728                     golden_settings_gc_9_4_2_alde,
0729                     ARRAY_SIZE(golden_settings_gc_9_4_2_alde));
0730
0731     /* apply golden settings per die */
0732     switch (die_id) {
0733     case 0:
0734         soc15_program_register_sequence(adev,
0735                 golden_settings_gc_9_4_2_alde_die_0,
0736                 ARRAY_SIZE(golden_settings_gc_9_4_2_alde_die_0));
0737         break;
0738     case 1:
0739         soc15_program_register_sequence(adev,
0740                 golden_settings_gc_9_4_2_alde_die_1,
0741                 ARRAY_SIZE(golden_settings_gc_9_4_2_alde_die_1));
0742         break;
0743     default:
0744         dev_warn(adev->dev,
0745              "invalid die id %d, ignore channel fabricid remap settings\n",
0746              die_id);
0747         break;
0748     }
0749
0750     return;
0751 }
0752
0753 void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev,
0754                 uint32_t first_vmid,
0755                 uint32_t last_vmid)
0756 {
0757     uint32_t data;
0758     int i;
0759
0760     mutex_lock(&adev->srbm_mutex);
0761
0762     for (i = first_vmid; i < last_vmid; i++) {
0763         data = 0;
0764         soc15_grbm_select(adev, 0, 0, 0, i);
0765         data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
0766         data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0);
0767         data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE,
0768                     0);
0769         WREG32(SOC15_REG_OFFSET(GC, 0, regSPI_GDBG_PER_VMID_CNTL), data);
0770     }
0771
0772     soc15_grbm_select(adev, 0, 0, 0, 0);
0773     mutex_unlock(&adev->srbm_mutex);
0774 }
0775
0776 void gfx_v9_4_2_set_power_brake_sequence(struct amdgpu_device *adev)
0777 {
0778     u32 tmp;
0779
0780     gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
0781
0782     tmp = 0;
0783     tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL, PATTERN_MODE, 1);
0784     WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL, tmp);
0785
0786     tmp = 0;
0787     tmp = REG_SET_FIELD(tmp, GC_THROTTLE_CTRL1, PWRBRK_STALL_EN, 1);
0788     WREG32_SOC15(GC, 0, regGC_THROTTLE_CTRL1, tmp);
0789
0790     WREG32_SOC15(GC, 0, regGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
0791     tmp = 0;
0792     tmp = REG_SET_FIELD(tmp, PWRBRK_STALL_PATTERN_CTRL, PWRBRK_END_STEP, 0x12);
0793     WREG32_SOC15(GC, 0, regGC_CAC_IND_DATA, tmp);
0794 }
0795
0796 static const struct soc15_reg_entry gfx_v9_4_2_edc_counter_regs[] = {
0797     /* CPF */
0798     { SOC15_REG_ENTRY(GC, 0, regCPF_EDC_ROQ_CNT), 0, 1, 1 },
0799     { SOC15_REG_ENTRY(GC, 0, regCPF_EDC_TAG_CNT), 0, 1, 1 },
0800     /* CPC */
0801     { SOC15_REG_ENTRY(GC, 0, regCPC_EDC_SCRATCH_CNT), 0, 1, 1 },
0802     { SOC15_REG_ENTRY(GC, 0, regCPC_EDC_UCODE_CNT), 0, 1, 1 },
0803     { SOC15_REG_ENTRY(GC, 0, regDC_EDC_STATE_CNT), 0, 1, 1 },
0804     { SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT), 0, 1, 1 },
0805     { SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT), 0, 1, 1 },
0806     /* GDS */
0807     { SOC15_REG_ENTRY(GC, 0, regGDS_EDC_CNT), 0, 1, 1 },
0808     { SOC15_REG_ENTRY(GC, 0, regGDS_EDC_GRBM_CNT), 0, 1, 1 },
0809     { SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 1, 1 },
0810     { SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PHY_CNT), 0, 1, 1 },
0811     { SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT), 0, 1, 1 },
0812     /* RLC */
0813     { SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT), 0, 1, 1 },
0814     { SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2), 0, 1, 1 },
0815     /* SPI */
0816     { SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT), 0, 8, 1 },
0817     /* SQC */
0818     { SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT), 0, 8, 7 },
0819     { SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2), 0, 8, 7 },
0820     { SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3), 0, 8, 7 },
0821     { SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3), 0, 8, 7 },
0822     /* SQ */
0823     { SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT), 0, 8, 14 },
0824     /* TCP */
0825     { SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW), 0, 8, 14 },
0826     /* TCI */
0827     { SOC15_REG_ENTRY(GC, 0, regTCI_EDC_CNT), 0, 1, 69 },
0828     /* TCC */
0829     { SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT), 0, 1, 16 },
0830     { SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2), 0, 1, 16 },
0831     /* TCA */
0832     { SOC15_REG_ENTRY(GC, 0, regTCA_EDC_CNT), 0, 1, 2 },
0833     /* TCX */
0834     { SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT), 0, 1, 2 },
0835     { SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2), 0, 1, 2 },
0836     /* TD */
0837     { SOC15_REG_ENTRY(GC, 0, regTD_EDC_CNT), 0, 8, 14 },
0838     /* TA */
0839     { SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT), 0, 8, 14 },
0840     /* GCEA */
0841     { SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT), 0, 1, 16 },
0842     { SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2), 0, 1, 16 },
0843     { SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 1, 16 },
0844 };
0845
0846 static void gfx_v9_4_2_select_se_sh(struct amdgpu_device *adev, u32 se_num,
0847                   u32 sh_num, u32 instance)
0848 {
0849     u32 data;
0850
0851     if (instance == 0xffffffff)
0852         data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
0853                      INSTANCE_BROADCAST_WRITES, 1);
0854     else
0855         data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
0856                      instance);
0857
0858     if (se_num == 0xffffffff)
0859         data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
0860                      1);
0861     else
0862         data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
0863
0864     if (sh_num == 0xffffffff)
0865         data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES,
0866                      1);
0867     else
0868         data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
0869
0870     WREG32_SOC15_RLC_SHADOW_EX(reg, GC, 0, regGRBM_GFX_INDEX, data);
0871 }
0872
0873 static const struct soc15_ras_field_entry gfx_v9_4_2_ras_fields[] = {
0874     /* CPF */
0875     { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, regCPF_EDC_ROQ_CNT),
0876       SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, SEC_COUNT_ME2),
0877       SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, DED_COUNT_ME2) },
0878     { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, regCPF_EDC_ROQ_CNT),
0879       SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, SEC_COUNT_ME1),
0880       SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, DED_COUNT_ME1) },
0881     { "CPF_TCIU_TAG", SOC15_REG_ENTRY(GC, 0, regCPF_EDC_TAG_CNT),
0882       SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT),
0883       SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT) },
0884
0885     /* CPC */
0886     { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, regCPC_EDC_SCRATCH_CNT),
0887       SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT),
0888       SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT) },
0889     { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, regCPC_EDC_UCODE_CNT),
0890       SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT),
0891       SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT) },
0892     { "CPC_DC_STATE_RAM_ME1", SOC15_REG_ENTRY(GC, 0, regDC_EDC_STATE_CNT),
0893       SOC15_REG_FIELD(DC_EDC_STATE_CNT, SEC_COUNT_ME1),
0894       SOC15_REG_FIELD(DC_EDC_STATE_CNT, DED_COUNT_ME1) },
0895     { "CPC_DC_CSINVOC_RAM_ME1",
0896       SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT),
0897       SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, SEC_COUNT_ME1),
0898       SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, DED_COUNT_ME1) },
0899     { "CPC_DC_RESTORE_RAM_ME1",
0900       SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT),
0901       SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, SEC_COUNT_ME1),
0902       SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, DED_COUNT_ME1) },
0903     { "CPC_DC_CSINVOC_RAM1_ME1",
0904       SOC15_REG_ENTRY(GC, 0, regDC_EDC_CSINVOC_CNT),
0905       SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, SEC_COUNT1_ME1),
0906       SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, DED_COUNT1_ME1) },
0907     { "CPC_DC_RESTORE_RAM1_ME1",
0908       SOC15_REG_ENTRY(GC, 0, regDC_EDC_RESTORE_CNT),
0909       SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, SEC_COUNT1_ME1),
0910       SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, DED_COUNT1_ME1) },
0911
0912     /* GDS */
0913     { "GDS_GRBM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_GRBM_CNT),
0914       SOC15_REG_FIELD(GDS_EDC_GRBM_CNT, SEC),
0915       SOC15_REG_FIELD(GDS_EDC_GRBM_CNT, DED) },
0916     { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_CNT),
0917       SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC),
0918       SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED) },
0919     { "GDS_PHY_CMD_RAM_MEM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PHY_CNT),
0920       SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC),
0921       SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) },
0922     { "GDS_PHY_DATA_RAM_MEM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PHY_CNT),
0923       SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SEC),
0924       SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_DED) },
0925     { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PHY_CNT),
0926       SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC),
0927       SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) },
0928     { "GDS_ME1_PIPE0_PIPE_MEM",
0929       SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT),
0930       SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC),
0931       SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) },
0932     { "GDS_ME1_PIPE1_PIPE_MEM",
0933       SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT),
0934       SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC),
0935       SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) },
0936     { "GDS_ME1_PIPE2_PIPE_MEM",
0937       SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT),
0938       SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC),
0939       SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) },
0940     { "GDS_ME1_PIPE3_PIPE_MEM",
0941       SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_PIPE_CNT),
0942       SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC),
0943       SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) },
0944     { "GDS_ME0_GFXHP3D_PIX_DED",
0945       SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
0946       SOC15_REG_FIELD(GDS_EDC_OA_DED, ME0_GFXHP3D_PIX_DED) },
0947     { "GDS_ME0_GFXHP3D_VTX_DED",
0948       SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
0949       SOC15_REG_FIELD(GDS_EDC_OA_DED, ME0_GFXHP3D_VTX_DED) },
0950     { "GDS_ME0_CS_DED",
0951       SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
0952       SOC15_REG_FIELD(GDS_EDC_OA_DED, ME0_CS_DED) },
0953     { "GDS_ME0_GFXHP3D_GS_DED",
0954       SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
0955       SOC15_REG_FIELD(GDS_EDC_OA_DED, ME0_GFXHP3D_GS_DED) },
0956     { "GDS_ME1_PIPE0_DED",
0957       SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
0958       SOC15_REG_FIELD(GDS_EDC_OA_DED, ME1_PIPE0_DED) },
0959     { "GDS_ME1_PIPE1_DED",
0960       SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
0961       SOC15_REG_FIELD(GDS_EDC_OA_DED, ME1_PIPE1_DED) },
0962     { "GDS_ME1_PIPE2_DED",
0963       SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
0964       SOC15_REG_FIELD(GDS_EDC_OA_DED, ME1_PIPE2_DED) },
0965     { "GDS_ME1_PIPE3_DED",
0966       SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
0967       SOC15_REG_FIELD(GDS_EDC_OA_DED, ME1_PIPE3_DED) },
0968     { "GDS_ME2_PIPE0_DED",
0969       SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
0970       SOC15_REG_FIELD(GDS_EDC_OA_DED, ME2_PIPE0_DED) },
0971     { "GDS_ME2_PIPE1_DED",
0972       SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
0973       SOC15_REG_FIELD(GDS_EDC_OA_DED, ME2_PIPE1_DED) },
0974     { "GDS_ME2_PIPE2_DED",
0975       SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
0976       SOC15_REG_FIELD(GDS_EDC_OA_DED, ME2_PIPE2_DED) },
0977     { "GDS_ME2_PIPE3_DED",
0978       SOC15_REG_ENTRY(GC, 0, regGDS_EDC_OA_DED), 0, 0,
0979       SOC15_REG_FIELD(GDS_EDC_OA_DED, ME2_PIPE3_DED) },
0980
0981     /* RLC */
0982     { "RLCG_INSTR_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT),
0983       SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_INSTR_RAM_SEC_COUNT),
0984       SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_INSTR_RAM_DED_COUNT) },
0985     { "RLCG_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT),
0986       SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_SCRATCH_RAM_SEC_COUNT),
0987       SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_SCRATCH_RAM_DED_COUNT) },
0988     { "RLCV_INSTR_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT),
0989       SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_INSTR_RAM_SEC_COUNT),
0990       SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_INSTR_RAM_DED_COUNT) },
0991     { "RLCV_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT),
0992       SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_SCRATCH_RAM_SEC_COUNT),
0993       SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_SCRATCH_RAM_DED_COUNT) },
0994     { "RLC_TCTAG_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT),
0995       SOC15_REG_FIELD(RLC_EDC_CNT, RLC_TCTAG_RAM_SEC_COUNT),
0996       SOC15_REG_FIELD(RLC_EDC_CNT, RLC_TCTAG_RAM_DED_COUNT) },
0997     { "RLC_SPM_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT),
0998       SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SPM_SCRATCH_RAM_SEC_COUNT),
0999       SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SPM_SCRATCH_RAM_DED_COUNT) },
1000     { "RLC_SRM_DATA_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT),
1001       SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_DATA_RAM_SEC_COUNT),
1002       SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_DATA_RAM_DED_COUNT) },
1003     { "RLC_SRM_ADDR_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT),
1004       SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_ADDR_RAM_SEC_COUNT),
1005       SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_ADDR_RAM_DED_COUNT) },
1006     { "RLC_SPM_SE0_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2),
1007       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE0_SCRATCH_RAM_SEC_COUNT),
1008       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE0_SCRATCH_RAM_DED_COUNT) },
1009     { "RLC_SPM_SE1_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2),
1010       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE1_SCRATCH_RAM_SEC_COUNT),
1011       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE1_SCRATCH_RAM_DED_COUNT) },
1012     { "RLC_SPM_SE2_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2),
1013       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE2_SCRATCH_RAM_SEC_COUNT),
1014       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE2_SCRATCH_RAM_DED_COUNT) },
1015     { "RLC_SPM_SE3_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2),
1016       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE3_SCRATCH_RAM_SEC_COUNT),
1017       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE3_SCRATCH_RAM_DED_COUNT) },
1018     { "RLC_SPM_SE4_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2),
1019       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE4_SCRATCH_RAM_SEC_COUNT),
1020       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE4_SCRATCH_RAM_DED_COUNT) },
1021     { "RLC_SPM_SE5_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2),
1022       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE5_SCRATCH_RAM_SEC_COUNT),
1023       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE5_SCRATCH_RAM_DED_COUNT) },
1024     { "RLC_SPM_SE6_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2),
1025       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE6_SCRATCH_RAM_SEC_COUNT),
1026       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE6_SCRATCH_RAM_DED_COUNT) },
1027     { "RLC_SPM_SE7_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, regRLC_EDC_CNT2),
1028       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE7_SCRATCH_RAM_SEC_COUNT),
1029       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE7_SCRATCH_RAM_DED_COUNT) },
1030
1031     /* SPI */
1032     { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT),
1033       SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SEC_COUNT),
1034       SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_DED_COUNT) },
1035     { "SPI_GDS_EXPREQ", SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT),
1036       SOC15_REG_FIELD(SPI_EDC_CNT, SPI_GDS_EXPREQ_SEC_COUNT),
1037       SOC15_REG_FIELD(SPI_EDC_CNT, SPI_GDS_EXPREQ_DED_COUNT) },
1038     { "SPI_WB_GRANT_30", SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT),
1039       SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_30_SEC_COUNT),
1040       SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_30_DED_COUNT) },
1041     { "SPI_LIFE_CNT", SOC15_REG_ENTRY(GC, 0, regSPI_EDC_CNT),
1042       SOC15_REG_FIELD(SPI_EDC_CNT, SPI_LIFE_CNT_SEC_COUNT),
1043       SOC15_REG_FIELD(SPI_EDC_CNT, SPI_LIFE_CNT_DED_COUNT) },
1044
1045     /* SQC - regSQC_EDC_CNT */
1046     { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT),
1047       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT),
1048       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) },
1049     { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT),
1050       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT),
1051       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) },
1052     { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT),
1053       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT),
1054       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) },
1055     { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT),
1056       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT),
1057       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) },
1058     { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT),
1059       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT),
1060       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) },
1061     { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT),
1062       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT),
1063       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) },
1064     { "SQC_DATA_CU3_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT),
1065       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU3_WRITE_DATA_BUF_SEC_COUNT),
1066       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU3_WRITE_DATA_BUF_DED_COUNT) },
1067     { "SQC_DATA_CU3_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT),
1068       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU3_UTCL1_LFIFO_SEC_COUNT),
1069       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU3_UTCL1_LFIFO_DED_COUNT) },
1070
1071     /* SQC - regSQC_EDC_CNT2 */
1072     { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2),
1073       SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT),
1074       SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) },
1075     { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2),
1076       SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT),
1077       SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) },
1078     { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2),
1079       SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT),
1080       SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) },
1081     { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2),
1082       SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT),
1083       SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) },
1084     { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2),
1085       SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT),
1086       SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) },
1087     { "SQC_DATA_BANKA_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT2),
1088       SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_SEC_COUNT),
1089       SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_DIRTY_BIT_RAM_DED_COUNT) },
1090
1091     /* SQC - regSQC_EDC_CNT3 */
1092     { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3),
1093       SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT),
1094       SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) },
1095     { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3),
1096       SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT),
1097       SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) },
1098     { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3),
1099       SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT),
1100       SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) },
1101     { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3),
1102       SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT),
1103       SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) },
1104     { "SQC_DATA_BANKB_DIRTY_BIT_RAM", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_CNT3),
1105       SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_SEC_COUNT),
1106       SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_DIRTY_BIT_RAM_DED_COUNT) },
1107
1108     /* SQC - regSQC_EDC_PARITY_CNT3 */
1109     { "SQC_INST_BANKA_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3),
1110       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT),
1111       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT) },
1112     { "SQC_INST_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3),
1113       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKA_MISS_FIFO_SEC_COUNT),
1114       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKA_MISS_FIFO_DED_COUNT) },
1115     { "SQC_DATA_BANKA_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3),
1116       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_HIT_FIFO_SEC_COUNT),
1117       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_HIT_FIFO_DED_COUNT) },
1118     { "SQC_DATA_BANKA_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3),
1119       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_MISS_FIFO_SEC_COUNT),
1120       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_MISS_FIFO_DED_COUNT) },
1121     { "SQC_INST_BANKB_UTCL1_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3),
1122       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT),
1123       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT) },
1124     { "SQC_INST_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3),
1125       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKB_MISS_FIFO_SEC_COUNT),
1126       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKB_MISS_FIFO_DED_COUNT) },
1127     { "SQC_DATA_BANKB_HIT_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3),
1128       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_HIT_FIFO_SEC_COUNT),
1129       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_HIT_FIFO_DED_COUNT) },
1130     { "SQC_DATA_BANKB_MISS_FIFO", SOC15_REG_ENTRY(GC, 0, regSQC_EDC_PARITY_CNT3),
1131       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_MISS_FIFO_SEC_COUNT),
1132       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_MISS_FIFO_DED_COUNT) },
1133
1134     /* SQ */
1135     { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT),
1136       SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT),
1137       SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT) },
1138     { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT),
1139       SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT),
1140       SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT) },
1141     { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT),
1142       SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT),
1143       SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT) },
1144     { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT),
1145       SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT),
1146       SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT) },
1147     { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT),
1148       SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT),
1149       SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT) },
1150     { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT),
1151       SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT),
1152       SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT) },
1153     { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, regSQ_EDC_CNT),
1154       SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT),
1155       SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT) },
1156
1157     /* TCP */
1158     { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW),
1159       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT),
1160       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) },
1161     { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW),
1162       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT),
1163       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) },
1164     { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW),
1165       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SEC_COUNT),
1166       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_DED_COUNT) },
1167     { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW),
1168       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT),
1169       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_DED_COUNT) },
1170     { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW),
1171       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SEC_COUNT),
1172       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_DED_COUNT) },
1173     { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW),
1174       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT),
1175       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) },
1176     { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, regTCP_EDC_CNT_NEW),
1177       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT),
1178       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) },
1179
1180     /* TCI */
1181     { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, regTCI_EDC_CNT),
1182       SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SEC_COUNT),
1183       SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_DED_COUNT) },
1184
1185     /* TCC */
1186     { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT),
1187       SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT),
1188       SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) },
1189     { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT),
1190       SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT),
1191       SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) },
1192     { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT),
1193       SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT),
1194       SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) },
1195     { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT),
1196       SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT),
1197       SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) },
1198     { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT),
1199       SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT),
1200       SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) },
1201     { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT),
1202       SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SEC_COUNT),
1203       SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_DED_COUNT) },
1204     { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT),
1205       SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_NEXT_RAM_SEC_COUNT),
1206       SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_NEXT_RAM_DED_COUNT) },
1207     { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2),
1208       SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SEC_COUNT),
1209       SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_DED_COUNT) },
1210     { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2),
1211       SOC15_REG_FIELD(TCC_EDC_CNT2, UC_ATOMIC_FIFO_SEC_COUNT),
1212       SOC15_REG_FIELD(TCC_EDC_CNT2, UC_ATOMIC_FIFO_DED_COUNT) },
1213     { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2),
1214       SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SEC_COUNT),
1215       SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_DED_COUNT) },
1216     { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2),
1217       SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_CONTROL_SEC_COUNT),
1218       SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_CONTROL_DED_COUNT) },
1219     { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2),
1220       SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_TRANSFER_SEC_COUNT),
1221       SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_TRANSFER_DED_COUNT) },
1222     { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2),
1223       SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_DEC_SEC_COUNT),
1224       SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_DEC_DED_COUNT) },
1225     { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2),
1226       SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SEC_COUNT),
1227       SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_DED_COUNT) },
1228     { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, regTCC_EDC_CNT2),
1229       SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_DATA_SEC_COUNT),
1230       SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_DATA_DED_COUNT) },
1231
1232     /* TCA */
1233     { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, regTCA_EDC_CNT),
1234       SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SEC_COUNT),
1235       SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_DED_COUNT) },
1236     { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, regTCA_EDC_CNT),
1237       SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SEC_COUNT),
1238       SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_DED_COUNT) },
1239
1240     /* TCX */
1241     { "TCX_GROUP0", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
1242       SOC15_REG_FIELD(TCX_EDC_CNT, GROUP0_SEC_COUNT),
1243       SOC15_REG_FIELD(TCX_EDC_CNT, GROUP0_DED_COUNT) },
1244     { "TCX_GROUP1", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
1245       SOC15_REG_FIELD(TCX_EDC_CNT, GROUP1_SEC_COUNT),
1246       SOC15_REG_FIELD(TCX_EDC_CNT, GROUP1_DED_COUNT) },
1247     { "TCX_GROUP2", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
1248       SOC15_REG_FIELD(TCX_EDC_CNT, GROUP2_SEC_COUNT),
1249       SOC15_REG_FIELD(TCX_EDC_CNT, GROUP2_DED_COUNT) },
1250     { "TCX_GROUP3", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
1251       SOC15_REG_FIELD(TCX_EDC_CNT, GROUP3_SEC_COUNT),
1252       SOC15_REG_FIELD(TCX_EDC_CNT, GROUP3_DED_COUNT) },
1253     { "TCX_GROUP4", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
1254       SOC15_REG_FIELD(TCX_EDC_CNT, GROUP4_SEC_COUNT),
1255       SOC15_REG_FIELD(TCX_EDC_CNT, GROUP4_DED_COUNT) },
1256     { "TCX_GROUP5", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
1257       SOC15_REG_FIELD(TCX_EDC_CNT, GROUP5_SED_COUNT), 0, 0 },
1258     { "TCX_GROUP6", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
1259       SOC15_REG_FIELD(TCX_EDC_CNT, GROUP6_SED_COUNT), 0, 0 },
1260     { "TCX_GROUP7", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
1261       SOC15_REG_FIELD(TCX_EDC_CNT, GROUP7_SED_COUNT), 0, 0 },
1262     { "TCX_GROUP8", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
1263       SOC15_REG_FIELD(TCX_EDC_CNT, GROUP8_SED_COUNT), 0, 0 },
1264     { "TCX_GROUP9", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
1265       SOC15_REG_FIELD(TCX_EDC_CNT, GROUP9_SED_COUNT), 0, 0 },
1266     { "TCX_GROUP10", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT),
1267       SOC15_REG_FIELD(TCX_EDC_CNT, GROUP10_SED_COUNT), 0, 0 },
1268     { "TCX_GROUP11", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2),
1269       SOC15_REG_FIELD(TCX_EDC_CNT2, GROUP11_SED_COUNT), 0, 0 },
1270     { "TCX_GROUP12", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2),
1271       SOC15_REG_FIELD(TCX_EDC_CNT2, GROUP12_SED_COUNT), 0, 0 },
1272     { "TCX_GROUP13", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2),
1273       SOC15_REG_FIELD(TCX_EDC_CNT2, GROUP13_SED_COUNT), 0, 0 },
1274     { "TCX_GROUP14", SOC15_REG_ENTRY(GC, 0, regTCX_EDC_CNT2),
1275       SOC15_REG_FIELD(TCX_EDC_CNT2, GROUP14_SED_COUNT), 0, 0 },
1276
1277     /* TD */
1278     { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, regTD_EDC_CNT),
1279       SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT),
1280       SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) },
1281     { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, regTD_EDC_CNT),
1282       SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT),
1283       SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) },
1284     { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, regTD_EDC_CNT),
1285       SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SEC_COUNT),
1286       SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_DED_COUNT) },
1287
1288     /* TA */
1289     { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT),
1290       SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT),
1291       SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) },
1292     { "TA_FS_AFIFO_LO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT),
1293       SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_LO_SEC_COUNT),
1294       SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_LO_DED_COUNT) },
1295     { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT),
1296       SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SEC_COUNT),
1297       SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_DED_COUNT) },
1298     { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT),
1299       SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SEC_COUNT),
1300       SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_DED_COUNT) },
1301     { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT),
1302       SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SEC_COUNT),
1303       SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_DED_COUNT) },
1304     { "TA_FS_AFIFO_HI", SOC15_REG_ENTRY(GC, 0, regTA_EDC_CNT),
1305       SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_HI_SEC_COUNT),
1306       SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_HI_DED_COUNT) },
1307
1308     /* EA - regGCEA_EDC_CNT */
1309     { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
1310       SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1311       SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) },
1312     { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
1313       SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1314       SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) },
1315     { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
1316       SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1317       SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) },
1318     { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
1319       SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1320       SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) },
1321     { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
1322       SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1323       SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) },
1324     { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
1325       SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
1326       SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_DED_COUNT) },
1327     { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
1328       SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 0, 0 },
1329     { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
1330       SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 0, 0 },
1331     { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
1332       SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 0, 0 },
1333     { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT),
1334       SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 0, 0 },
1335
1336     /* EA - regGCEA_EDC_CNT2 */
1337     { "EA_GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
1338       SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1339       SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) },
1340     { "EA_GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
1341       SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1342       SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) },
1343     { "EA_GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
1344       SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1345       SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) },
1346     { "EA_GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
1347       SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 0, 0 },
1348     { "EA_GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
1349       SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 0, 0 },
1350     { "EA_MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
1351       SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1352       SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_DED_COUNT) },
1353     { "EA_MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
1354       SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1355       SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_DED_COUNT) },
1356     { "EA_MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
1357       SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1358       SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_DED_COUNT) },
1359     { "EA_MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT2),
1360       SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1361       SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_DED_COUNT) },
1362
1363     /* EA - regGCEA_EDC_CNT3 */
1364     { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0,
1365       SOC15_REG_FIELD(GCEA_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT) },
1366     { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0,
1367       SOC15_REG_FIELD(GCEA_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT) },
1368     { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0,
1369       SOC15_REG_FIELD(GCEA_EDC_CNT3, IORD_CMDMEM_DED_COUNT) },
1370     { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0,
1371       SOC15_REG_FIELD(GCEA_EDC_CNT3, IOWR_CMDMEM_DED_COUNT) },
1372     { "EA_GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0,
1373       SOC15_REG_FIELD(GCEA_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT) },
1374     { "EA_GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3), 0, 0,
1375       SOC15_REG_FIELD(GCEA_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT) },
1376     { "EA_MAM_A0MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3),
1377       SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A0MEM_SEC_COUNT),
1378       SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A0MEM_DED_COUNT) },
1379     { "EA_MAM_A1MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3),
1380       SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A1MEM_SEC_COUNT),
1381       SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A1MEM_DED_COUNT) },
1382     { "EA_MAM_A2MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3),
1383       SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A2MEM_SEC_COUNT),
1384       SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A2MEM_DED_COUNT) },
1385     { "EA_MAM_A3MEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3),
1386       SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A3MEM_SEC_COUNT),
1387       SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A3MEM_DED_COUNT) },
1388     { "EA_MAM_AFMEM", SOC15_REG_ENTRY(GC, 0, regGCEA_EDC_CNT3),
1389       SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_AFMEM_SEC_COUNT),
1390       SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_AFMEM_DED_COUNT) },
1391 };
1392
1393 static const char * const vml2_walker_mems[] = {
1394     "UTC_VML2_CACHE_PDE0_MEM0",
1395     "UTC_VML2_CACHE_PDE0_MEM1",
1396     "UTC_VML2_CACHE_PDE1_MEM0",
1397     "UTC_VML2_CACHE_PDE1_MEM1",
1398     "UTC_VML2_CACHE_PDE2_MEM0",
1399     "UTC_VML2_CACHE_PDE2_MEM1",
1400     "UTC_VML2_RDIF_ARADDRS",
1401     "UTC_VML2_RDIF_LOG_FIFO",
1402     "UTC_VML2_QUEUE_REQ",
1403     "UTC_VML2_QUEUE_RET",
1404 };
1405
1406 static struct gfx_v9_4_2_utc_block gfx_v9_4_2_utc_blocks[] = {
1407     { VML2_MEM, 8, 2, 2,
1408       { SOC15_REG_ENTRY(GC, 0, regVML2_MEM_ECC_INDEX) },
1409       { SOC15_REG_ENTRY(GC, 0, regVML2_MEM_ECC_CNTL) },
1410       SOC15_REG_FIELD(VML2_MEM_ECC_CNTL, SEC_COUNT),
1411       SOC15_REG_FIELD(VML2_MEM_ECC_CNTL, DED_COUNT),
1412       REG_SET_FIELD(0, VML2_MEM_ECC_CNTL, WRITE_COUNTERS, 1) },
1413     { VML2_WALKER_MEM, ARRAY_SIZE(vml2_walker_mems), 1, 1,
1414       { SOC15_REG_ENTRY(GC, 0, regVML2_WALKER_MEM_ECC_INDEX) },
1415       { SOC15_REG_ENTRY(GC, 0, regVML2_WALKER_MEM_ECC_CNTL) },
1416       SOC15_REG_FIELD(VML2_WALKER_MEM_ECC_CNTL, SEC_COUNT),
1417       SOC15_REG_FIELD(VML2_WALKER_MEM_ECC_CNTL, DED_COUNT),
1418       REG_SET_FIELD(0, VML2_WALKER_MEM_ECC_CNTL, WRITE_COUNTERS, 1) },
1419     { UTCL2_MEM, 18, 1, 2,
1420       { SOC15_REG_ENTRY(GC, 0, regUTCL2_MEM_ECC_INDEX) },
1421       { SOC15_REG_ENTRY(GC, 0, regUTCL2_MEM_ECC_CNTL) },
1422       SOC15_REG_FIELD(UTCL2_MEM_ECC_CNTL, SEC_COUNT),
1423       SOC15_REG_FIELD(UTCL2_MEM_ECC_CNTL, DED_COUNT),
1424       REG_SET_FIELD(0, UTCL2_MEM_ECC_CNTL, WRITE_COUNTERS, 1) },
1425     { ATC_L2_CACHE_2M, 8, 2, 1,
1426       { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_2M_DSM_INDEX) },
1427       { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_2M_DSM_CNTL) },
1428       SOC15_REG_FIELD(ATC_L2_CACHE_2M_DSM_CNTL, SEC_COUNT),
1429       SOC15_REG_FIELD(ATC_L2_CACHE_2M_DSM_CNTL, DED_COUNT),
1430       REG_SET_FIELD(0, ATC_L2_CACHE_2M_DSM_CNTL, WRITE_COUNTERS, 1) },
1431     { ATC_L2_CACHE_32K, 8, 2, 2,
1432       { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_32K_DSM_INDEX) },
1433       { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_32K_DSM_CNTL) },
1434       SOC15_REG_FIELD(ATC_L2_CACHE_32K_DSM_CNTL, SEC_COUNT),
1435       SOC15_REG_FIELD(ATC_L2_CACHE_32K_DSM_CNTL, DED_COUNT),
1436       REG_SET_FIELD(0, ATC_L2_CACHE_32K_DSM_CNTL, WRITE_COUNTERS, 1) },
1437     { ATC_L2_CACHE_4K, 8, 2, 8,
1438       { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_4K_DSM_INDEX) },
1439       { SOC15_REG_ENTRY(GC, 0, regATC_L2_CACHE_4K_DSM_CNTL) },
1440       SOC15_REG_FIELD(ATC_L2_CACHE_4K_DSM_CNTL, SEC_COUNT),
1441       SOC15_REG_FIELD(ATC_L2_CACHE_4K_DSM_CNTL, DED_COUNT),
1442       REG_SET_FIELD(0, ATC_L2_CACHE_4K_DSM_CNTL, WRITE_COUNTERS, 1) },
1443 };
1444
1445 static const struct soc15_reg_entry gfx_v9_4_2_ea_err_status_regs = {
1446     SOC15_REG_ENTRY(GC, 0, regGCEA_ERR_STATUS), 0, 1, 16
1447 };
1448
1449 static int gfx_v9_4_2_get_reg_error_count(struct amdgpu_device *adev,
1450                       const struct soc15_reg_entry *reg,
1451                       uint32_t se_id, uint32_t inst_id,
1452                       uint32_t value, uint32_t *sec_count,
1453                       uint32_t *ded_count)
1454 {
1455     uint32_t i;
1456     uint32_t sec_cnt, ded_cnt;
1457
1458     for (i = 0; i < ARRAY_SIZE(gfx_v9_4_2_ras_fields); i++) {
1459         if (gfx_v9_4_2_ras_fields[i].reg_offset != reg->reg_offset ||
1460             gfx_v9_4_2_ras_fields[i].seg != reg->seg ||
1461             gfx_v9_4_2_ras_fields[i].inst != reg->inst)
1462             continue;
1463
1464         sec_cnt = SOC15_RAS_REG_FIELD_VAL(
1465             value, gfx_v9_4_2_ras_fields[i], sec);
1466         if (sec_cnt) {
1467             dev_info(adev->dev,
1468                  "GFX SubBlock %s, Instance[%d][%d], SEC %d\n",
1469                  gfx_v9_4_2_ras_fields[i].name, se_id, inst_id,
1470                  sec_cnt);
1471             *sec_count += sec_cnt;
1472         }
1473
1474         ded_cnt = SOC15_RAS_REG_FIELD_VAL(
1475             value, gfx_v9_4_2_ras_fields[i], ded);
1476         if (ded_cnt) {
1477             dev_info(adev->dev,
1478                  "GFX SubBlock %s, Instance[%d][%d], DED %d\n",
1479                  gfx_v9_4_2_ras_fields[i].name, se_id, inst_id,
1480                  ded_cnt);
1481             *ded_count += ded_cnt;
1482         }
1483     }
1484
1485     return 0;
1486 }
1487
1488 static int gfx_v9_4_2_query_sram_edc_count(struct amdgpu_device *adev,
1489                 uint32_t *sec_count, uint32_t *ded_count)
1490 {
1491     uint32_t i, j, k, data;
1492     uint32_t sec_cnt = 0, ded_cnt = 0;
1493
1494     if (sec_count && ded_count) {
1495         *sec_count = 0;
1496         *ded_count = 0;
1497     }
1498
1499     mutex_lock(&adev->grbm_idx_mutex);
1500
1501     for (i = 0; i < ARRAY_SIZE(gfx_v9_4_2_edc_counter_regs); i++) {
1502         for (j = 0; j < gfx_v9_4_2_edc_counter_regs[i].se_num; j++) {
1503             for (k = 0; k < gfx_v9_4_2_edc_counter_regs[i].instance;
1504                  k++) {
1505                 gfx_v9_4_2_select_se_sh(adev, j, 0, k);
1506
1507                 /* if sec/ded_count is null, just clear counter */
1508                 if (!sec_count || !ded_count) {
1509                     WREG32(SOC15_REG_ENTRY_OFFSET(
1510                         gfx_v9_4_2_edc_counter_regs[i]), 0);
1511                     continue;
1512                 }
1513
1514                 data = RREG32(SOC15_REG_ENTRY_OFFSET(
1515                     gfx_v9_4_2_edc_counter_regs[i]));
1516
1517                 if (!data)
1518                     continue;
1519
1520                 gfx_v9_4_2_get_reg_error_count(adev,
1521                     &gfx_v9_4_2_edc_counter_regs[i],
1522                     j, k, data, &sec_cnt, &ded_cnt);
1523
1524                 /* clear counter after read */
1525                 WREG32(SOC15_REG_ENTRY_OFFSET(
1526                     gfx_v9_4_2_edc_counter_regs[i]), 0);
1527             }
1528         }
1529     }
1530
1531     if (sec_count && ded_count) {
1532         *sec_count += sec_cnt;
1533         *ded_count += ded_cnt;
1534     }
1535
1536     gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1537     mutex_unlock(&adev->grbm_idx_mutex);
1538
1539     return 0;
1540 }
1541
1542 static void gfx_v9_4_2_log_utc_edc_count(struct amdgpu_device *adev,
1543                      struct gfx_v9_4_2_utc_block *blk,
1544                      uint32_t instance, uint32_t sec_cnt,
1545                      uint32_t ded_cnt)
1546 {
1547     uint32_t bank, way, mem;
1548     static const char *vml2_way_str[] = { "BIGK", "4K" };
1549     static const char *utcl2_rounter_str[] = { "VMC", "APT" };
1550
1551     mem = instance % blk->num_mem_blocks;
1552     way = (instance / blk->num_mem_blocks) % blk->num_ways;
1553     bank = instance / (blk->num_mem_blocks * blk->num_ways);
1554
1555     switch (blk->type) {
1556     case VML2_MEM:
1557         dev_info(
1558             adev->dev,
1559             "GFX SubBlock UTC_VML2_BANK_CACHE_%d_%s_MEM%d, SED %d, DED %d\n",
1560             bank, vml2_way_str[way], mem, sec_cnt, ded_cnt);
1561         break;
1562     case VML2_WALKER_MEM:
1563         dev_info(adev->dev, "GFX SubBlock %s, SED %d, DED %d\n",
1564              vml2_walker_mems[bank], sec_cnt, ded_cnt);
1565         break;
1566     case UTCL2_MEM:
1567         dev_info(
1568             adev->dev,
1569             "GFX SubBlock UTCL2_ROUTER_IFIF%d_GROUP0_%s, SED %d, DED %d\n",
1570             bank, utcl2_rounter_str[mem], sec_cnt, ded_cnt);
1571         break;
1572     case ATC_L2_CACHE_2M:
1573         dev_info(
1574             adev->dev,
1575             "GFX SubBlock UTC_ATCL2_CACHE_2M_BANK%d_WAY%d_MEM, SED %d, DED %d\n",
1576             bank, way, sec_cnt, ded_cnt);
1577         break;
1578     case ATC_L2_CACHE_32K:
1579         dev_info(
1580             adev->dev,
1581             "GFX SubBlock UTC_ATCL2_CACHE_32K_BANK%d_WAY%d_MEM%d, SED %d, DED %d\n",
1582             bank, way, mem, sec_cnt, ded_cnt);
1583         break;
1584     case ATC_L2_CACHE_4K:
1585         dev_info(
1586             adev->dev,
1587             "GFX SubBlock UTC_ATCL2_CACHE_4K_BANK%d_WAY%d_MEM%d, SED %d, DED %d\n",
1588             bank, way, mem, sec_cnt, ded_cnt);
1589         break;
1590     }
1591 }
1592
1593 static int gfx_v9_4_2_query_utc_edc_count(struct amdgpu_device *adev,
1594                       uint32_t *sec_count,
1595                       uint32_t *ded_count)
1596 {
1597     uint32_t i, j, data;
1598     uint32_t sec_cnt, ded_cnt;
1599     uint32_t num_instances;
1600     struct gfx_v9_4_2_utc_block *blk;
1601
1602     if (sec_count && ded_count) {
1603         *sec_count = 0;
1604         *ded_count = 0;
1605     }
1606
1607     for (i = 0; i < ARRAY_SIZE(gfx_v9_4_2_utc_blocks); i++) {
1608         blk = &gfx_v9_4_2_utc_blocks[i];
1609         num_instances =
1610             blk->num_banks * blk->num_ways * blk->num_mem_blocks;
1611         for (j = 0; j < num_instances; j++) {
1612             WREG32(SOC15_REG_ENTRY_OFFSET(blk->idx_reg), j);
1613
1614             /* if sec/ded_count is NULL, just clear counter */
1615             if (!sec_count || !ded_count) {
1616                 WREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg),
1617                        blk->clear);
1618                 continue;
1619             }
1620
1621             data = RREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg));
1622             if (!data)
1623                 continue;
1624
1625             sec_cnt = SOC15_RAS_REG_FIELD_VAL(data, *blk, sec);
1626             *sec_count += sec_cnt;
1627             ded_cnt = SOC15_RAS_REG_FIELD_VAL(data, *blk, ded);
1628             *ded_count += ded_cnt;
1629
1630             /* clear counter after read */
1631             WREG32(SOC15_REG_ENTRY_OFFSET(blk->data_reg),
1632                    blk->clear);
1633
1634             /* print the edc count */
1635             if (sec_cnt || ded_cnt)
1636                 gfx_v9_4_2_log_utc_edc_count(adev, blk, j, sec_cnt,
1637                                  ded_cnt);
1638         }
1639     }
1640
1641     return 0;
1642 }
1643
1644 static void gfx_v9_4_2_query_ras_error_count(struct amdgpu_device *adev,
1645                         void *ras_error_status)
1646 {
1647     struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
1648     uint32_t sec_count = 0, ded_count = 0;
1649
1650     if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
1651         return;
1652
1653     err_data->ue_count = 0;
1654     err_data->ce_count = 0;
1655
1656     gfx_v9_4_2_query_sram_edc_count(adev, &sec_count, &ded_count);
1657     err_data->ce_count += sec_count;
1658     err_data->ue_count += ded_count;
1659
1660     gfx_v9_4_2_query_utc_edc_count(adev, &sec_count, &ded_count);
1661     err_data->ce_count += sec_count;
1662     err_data->ue_count += ded_count;
1663
1664 }
1665
1666 static void gfx_v9_4_2_reset_utc_err_status(struct amdgpu_device *adev)
1667 {
1668     WREG32_SOC15(GC, 0, regUTCL2_MEM_ECC_STATUS, 0x3);
1669     WREG32_SOC15(GC, 0, regVML2_MEM_ECC_STATUS, 0x3);
1670     WREG32_SOC15(GC, 0, regVML2_WALKER_MEM_ECC_STATUS, 0x3);
1671 }
1672
1673 static void gfx_v9_4_2_reset_ea_err_status(struct amdgpu_device *adev)
1674 {
1675     uint32_t i, j;
1676     uint32_t value;
1677
1678     mutex_lock(&adev->grbm_idx_mutex);
1679     for (i = 0; i < gfx_v9_4_2_ea_err_status_regs.se_num; i++) {
1680         for (j = 0; j < gfx_v9_4_2_ea_err_status_regs.instance;
1681              j++) {
1682             gfx_v9_4_2_select_se_sh(adev, i, 0, j);
1683             value = RREG32(SOC15_REG_ENTRY_OFFSET(
1684                 gfx_v9_4_2_ea_err_status_regs));
1685             value = REG_SET_FIELD(value, GCEA_ERR_STATUS, CLEAR_ERROR_STATUS, 0x1);
1686             WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), value);
1687         }
1688     }
1689     gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1690     mutex_unlock(&adev->grbm_idx_mutex);
1691 }
1692
1693 static void gfx_v9_4_2_reset_ras_error_count(struct amdgpu_device *adev)
1694 {
1695     if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
1696         return;
1697
1698     gfx_v9_4_2_query_sram_edc_count(adev, NULL, NULL);
1699     gfx_v9_4_2_query_utc_edc_count(adev, NULL, NULL);
1700 }
1701
1702 static int gfx_v9_4_2_ras_error_inject(struct amdgpu_device *adev, void *inject_if)
1703 {
1704     struct ras_inject_if *info = (struct ras_inject_if *)inject_if;
1705     int ret;
1706     struct ta_ras_trigger_error_input block_info = { 0 };
1707
1708     if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
1709         return -EINVAL;
1710
1711     block_info.block_id = amdgpu_ras_block_to_ta(info->head.block);
1712     block_info.sub_block_index = info->head.sub_block_index;
1713     block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type);
1714     block_info.address = info->address;
1715     block_info.value = info->value;
1716
1717     mutex_lock(&adev->grbm_idx_mutex);
1718     ret = psp_ras_trigger_error(&adev->psp, &block_info);
1719     mutex_unlock(&adev->grbm_idx_mutex);
1720
1721     return ret;
1722 }
1723
1724 static void gfx_v9_4_2_query_ea_err_status(struct amdgpu_device *adev)
1725 {
1726     uint32_t i, j;
1727     uint32_t reg_value;
1728
1729     mutex_lock(&adev->grbm_idx_mutex);
1730
1731     for (i = 0; i < gfx_v9_4_2_ea_err_status_regs.se_num; i++) {
1732         for (j = 0; j < gfx_v9_4_2_ea_err_status_regs.instance;
1733              j++) {
1734             gfx_v9_4_2_select_se_sh(adev, i, 0, j);
1735             reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(
1736                 gfx_v9_4_2_ea_err_status_regs));
1737
1738             if (REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_STATUS) ||
1739                 REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_WRRSP_STATUS) ||
1740                 REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
1741                 dev_warn(adev->dev, "GCEA err detected at instance: %d, status: 0x%x!\n",
1742                         j, reg_value);
1743             }
1744             /* clear after read */
1745             reg_value = REG_SET_FIELD(reg_value, GCEA_ERR_STATUS,
1746                           CLEAR_ERROR_STATUS, 0x1);
1747             WREG32(SOC15_REG_ENTRY_OFFSET(gfx_v9_4_2_ea_err_status_regs), reg_value);
1748         }
1749     }
1750
1751     gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1752     mutex_unlock(&adev->grbm_idx_mutex);
1753 }
1754
1755 static void gfx_v9_4_2_query_utc_err_status(struct amdgpu_device *adev)
1756 {
1757     uint32_t data;
1758
1759     data = RREG32_SOC15(GC, 0, regUTCL2_MEM_ECC_STATUS);
1760     if (data) {
1761         dev_warn(adev->dev, "GFX UTCL2 Mem Ecc Status: 0x%x!\n", data);
1762         WREG32_SOC15(GC, 0, regUTCL2_MEM_ECC_STATUS, 0x3);
1763     }
1764
1765     data = RREG32_SOC15(GC, 0, regVML2_MEM_ECC_STATUS);
1766     if (data) {
1767         dev_warn(adev->dev, "GFX VML2 Mem Ecc Status: 0x%x!\n", data);
1768         WREG32_SOC15(GC, 0, regVML2_MEM_ECC_STATUS, 0x3);
1769     }
1770
1771     data = RREG32_SOC15(GC, 0, regVML2_WALKER_MEM_ECC_STATUS);
1772     if (data) {
1773         dev_warn(adev->dev, "GFX VML2 Walker Mem Ecc Status: 0x%x!\n", data);
1774         WREG32_SOC15(GC, 0, regVML2_WALKER_MEM_ECC_STATUS, 0x3);
1775     }
1776 }
1777
1778 static void gfx_v9_4_2_query_ras_error_status(struct amdgpu_device *adev)
1779 {
1780     if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
1781         return;
1782
1783     gfx_v9_4_2_query_ea_err_status(adev);
1784     gfx_v9_4_2_query_utc_err_status(adev);
1785     gfx_v9_4_2_query_sq_timeout_status(adev);
1786 }
1787
1788 static void gfx_v9_4_2_reset_ras_error_status(struct amdgpu_device *adev)
1789 {
1790     if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
1791         return;
1792
1793     gfx_v9_4_2_reset_utc_err_status(adev);
1794     gfx_v9_4_2_reset_ea_err_status(adev);
1795     gfx_v9_4_2_reset_sq_timeout_status(adev);
1796 }
1797
1798 static void gfx_v9_4_2_enable_watchdog_timer(struct amdgpu_device *adev)
1799 {
1800     uint32_t i;
1801     uint32_t data;
1802
1803     data = REG_SET_FIELD(0, SQ_TIMEOUT_CONFIG, TIMEOUT_FATAL_DISABLE,
1804                  amdgpu_watchdog_timer.timeout_fatal_disable ? 1 :
1805                                        0);
1806
1807     if (amdgpu_watchdog_timer.timeout_fatal_disable &&
1808         (amdgpu_watchdog_timer.period < 1 ||
1809          amdgpu_watchdog_timer.period > 0x23)) {
1810         dev_warn(adev->dev, "Watchdog period range is 1 to 0x23\n");
1811         amdgpu_watchdog_timer.period = 0x23;
1812     }
1813     data = REG_SET_FIELD(data, SQ_TIMEOUT_CONFIG, PERIOD_SEL,
1814                  amdgpu_watchdog_timer.period);
1815
1816     mutex_lock(&adev->grbm_idx_mutex);
1817     for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1818         gfx_v9_4_2_select_se_sh(adev, i, 0xffffffff, 0xffffffff);
1819         WREG32_SOC15(GC, 0, regSQ_TIMEOUT_CONFIG, data);
1820     }
1821     gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1822     mutex_unlock(&adev->grbm_idx_mutex);
1823 }
1824
1825 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
1826 {
1827     WREG32_SOC15_RLC_EX(reg, GC, 0, regSQ_IND_INDEX,
1828         (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1829         (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1830         (address << SQ_IND_INDEX__INDEX__SHIFT) |
1831         (SQ_IND_INDEX__FORCE_READ_MASK));
1832     return RREG32_SOC15(GC, 0, regSQ_IND_DATA);
1833 }
1834
1835 static void gfx_v9_4_2_log_cu_timeout_status(struct amdgpu_device *adev,
1836                     uint32_t status)
1837 {
1838     struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
1839     uint32_t i, simd, wave;
1840     uint32_t wave_status;
1841     uint32_t wave_pc_lo, wave_pc_hi;
1842     uint32_t wave_exec_lo, wave_exec_hi;
1843     uint32_t wave_inst_dw0, wave_inst_dw1;
1844     uint32_t wave_ib_sts;
1845
1846     for (i = 0; i < 32; i++) {
1847         if (!((i << 1) & status))
1848             continue;
1849
1850         simd = i / cu_info->max_waves_per_simd;
1851         wave = i % cu_info->max_waves_per_simd;
1852
1853         wave_status = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
1854         wave_pc_lo = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
1855         wave_pc_hi = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
1856         wave_exec_lo =
1857             wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
1858         wave_exec_hi =
1859             wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
1860         wave_inst_dw0 =
1861             wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
1862         wave_inst_dw1 =
1863             wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
1864         wave_ib_sts = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
1865
1866         dev_info(
1867             adev->dev,
1868             "\t SIMD %d, Wave %d: status 0x%x, pc 0x%llx, exec 0x%llx, inst 0x%llx, ib_sts 0x%x\n",
1869             simd, wave, wave_status,
1870             ((uint64_t)wave_pc_hi << 32 | wave_pc_lo),
1871             ((uint64_t)wave_exec_hi << 32 | wave_exec_lo),
1872             ((uint64_t)wave_inst_dw1 << 32 | wave_inst_dw0),
1873             wave_ib_sts);
1874     }
1875 }
1876
1877 static void gfx_v9_4_2_query_sq_timeout_status(struct amdgpu_device *adev)
1878 {
1879     uint32_t se_idx, sh_idx, cu_idx;
1880     uint32_t status;
1881
1882     mutex_lock(&adev->grbm_idx_mutex);
1883     for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines;
1884          se_idx++) {
1885         for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se;
1886              sh_idx++) {
1887             for (cu_idx = 0;
1888                  cu_idx < adev->gfx.config.max_cu_per_sh;
1889                  cu_idx++) {
1890                 gfx_v9_4_2_select_se_sh(adev, se_idx, sh_idx,
1891                             cu_idx);
1892                 status = RREG32_SOC15(GC, 0,
1893                               regSQ_TIMEOUT_STATUS);
1894                 if (status != 0) {
1895                     dev_info(
1896                         adev->dev,
1897                         "GFX Watchdog Timeout: SE %d, SH %d, CU %d\n",
1898                         se_idx, sh_idx, cu_idx);
1899                     gfx_v9_4_2_log_cu_timeout_status(
1900                         adev, status);
1901                 }
1902                 /* clear old status */
1903                 WREG32_SOC15(GC, 0, regSQ_TIMEOUT_STATUS, 0);
1904             }
1905         }
1906     }
1907     gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1908     mutex_unlock(&adev->grbm_idx_mutex);
1909 }
1910
1911 static void gfx_v9_4_2_reset_sq_timeout_status(struct amdgpu_device *adev)
1912 {
1913     uint32_t se_idx, sh_idx, cu_idx;
1914
1915     mutex_lock(&adev->grbm_idx_mutex);
1916     for (se_idx = 0; se_idx < adev->gfx.config.max_shader_engines;
1917          se_idx++) {
1918         for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se;
1919              sh_idx++) {
1920             for (cu_idx = 0;
1921                  cu_idx < adev->gfx.config.max_cu_per_sh;
1922                  cu_idx++) {
1923                 gfx_v9_4_2_select_se_sh(adev, se_idx, sh_idx,
1924                             cu_idx);
1925                 WREG32_SOC15(GC, 0, regSQ_TIMEOUT_STATUS, 0);
1926             }
1927         }
1928     }
1929     gfx_v9_4_2_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1930     mutex_unlock(&adev->grbm_idx_mutex);
1931 }
1932
1933 static bool gfx_v9_4_2_query_uctl2_poison_status(struct amdgpu_device *adev)
1934 {
1935     u32 status = 0;
1936     struct amdgpu_vmhub *hub;
1937
1938     hub = &adev->vmhub[AMDGPU_GFXHUB_0];
1939     status = RREG32(hub->vm_l2_pro_fault_status);
1940     /* reset page fault status */
1941     WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
1942
1943     return REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, FED);
1944 }
1945
1946 struct amdgpu_ras_block_hw_ops  gfx_v9_4_2_ras_ops = {
1947         .ras_error_inject = &gfx_v9_4_2_ras_error_inject,
1948         .query_ras_error_count = &gfx_v9_4_2_query_ras_error_count,
1949         .reset_ras_error_count = &gfx_v9_4_2_reset_ras_error_count,
1950         .query_ras_error_status = &gfx_v9_4_2_query_ras_error_status,
1951         .reset_ras_error_status = &gfx_v9_4_2_reset_ras_error_status,
1952 };
1953
1954 struct amdgpu_gfx_ras gfx_v9_4_2_ras = {
1955     .ras_block = {
1956         .hw_ops = &gfx_v9_4_2_ras_ops,
1957     },
1958     .enable_watchdog_timer = &gfx_v9_4_2_enable_watchdog_timer,
1959     .query_utcl2_poison_status = gfx_v9_4_2_query_uctl2_poison_status,
1960 };