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OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2020 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #include <linux/kernel.h>
0025 
0026 #include "amdgpu.h"
0027 #include "amdgpu_gfx.h"
0028 #include "soc15.h"
0029 #include "soc15d.h"
0030 #include "amdgpu_atomfirmware.h"
0031 #include "amdgpu_pm.h"
0032 
0033 #include "gc/gc_9_4_1_offset.h"
0034 #include "gc/gc_9_4_1_sh_mask.h"
0035 #include "soc15_common.h"
0036 
0037 #include "gfx_v9_4.h"
0038 #include "amdgpu_ras.h"
0039 
0040 static const struct soc15_reg_entry gfx_v9_4_edc_counter_regs[] = {
0041     /* CPC */
0042     { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT), 0, 1, 1 },
0043     { SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT), 0, 1, 1 },
0044     /* DC */
0045     { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT), 0, 1, 1 },
0046     { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT), 0, 1, 1 },
0047     { SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT), 0, 1, 1 },
0048     /* CPF */
0049     { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT), 0, 1, 1 },
0050     { SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT), 0, 1, 1 },
0051     /* GDS */
0052     { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT), 0, 1, 1 },
0053     { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT), 0, 1, 1 },
0054     { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_DED), 0, 1, 1 },
0055     { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT), 0, 1, 1 },
0056     { SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT), 0, 1, 1 },
0057     /* SPI */
0058     { SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT), 0, 4, 1 },
0059     /* SQ */
0060     { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 8, 16 },
0061     { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_DED_CNT), 0, 8, 16 },
0062     { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_INFO), 0, 8, 16 },
0063     { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT), 0, 8, 16 },
0064     /* SQC */
0065     { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT), 0, 4, 6 },
0066     { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2), 0, 4, 6 },
0067     { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3), 0, 4, 6 },
0068     { SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3), 0, 4, 6 },
0069     /* TA */
0070     { SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT), 0, 4, 16 },
0071     /* TCA */
0072     { SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT), 0, 1, 2 },
0073     /* TCC */
0074     { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT), 0, 1, 16 },
0075     { SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2), 0, 1, 16 },
0076     /* TCI */
0077     { SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT), 0, 1, 72 },
0078     /* TCP */
0079     { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW), 0, 4, 16 },
0080     { SOC15_REG_ENTRY(GC, 0, mmTCP_ATC_EDC_GATCL1_CNT), 0, 4, 16 },
0081     { SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT), 0, 4, 16 },
0082     /* TD */
0083     { SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT), 0, 4, 16 },
0084     /* GCEA */
0085     { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT), 0, 1, 32 },
0086     { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2), 0, 1, 32 },
0087     { SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 1, 32 },
0088     /* RLC */
0089     { SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT), 0, 1, 1 },
0090     { SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2), 0, 1, 1 },
0091 };
0092 
0093 static void gfx_v9_4_select_se_sh(struct amdgpu_device *adev, u32 se_num,
0094                   u32 sh_num, u32 instance)
0095 {
0096     u32 data;
0097 
0098     if (instance == 0xffffffff)
0099         data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
0100                      INSTANCE_BROADCAST_WRITES, 1);
0101     else
0102         data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
0103                      instance);
0104 
0105     if (se_num == 0xffffffff)
0106         data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
0107                      1);
0108     else
0109         data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
0110 
0111     if (sh_num == 0xffffffff)
0112         data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES,
0113                      1);
0114     else
0115         data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
0116 
0117     WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data);
0118 }
0119 
0120 static const struct soc15_ras_field_entry gfx_v9_4_ras_fields[] = {
0121     /* CPC */
0122     { "CPC_SCRATCH", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_SCRATCH_CNT),
0123       SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, SEC_COUNT),
0124       SOC15_REG_FIELD(CPC_EDC_SCRATCH_CNT, DED_COUNT) },
0125     { "CPC_UCODE", SOC15_REG_ENTRY(GC, 0, mmCPC_EDC_UCODE_CNT),
0126       SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, SEC_COUNT),
0127       SOC15_REG_FIELD(CPC_EDC_UCODE_CNT, DED_COUNT) },
0128     { "CPC_DC_STATE_RAM_ME1", SOC15_REG_ENTRY(GC, 0, mmDC_EDC_STATE_CNT),
0129       SOC15_REG_FIELD(DC_EDC_STATE_CNT, SEC_COUNT_ME1),
0130       SOC15_REG_FIELD(DC_EDC_STATE_CNT, DED_COUNT_ME1) },
0131     { "CPC_DC_CSINVOC_RAM_ME1",
0132       SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
0133       SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, SEC_COUNT_ME1),
0134       SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, DED_COUNT_ME1) },
0135     { "CPC_DC_RESTORE_RAM_ME1",
0136       SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
0137       SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, SEC_COUNT_ME1),
0138       SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, DED_COUNT_ME1) },
0139     { "CPC_DC_CSINVOC_RAM1_ME1",
0140       SOC15_REG_ENTRY(GC, 0, mmDC_EDC_CSINVOC_CNT),
0141       SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, SEC_COUNT1_ME1),
0142       SOC15_REG_FIELD(DC_EDC_CSINVOC_CNT, DED_COUNT1_ME1) },
0143     { "CPC_DC_RESTORE_RAM1_ME1",
0144       SOC15_REG_ENTRY(GC, 0, mmDC_EDC_RESTORE_CNT),
0145       SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, SEC_COUNT1_ME1),
0146       SOC15_REG_FIELD(DC_EDC_RESTORE_CNT, DED_COUNT1_ME1) },
0147 
0148     /* CPF */
0149     { "CPF_ROQ_ME2", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
0150       SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, SEC_COUNT_ME2),
0151       SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, DED_COUNT_ME2) },
0152     { "CPF_ROQ_ME1", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_ROQ_CNT),
0153       SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, SEC_COUNT_ME1),
0154       SOC15_REG_FIELD(CPF_EDC_ROQ_CNT, DED_COUNT_ME1) },
0155     { "CPF_TCIU_TAG", SOC15_REG_ENTRY(GC, 0, mmCPF_EDC_TAG_CNT),
0156       SOC15_REG_FIELD(CPF_EDC_TAG_CNT, SEC_COUNT),
0157       SOC15_REG_FIELD(CPF_EDC_TAG_CNT, DED_COUNT) },
0158 
0159     /* GDS */
0160     { "GDS_GRBM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_GRBM_CNT),
0161       SOC15_REG_FIELD(GDS_EDC_GRBM_CNT, SEC),
0162       SOC15_REG_FIELD(GDS_EDC_GRBM_CNT, DED) },
0163     { "GDS_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_CNT),
0164       SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_SEC),
0165       SOC15_REG_FIELD(GDS_EDC_CNT, GDS_MEM_DED) },
0166     { "GDS_PHY_CMD_RAM_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
0167       SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_SEC),
0168       SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_CMD_RAM_MEM_DED) },
0169     { "GDS_PHY_DATA_RAM_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
0170       SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_SEC),
0171       SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, PHY_DATA_RAM_MEM_DED) },
0172     { "GDS_ME0_CS_PIPE_MEM", SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PHY_CNT),
0173       SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_SEC),
0174       SOC15_REG_FIELD(GDS_EDC_OA_PHY_CNT, ME0_CS_PIPE_MEM_DED) },
0175     { "GDS_ME1_PIPE0_PIPE_MEM",
0176       SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
0177       SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_SEC),
0178       SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE0_PIPE_MEM_DED) },
0179     { "GDS_ME1_PIPE1_PIPE_MEM",
0180       SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
0181       SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_SEC),
0182       SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE1_PIPE_MEM_DED) },
0183     { "GDS_ME1_PIPE2_PIPE_MEM",
0184       SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
0185       SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_SEC),
0186       SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE2_PIPE_MEM_DED) },
0187     { "GDS_ME1_PIPE3_PIPE_MEM",
0188       SOC15_REG_ENTRY(GC, 0, mmGDS_EDC_OA_PIPE_CNT),
0189       SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_SEC),
0190       SOC15_REG_FIELD(GDS_EDC_OA_PIPE_CNT, ME1_PIPE3_PIPE_MEM_DED) },
0191 
0192     /* SPI */
0193     { "SPI_SR_MEM", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
0194       SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_SEC_COUNT),
0195       SOC15_REG_FIELD(SPI_EDC_CNT, SPI_SR_MEM_DED_COUNT) },
0196     { "SPI_GDS_EXPREQ", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
0197       SOC15_REG_FIELD(SPI_EDC_CNT, SPI_GDS_EXPREQ_SEC_COUNT),
0198       SOC15_REG_FIELD(SPI_EDC_CNT, SPI_GDS_EXPREQ_DED_COUNT) },
0199     { "SPI_WB_GRANT_30", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
0200       SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_30_SEC_COUNT),
0201       SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_30_DED_COUNT) },
0202     { "SPI_WB_GRANT_61", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
0203       SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_61_SEC_COUNT),
0204       SOC15_REG_FIELD(SPI_EDC_CNT, SPI_WB_GRANT_61_DED_COUNT) },
0205     { "SPI_LIFE_CNT", SOC15_REG_ENTRY(GC, 0, mmSPI_EDC_CNT),
0206       SOC15_REG_FIELD(SPI_EDC_CNT, SPI_LIFE_CNT_SEC_COUNT),
0207       SOC15_REG_FIELD(SPI_EDC_CNT, SPI_LIFE_CNT_DED_COUNT) },
0208 
0209     /* SQ */
0210     { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
0211       SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_SEC_COUNT),
0212       SOC15_REG_FIELD(SQ_EDC_CNT, SGPR_DED_COUNT) },
0213     { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
0214       SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_SEC_COUNT),
0215       SOC15_REG_FIELD(SQ_EDC_CNT, LDS_D_DED_COUNT) },
0216     { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
0217       SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_SEC_COUNT),
0218       SOC15_REG_FIELD(SQ_EDC_CNT, LDS_I_DED_COUNT) },
0219     { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
0220       SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_SEC_COUNT),
0221       SOC15_REG_FIELD(SQ_EDC_CNT, VGPR0_DED_COUNT) },
0222     { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
0223       SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_SEC_COUNT),
0224       SOC15_REG_FIELD(SQ_EDC_CNT, VGPR1_DED_COUNT) },
0225     { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
0226       SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_SEC_COUNT),
0227       SOC15_REG_FIELD(SQ_EDC_CNT, VGPR2_DED_COUNT) },
0228     { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
0229       SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_SEC_COUNT),
0230       SOC15_REG_FIELD(SQ_EDC_CNT, VGPR3_DED_COUNT) },
0231 
0232     /* SQC */
0233     { "SQC_INST_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
0234       SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_SEC_COUNT),
0235       SOC15_REG_FIELD(SQC_EDC_CNT2, INST_UTCL1_LFIFO_DED_COUNT) },
0236     { "SQC_DATA_CU0_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
0237       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_SEC_COUNT),
0238       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_WRITE_DATA_BUF_DED_COUNT) },
0239     { "SQC_DATA_CU0_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
0240       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_SEC_COUNT),
0241       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU0_UTCL1_LFIFO_DED_COUNT) },
0242     { "SQC_DATA_CU1_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
0243       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_SEC_COUNT),
0244       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_WRITE_DATA_BUF_DED_COUNT) },
0245     { "SQC_DATA_CU1_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
0246       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_SEC_COUNT),
0247       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU1_UTCL1_LFIFO_DED_COUNT) },
0248     { "SQC_DATA_CU2_WRITE_DATA_BUF", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
0249       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_SEC_COUNT),
0250       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_WRITE_DATA_BUF_DED_COUNT) },
0251     { "SQC_DATA_CU2_UTCL1_LFIFO", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT),
0252       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_SEC_COUNT),
0253       SOC15_REG_FIELD(SQC_EDC_CNT, DATA_CU2_UTCL1_LFIFO_DED_COUNT) },
0254     { "SQC_INST_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
0255       SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_SEC_COUNT),
0256       SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_TAG_RAM_DED_COUNT) },
0257     { "SQC_INST_BANKA_UTCL1_MISS_FIFO",
0258       SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
0259       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
0260               INST_BANKA_UTCL1_MISS_FIFO_SEC_COUNT),
0261       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
0262               INST_BANKA_UTCL1_MISS_FIFO_DED_COUNT) },
0263     { "SQC_INST_BANKA_MISS_FIFO",
0264       SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
0265       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKA_MISS_FIFO_SEC_COUNT),
0266       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
0267               INST_BANKA_MISS_FIFO_DED_COUNT) },
0268     { "SQC_INST_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
0269       SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_SEC_COUNT),
0270       SOC15_REG_FIELD(SQC_EDC_CNT2, INST_BANKA_BANK_RAM_DED_COUNT) },
0271     { "SQC_DATA_BANKA_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
0272       SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_SEC_COUNT),
0273       SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_TAG_RAM_DED_COUNT) },
0274     { "SQC_DATA_BANKA_HIT_FIFO",
0275       SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
0276       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_HIT_FIFO_SEC_COUNT),
0277       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_HIT_FIFO_DED_COUNT) },
0278     { "SQC_DATA_BANKA_MISS_FIFO",
0279       SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
0280       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKA_MISS_FIFO_SEC_COUNT),
0281       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
0282               DATA_BANKA_MISS_FIFO_DED_COUNT) },
0283     { "SQC_DATA_BANKA_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT2),
0284       SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_SEC_COUNT),
0285       SOC15_REG_FIELD(SQC_EDC_CNT2, DATA_BANKA_BANK_RAM_DED_COUNT) },
0286     { "SQC_INST_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
0287       SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_SEC_COUNT),
0288       SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_TAG_RAM_DED_COUNT) },
0289     { "SQC_INST_BANKB_UTCL1_MISS_FIFO",
0290       SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
0291       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
0292               INST_BANKB_UTCL1_MISS_FIFO_SEC_COUNT),
0293       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
0294               INST_BANKB_UTCL1_MISS_FIFO_DED_COUNT) },
0295     { "SQC_INST_BANKB_MISS_FIFO",
0296       SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
0297       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, INST_BANKB_MISS_FIFO_SEC_COUNT),
0298       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
0299               INST_BANKB_MISS_FIFO_DED_COUNT) },
0300     { "SQC_INST_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
0301       SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_SEC_COUNT),
0302       SOC15_REG_FIELD(SQC_EDC_CNT3, INST_BANKB_BANK_RAM_DED_COUNT) },
0303     { "SQC_DATA_BANKB_TAG_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
0304       SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_SEC_COUNT),
0305       SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_TAG_RAM_DED_COUNT) },
0306     { "SQC_DATA_BANKB_HIT_FIFO",
0307       SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
0308       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_HIT_FIFO_SEC_COUNT),
0309       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_HIT_FIFO_DED_COUNT) },
0310     { "SQC_DATA_BANKB_MISS_FIFO",
0311       SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_PARITY_CNT3),
0312       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3, DATA_BANKB_MISS_FIFO_SEC_COUNT),
0313       SOC15_REG_FIELD(SQC_EDC_PARITY_CNT3,
0314               DATA_BANKB_MISS_FIFO_DED_COUNT) },
0315     { "SQC_DATA_BANKB_BANK_RAM", SOC15_REG_ENTRY(GC, 0, mmSQC_EDC_CNT3),
0316       SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_SEC_COUNT),
0317       SOC15_REG_FIELD(SQC_EDC_CNT3, DATA_BANKB_BANK_RAM_DED_COUNT) },
0318 
0319     /* TA */
0320     { "TA_FS_DFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
0321       SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_SEC_COUNT),
0322       SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_DFIFO_DED_COUNT) },
0323     { "TA_FS_AFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
0324       SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_SEC_COUNT),
0325       SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_AFIFO_DED_COUNT) },
0326     { "TA_FL_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
0327       SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_SEC_COUNT),
0328       SOC15_REG_FIELD(TA_EDC_CNT, TA_FL_LFIFO_DED_COUNT) },
0329     { "TA_FX_LFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
0330       SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_SEC_COUNT),
0331       SOC15_REG_FIELD(TA_EDC_CNT, TA_FX_LFIFO_DED_COUNT) },
0332     { "TA_FS_CFIFO", SOC15_REG_ENTRY(GC, 0, mmTA_EDC_CNT),
0333       SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_SEC_COUNT),
0334       SOC15_REG_FIELD(TA_EDC_CNT, TA_FS_CFIFO_DED_COUNT) },
0335 
0336     /* TCA */
0337     { "TCA_HOLE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT),
0338       SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_SEC_COUNT),
0339       SOC15_REG_FIELD(TCA_EDC_CNT, HOLE_FIFO_DED_COUNT) },
0340     { "TCA_REQ_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCA_EDC_CNT),
0341       SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_SEC_COUNT),
0342       SOC15_REG_FIELD(TCA_EDC_CNT, REQ_FIFO_DED_COUNT) },
0343 
0344     /* TCC */
0345     { "TCC_CACHE_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
0346       SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_SEC_COUNT),
0347       SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DATA_DED_COUNT) },
0348     { "TCC_CACHE_DIRTY", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
0349       SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_SEC_COUNT),
0350       SOC15_REG_FIELD(TCC_EDC_CNT, CACHE_DIRTY_DED_COUNT) },
0351     { "TCC_HIGH_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
0352       SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_SEC_COUNT),
0353       SOC15_REG_FIELD(TCC_EDC_CNT, HIGH_RATE_TAG_DED_COUNT) },
0354     { "TCC_LOW_RATE_TAG", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
0355       SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_SEC_COUNT),
0356       SOC15_REG_FIELD(TCC_EDC_CNT, LOW_RATE_TAG_DED_COUNT) },
0357     { "TCC_IN_USE_DEC", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
0358       SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_DEC_SEC_COUNT),
0359       SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_DEC_DED_COUNT) },
0360     { "TCC_IN_USE_TRANSFER", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
0361       SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_TRANSFER_SEC_COUNT),
0362       SOC15_REG_FIELD(TCC_EDC_CNT2, IN_USE_TRANSFER_DED_COUNT) },
0363     { "TCC_RETURN_DATA", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
0364       SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_DATA_SEC_COUNT),
0365       SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_DATA_DED_COUNT) },
0366     { "TCC_RETURN_CONTROL", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
0367       SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_CONTROL_SEC_COUNT),
0368       SOC15_REG_FIELD(TCC_EDC_CNT2, RETURN_CONTROL_DED_COUNT) },
0369     { "TCC_UC_ATOMIC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
0370       SOC15_REG_FIELD(TCC_EDC_CNT2, UC_ATOMIC_FIFO_SEC_COUNT),
0371       SOC15_REG_FIELD(TCC_EDC_CNT2, UC_ATOMIC_FIFO_DED_COUNT) },
0372     { "TCC_WRITE_RETURN", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
0373       SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_SEC_COUNT),
0374       SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_RETURN_DED_COUNT) },
0375     { "TCC_WRITE_CACHE_READ", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
0376       SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_SEC_COUNT),
0377       SOC15_REG_FIELD(TCC_EDC_CNT2, WRITE_CACHE_READ_DED_COUNT) },
0378     { "TCC_SRC_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
0379       SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_SEC_COUNT),
0380       SOC15_REG_FIELD(TCC_EDC_CNT, SRC_FIFO_DED_COUNT) },
0381     { "TCC_CACHE_TAG_PROBE_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT2),
0382       SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_SEC_COUNT),
0383       SOC15_REG_FIELD(TCC_EDC_CNT2, CACHE_TAG_PROBE_FIFO_DED_COUNT) },
0384     { "TCC_LATENCY_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
0385       SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_SEC_COUNT),
0386       SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_DED_COUNT) },
0387     { "TCC_LATENCY_FIFO_NEXT_RAM", SOC15_REG_ENTRY(GC, 0, mmTCC_EDC_CNT),
0388       SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_NEXT_RAM_SEC_COUNT),
0389       SOC15_REG_FIELD(TCC_EDC_CNT, LATENCY_FIFO_NEXT_RAM_DED_COUNT) },
0390 
0391     /* TCI */
0392     { "TCI_WRITE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCI_EDC_CNT),
0393       SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_SEC_COUNT),
0394       SOC15_REG_FIELD(TCI_EDC_CNT, WRITE_RAM_DED_COUNT) },
0395 
0396     /* TCP */
0397     { "TCP_CACHE_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
0398       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_SEC_COUNT),
0399       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CACHE_RAM_DED_COUNT) },
0400     { "TCP_LFIFO_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
0401       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_SEC_COUNT),
0402       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, LFIFO_RAM_DED_COUNT) },
0403     { "TCP_CMD_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
0404       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_SEC_COUNT),
0405       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, CMD_FIFO_DED_COUNT) },
0406     { "TCP_VM_FIFO", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
0407       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_SEC_COUNT),
0408       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, VM_FIFO_DED_COUNT) },
0409     { "TCP_DB_RAM", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
0410       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, DB_RAM_SED_COUNT), 0, 0 },
0411     { "TCP_UTCL1_LFIFO0", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
0412       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_SEC_COUNT),
0413       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO0_DED_COUNT) },
0414     { "TCP_UTCL1_LFIFO1", SOC15_REG_ENTRY(GC, 0, mmTCP_EDC_CNT_NEW),
0415       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_SEC_COUNT),
0416       SOC15_REG_FIELD(TCP_EDC_CNT_NEW, UTCL1_LFIFO1_DED_COUNT) },
0417 
0418     /* TD */
0419     { "TD_SS_FIFO_LO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
0420       SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_SEC_COUNT),
0421       SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_LO_DED_COUNT) },
0422     { "TD_SS_FIFO_HI", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
0423       SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_SEC_COUNT),
0424       SOC15_REG_FIELD(TD_EDC_CNT, SS_FIFO_HI_DED_COUNT) },
0425     { "TD_CS_FIFO", SOC15_REG_ENTRY(GC, 0, mmTD_EDC_CNT),
0426       SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_SEC_COUNT),
0427       SOC15_REG_FIELD(TD_EDC_CNT, CS_FIFO_DED_COUNT) },
0428 
0429     /* EA */
0430     { "EA_DRAMRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
0431       SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
0432       SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT) },
0433     { "EA_DRAMWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
0434       SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
0435       SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT) },
0436     { "EA_DRAMWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
0437       SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
0438       SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT) },
0439     { "EA_RRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
0440       SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
0441       SOC15_REG_FIELD(GCEA_EDC_CNT, RRET_TAGMEM_DED_COUNT) },
0442     { "EA_WRET_TAGMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
0443       SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
0444       SOC15_REG_FIELD(GCEA_EDC_CNT, WRET_TAGMEM_DED_COUNT) },
0445     { "EA_GMIRD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
0446       SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
0447       SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT) },
0448     { "EA_GMIWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
0449       SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
0450       SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT) },
0451     { "EA_GMIWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
0452       SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
0453       SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT) },
0454     { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
0455       SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT), 0, 0 },
0456     { "EA_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
0457       SOC15_REG_FIELD(GCEA_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT) },
0458     { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
0459       SOC15_REG_FIELD(GCEA_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT), 0, 0 },
0460     { "EA_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
0461       SOC15_REG_FIELD(GCEA_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT) },
0462     { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
0463       SOC15_REG_FIELD(GCEA_EDC_CNT, IORD_CMDMEM_SED_COUNT), 0, 0 },
0464     { "EA_IORD_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
0465       SOC15_REG_FIELD(GCEA_EDC_CNT3, IORD_CMDMEM_DED_COUNT) },
0466     { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
0467       SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_CMDMEM_SED_COUNT), 0, 0 },
0468     { "EA_IOWR_CMDMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
0469       SOC15_REG_FIELD(GCEA_EDC_CNT3, IOWR_CMDMEM_DED_COUNT) },
0470     { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
0471       SOC15_REG_FIELD(GCEA_EDC_CNT, IOWR_DATAMEM_SED_COUNT), 0, 0 },
0472     { "EA_IOWR_DATAMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
0473       SOC15_REG_FIELD(GCEA_EDC_CNT3, IOWR_DATAMEM_DED_COUNT) },
0474     { "EA_GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
0475       SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT), 0, 0 },
0476     { "EA_GMIRD_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
0477       SOC15_REG_FIELD(GCEA_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT) },
0478     { "EA_GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
0479       SOC15_REG_FIELD(GCEA_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT), 0, 0 },
0480     { "EA_GMIWR_PAGEMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
0481       SOC15_REG_FIELD(GCEA_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT) },
0482     { "EA_MAM_D0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
0483       SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_SED_COUNT),
0484       SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D0MEM_DED_COUNT) },
0485     { "EA_MAM_D1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
0486       SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_SED_COUNT),
0487       SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D1MEM_DED_COUNT) },
0488     { "EA_MAM_D2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
0489       SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_SED_COUNT),
0490       SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D2MEM_DED_COUNT) },
0491     { "EA_MAM_D3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT2),
0492       SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_SED_COUNT),
0493       SOC15_REG_FIELD(GCEA_EDC_CNT2, MAM_D3MEM_DED_COUNT) },
0494     { "EA_MAM_A0MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3),
0495       SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A0MEM_SEC_COUNT),
0496       SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A0MEM_DED_COUNT) },
0497     { "EA_MAM_A1MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3),
0498       SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A1MEM_SEC_COUNT),
0499       SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A1MEM_DED_COUNT) },
0500     { "EA_MAM_A2MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3),
0501       SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A2MEM_SEC_COUNT),
0502       SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A2MEM_DED_COUNT) },
0503     { "EA_MAM_A3MEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3),
0504       SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A3MEM_SEC_COUNT),
0505       SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_A3MEM_DED_COUNT) },
0506     { "EA_MAM_AFMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT),
0507       SOC15_REG_FIELD(GCEA_EDC_CNT, MAM_AFMEM_SEC_COUNT), 0, 0 },
0508     { "EA_MAM_AFMEM", SOC15_REG_ENTRY(GC, 0, mmGCEA_EDC_CNT3), 0, 0,
0509       SOC15_REG_FIELD(GCEA_EDC_CNT3, MAM_AFMEM_DED_COUNT) },
0510 
0511     /* RLC */
0512     { "RLCG_INSTR_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
0513       SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_INSTR_RAM_SEC_COUNT),
0514       SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_INSTR_RAM_DED_COUNT) },
0515     { "RLCG_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
0516       SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_SCRATCH_RAM_SEC_COUNT),
0517       SOC15_REG_FIELD(RLC_EDC_CNT, RLCG_SCRATCH_RAM_DED_COUNT) },
0518     { "RLCV_INSTR_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
0519       SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_INSTR_RAM_SEC_COUNT),
0520       SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_INSTR_RAM_DED_COUNT) },
0521     { "RLCV_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
0522       SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_SCRATCH_RAM_SEC_COUNT),
0523       SOC15_REG_FIELD(RLC_EDC_CNT, RLCV_SCRATCH_RAM_DED_COUNT) },
0524     { "RLC_TCTAG_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
0525       SOC15_REG_FIELD(RLC_EDC_CNT, RLC_TCTAG_RAM_SEC_COUNT),
0526       SOC15_REG_FIELD(RLC_EDC_CNT, RLC_TCTAG_RAM_DED_COUNT) },
0527     { "RLC_SPM_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
0528       SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SPM_SCRATCH_RAM_SEC_COUNT),
0529       SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SPM_SCRATCH_RAM_DED_COUNT) },
0530     { "RLC_SRM_DATA_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
0531       SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_DATA_RAM_SEC_COUNT),
0532       SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_DATA_RAM_DED_COUNT) },
0533     { "RLC_SRM_ADDR_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT),
0534       SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_ADDR_RAM_SEC_COUNT),
0535       SOC15_REG_FIELD(RLC_EDC_CNT, RLC_SRM_ADDR_RAM_DED_COUNT) },
0536     { "RLC_SPM_SE0_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
0537       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE0_SCRATCH_RAM_SEC_COUNT),
0538       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE0_SCRATCH_RAM_DED_COUNT) },
0539     { "RLC_SPM_SE1_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
0540       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE1_SCRATCH_RAM_SEC_COUNT),
0541       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE1_SCRATCH_RAM_DED_COUNT) },
0542     { "RLC_SPM_SE2_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
0543       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE2_SCRATCH_RAM_SEC_COUNT),
0544       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE2_SCRATCH_RAM_DED_COUNT) },
0545     { "RLC_SPM_SE3_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
0546       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE3_SCRATCH_RAM_SEC_COUNT),
0547       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE3_SCRATCH_RAM_DED_COUNT) },
0548     { "RLC_SPM_SE4_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
0549       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE4_SCRATCH_RAM_SEC_COUNT),
0550       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE4_SCRATCH_RAM_DED_COUNT) },
0551     { "RLC_SPM_SE5_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
0552       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE5_SCRATCH_RAM_SEC_COUNT),
0553       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE5_SCRATCH_RAM_DED_COUNT) },
0554     { "RLC_SPM_SE6_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
0555       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE6_SCRATCH_RAM_SEC_COUNT),
0556       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE6_SCRATCH_RAM_DED_COUNT) },
0557     { "RLC_SPM_SE7_SCRATCH_RAM", SOC15_REG_ENTRY(GC, 0, mmRLC_EDC_CNT2),
0558       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE7_SCRATCH_RAM_SEC_COUNT),
0559       SOC15_REG_FIELD(RLC_EDC_CNT2, RLC_SPM_SE7_SCRATCH_RAM_DED_COUNT) },
0560 };
0561 
0562 static const char * const vml2_mems[] = {
0563     "UTC_VML2_BANK_CACHE_0_BIGK_MEM0",
0564     "UTC_VML2_BANK_CACHE_0_BIGK_MEM1",
0565     "UTC_VML2_BANK_CACHE_0_4K_MEM0",
0566     "UTC_VML2_BANK_CACHE_0_4K_MEM1",
0567     "UTC_VML2_BANK_CACHE_1_BIGK_MEM0",
0568     "UTC_VML2_BANK_CACHE_1_BIGK_MEM1",
0569     "UTC_VML2_BANK_CACHE_1_4K_MEM0",
0570     "UTC_VML2_BANK_CACHE_1_4K_MEM1",
0571     "UTC_VML2_BANK_CACHE_2_BIGK_MEM0",
0572     "UTC_VML2_BANK_CACHE_2_BIGK_MEM1",
0573     "UTC_VML2_BANK_CACHE_2_4K_MEM0",
0574     "UTC_VML2_BANK_CACHE_2_4K_MEM1",
0575     "UTC_VML2_BANK_CACHE_3_BIGK_MEM0",
0576     "UTC_VML2_BANK_CACHE_3_BIGK_MEM1",
0577     "UTC_VML2_BANK_CACHE_3_4K_MEM0",
0578     "UTC_VML2_BANK_CACHE_3_4K_MEM1",
0579     "UTC_VML2_IFIFO_GROUP0",
0580     "UTC_VML2_IFIFO_GROUP1",
0581     "UTC_VML2_IFIFO_GROUP2",
0582     "UTC_VML2_IFIFO_GROUP3",
0583     "UTC_VML2_IFIFO_GROUP4",
0584     "UTC_VML2_IFIFO_GROUP5",
0585     "UTC_VML2_IFIFO_GROUP6",
0586     "UTC_VML2_IFIFO_GROUP7",
0587     "UTC_VML2_IFIFO_GROUP8",
0588     "UTC_VML2_IFIFO_GROUP9",
0589     "UTC_VML2_IFIFO_GROUP10",
0590     "UTC_VML2_IFIFO_GROUP11",
0591     "UTC_VML2_IFIFO_GROUP12",
0592     "UTC_VML2_IFIFO_GROUP13",
0593     "UTC_VML2_IFIFO_GROUP14",
0594     "UTC_VML2_IFIFO_GROUP15",
0595     "UTC_VML2_IFIFO_GROUP16",
0596     "UTC_VML2_IFIFO_GROUP17",
0597     "UTC_VML2_IFIFO_GROUP18",
0598     "UTC_VML2_IFIFO_GROUP19",
0599     "UTC_VML2_IFIFO_GROUP20",
0600     "UTC_VML2_IFIFO_GROUP21",
0601     "UTC_VML2_IFIFO_GROUP22",
0602     "UTC_VML2_IFIFO_GROUP23",
0603     "UTC_VML2_IFIFO_GROUP24",
0604 };
0605 
0606 static const char * const vml2_walker_mems[] = {
0607     "UTC_VML2_CACHE_PDE0_MEM0",
0608     "UTC_VML2_CACHE_PDE0_MEM1",
0609     "UTC_VML2_CACHE_PDE1_MEM0",
0610     "UTC_VML2_CACHE_PDE1_MEM1",
0611     "UTC_VML2_CACHE_PDE2_MEM0",
0612     "UTC_VML2_CACHE_PDE2_MEM1",
0613     "UTC_VML2_RDIF_ARADDRS",
0614     "UTC_VML2_RDIF_LOG_FIFO",
0615     "UTC_VML2_QUEUE_REQ",
0616     "UTC_VML2_QUEUE_RET",
0617 };
0618 
0619 static const char * const utcl2_router_mems[] = {
0620     "UTCL2_ROUTER_GROUP0_VML2_REQ_FIFO0",
0621     "UTCL2_ROUTER_GROUP1_VML2_REQ_FIFO1",
0622     "UTCL2_ROUTER_GROUP2_VML2_REQ_FIFO2",
0623     "UTCL2_ROUTER_GROUP3_VML2_REQ_FIFO3",
0624     "UTCL2_ROUTER_GROUP4_VML2_REQ_FIFO4",
0625     "UTCL2_ROUTER_GROUP5_VML2_REQ_FIFO5",
0626     "UTCL2_ROUTER_GROUP6_VML2_REQ_FIFO6",
0627     "UTCL2_ROUTER_GROUP7_VML2_REQ_FIFO7",
0628     "UTCL2_ROUTER_GROUP8_VML2_REQ_FIFO8",
0629     "UTCL2_ROUTER_GROUP9_VML2_REQ_FIFO9",
0630     "UTCL2_ROUTER_GROUP10_VML2_REQ_FIFO10",
0631     "UTCL2_ROUTER_GROUP11_VML2_REQ_FIFO11",
0632     "UTCL2_ROUTER_GROUP12_VML2_REQ_FIFO12",
0633     "UTCL2_ROUTER_GROUP13_VML2_REQ_FIFO13",
0634     "UTCL2_ROUTER_GROUP14_VML2_REQ_FIFO14",
0635     "UTCL2_ROUTER_GROUP15_VML2_REQ_FIFO15",
0636     "UTCL2_ROUTER_GROUP16_VML2_REQ_FIFO16",
0637     "UTCL2_ROUTER_GROUP17_VML2_REQ_FIFO17",
0638     "UTCL2_ROUTER_GROUP18_VML2_REQ_FIFO18",
0639     "UTCL2_ROUTER_GROUP19_VML2_REQ_FIFO19",
0640     "UTCL2_ROUTER_GROUP20_VML2_REQ_FIFO20",
0641     "UTCL2_ROUTER_GROUP21_VML2_REQ_FIFO21",
0642     "UTCL2_ROUTER_GROUP22_VML2_REQ_FIFO22",
0643     "UTCL2_ROUTER_GROUP23_VML2_REQ_FIFO23",
0644     "UTCL2_ROUTER_GROUP24_VML2_REQ_FIFO24",
0645 };
0646 
0647 static const char * const atc_l2_cache_2m_mems[] = {
0648     "UTC_ATCL2_CACHE_2M_BANK0_WAY0_MEM",
0649     "UTC_ATCL2_CACHE_2M_BANK0_WAY1_MEM",
0650     "UTC_ATCL2_CACHE_2M_BANK1_WAY0_MEM",
0651     "UTC_ATCL2_CACHE_2M_BANK1_WAY1_MEM",
0652 };
0653 
0654 static const char * const atc_l2_cache_4k_mems[] = {
0655     "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0",
0656     "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1",
0657     "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2",
0658     "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3",
0659     "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4",
0660     "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5",
0661     "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6",
0662     "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7",
0663     "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0",
0664     "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1",
0665     "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2",
0666     "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3",
0667     "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4",
0668     "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5",
0669     "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6",
0670     "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7",
0671     "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0",
0672     "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1",
0673     "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2",
0674     "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3",
0675     "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4",
0676     "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5",
0677     "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6",
0678     "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7",
0679     "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0",
0680     "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1",
0681     "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2",
0682     "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3",
0683     "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4",
0684     "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5",
0685     "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6",
0686     "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7",
0687 };
0688 
0689 static int gfx_v9_4_query_utc_edc_status(struct amdgpu_device *adev,
0690                      struct ras_err_data *err_data)
0691 {
0692     uint32_t i, data;
0693     uint32_t sec_count, ded_count;
0694 
0695     WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, 255);
0696     WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL, 0);
0697     WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, 255);
0698     WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL, 0);
0699     WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, 255);
0700     WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL, 0);
0701 
0702     WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, 255);
0703     WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
0704     WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, 255);
0705     WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
0706 
0707     for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) {
0708         WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, i);
0709         data = RREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL);
0710 
0711         sec_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, SEC_COUNT);
0712         if (sec_count) {
0713             dev_info(adev->dev,
0714                  "Instance[%d]: SubBlock %s, SEC %d\n", i,
0715                  vml2_mems[i], sec_count);
0716             err_data->ce_count += sec_count;
0717         }
0718 
0719         ded_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, DED_COUNT);
0720         if (ded_count) {
0721             dev_info(adev->dev,
0722                  "Instance[%d]: SubBlock %s, DED %d\n", i,
0723                  vml2_mems[i], ded_count);
0724             err_data->ue_count += ded_count;
0725         }
0726     }
0727 
0728     for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) {
0729         WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, i);
0730         data = RREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL);
0731 
0732         sec_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL,
0733                       SEC_COUNT);
0734         if (sec_count) {
0735             dev_info(adev->dev,
0736                  "Instance[%d]: SubBlock %s, SEC %d\n", i,
0737                  vml2_walker_mems[i], sec_count);
0738             err_data->ce_count += sec_count;
0739         }
0740 
0741         ded_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL,
0742                       DED_COUNT);
0743         if (ded_count) {
0744             dev_info(adev->dev,
0745                  "Instance[%d]: SubBlock %s, DED %d\n", i,
0746                  vml2_walker_mems[i], ded_count);
0747             err_data->ue_count += ded_count;
0748         }
0749     }
0750 
0751     for (i = 0; i < ARRAY_SIZE(utcl2_router_mems); i++) {
0752         WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, i);
0753         data = RREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL);
0754 
0755         sec_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, SEC_COUNT);
0756         if (sec_count) {
0757             dev_info(adev->dev,
0758                  "Instance[%d]: SubBlock %s, SEC %d\n", i,
0759                  utcl2_router_mems[i], sec_count);
0760             err_data->ce_count += sec_count;
0761         }
0762 
0763         ded_count = REG_GET_FIELD(data, UTCL2_MEM_ECC_CNTL, DED_COUNT);
0764         if (ded_count) {
0765             dev_info(adev->dev,
0766                  "Instance[%d]: SubBlock %s, DED %d\n", i,
0767                  utcl2_router_mems[i], ded_count);
0768             err_data->ue_count += ded_count;
0769         }
0770     }
0771 
0772     for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) {
0773         WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, i);
0774         data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL);
0775 
0776         sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL,
0777                       SEC_COUNT);
0778         if (sec_count) {
0779             dev_info(adev->dev,
0780                  "Instance[%d]: SubBlock %s, SEC %d\n", i,
0781                  atc_l2_cache_2m_mems[i], sec_count);
0782             err_data->ce_count += sec_count;
0783         }
0784 
0785         ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_2M_DSM_CNTL,
0786                       DED_COUNT);
0787         if (ded_count) {
0788             dev_info(adev->dev,
0789                  "Instance[%d]: SubBlock %s, DED %d\n", i,
0790                  atc_l2_cache_2m_mems[i], ded_count);
0791             err_data->ue_count += ded_count;
0792         }
0793     }
0794 
0795     for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) {
0796         WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, i);
0797         data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_CNTL);
0798 
0799         sec_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL,
0800                       SEC_COUNT);
0801         if (sec_count) {
0802             dev_info(adev->dev,
0803                  "Instance[%d]: SubBlock %s, SEC %d\n", i,
0804                  atc_l2_cache_4k_mems[i], sec_count);
0805             err_data->ce_count += sec_count;
0806         }
0807 
0808         ded_count = REG_GET_FIELD(data, ATC_L2_CACHE_4K_DSM_CNTL,
0809                       DED_COUNT);
0810         if (ded_count) {
0811             dev_info(adev->dev,
0812                  "Instance[%d]: SubBlock %s, DED %d\n", i,
0813                  atc_l2_cache_4k_mems[i], ded_count);
0814             err_data->ue_count += ded_count;
0815         }
0816     }
0817 
0818     WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, 255);
0819     WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, 255);
0820     WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, 255);
0821     WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, 255);
0822     WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, 255);
0823 
0824     return 0;
0825 }
0826 
0827 static int gfx_v9_4_ras_error_count(struct amdgpu_device *adev,
0828                     const struct soc15_reg_entry *reg,
0829                     uint32_t se_id, uint32_t inst_id,
0830                     uint32_t value, uint32_t *sec_count,
0831                     uint32_t *ded_count)
0832 {
0833     uint32_t i;
0834     uint32_t sec_cnt, ded_cnt;
0835 
0836     for (i = 0; i < ARRAY_SIZE(gfx_v9_4_ras_fields); i++) {
0837         if (gfx_v9_4_ras_fields[i].reg_offset != reg->reg_offset ||
0838             gfx_v9_4_ras_fields[i].seg != reg->seg ||
0839             gfx_v9_4_ras_fields[i].inst != reg->inst)
0840             continue;
0841 
0842         sec_cnt = (value & gfx_v9_4_ras_fields[i].sec_count_mask) >>
0843               gfx_v9_4_ras_fields[i].sec_count_shift;
0844         if (sec_cnt) {
0845             dev_info(adev->dev,
0846                  "GFX SubBlock %s, Instance[%d][%d], SEC %d\n",
0847                  gfx_v9_4_ras_fields[i].name, se_id, inst_id,
0848                  sec_cnt);
0849             *sec_count += sec_cnt;
0850         }
0851 
0852         ded_cnt = (value & gfx_v9_4_ras_fields[i].ded_count_mask) >>
0853               gfx_v9_4_ras_fields[i].ded_count_shift;
0854         if (ded_cnt) {
0855             dev_info(adev->dev,
0856                  "GFX SubBlock %s, Instance[%d][%d], DED %d\n",
0857                  gfx_v9_4_ras_fields[i].name, se_id, inst_id,
0858                  ded_cnt);
0859             *ded_count += ded_cnt;
0860         }
0861     }
0862 
0863     return 0;
0864 }
0865 
0866 static void gfx_v9_4_query_ras_error_count(struct amdgpu_device *adev,
0867                       void *ras_error_status)
0868 {
0869     struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
0870     uint32_t sec_count = 0, ded_count = 0;
0871     uint32_t i, j, k;
0872     uint32_t reg_value;
0873 
0874     if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
0875         return;
0876 
0877     err_data->ue_count = 0;
0878     err_data->ce_count = 0;
0879 
0880     mutex_lock(&adev->grbm_idx_mutex);
0881 
0882     for (i = 0; i < ARRAY_SIZE(gfx_v9_4_edc_counter_regs); i++) {
0883         for (j = 0; j < gfx_v9_4_edc_counter_regs[i].se_num; j++) {
0884             for (k = 0; k < gfx_v9_4_edc_counter_regs[i].instance;
0885                  k++) {
0886                 gfx_v9_4_select_se_sh(adev, j, 0, k);
0887                 reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(
0888                     gfx_v9_4_edc_counter_regs[i]));
0889                 if (reg_value)
0890                     gfx_v9_4_ras_error_count(adev,
0891                         &gfx_v9_4_edc_counter_regs[i],
0892                         j, k, reg_value, &sec_count,
0893                         &ded_count);
0894             }
0895         }
0896     }
0897 
0898     err_data->ce_count += sec_count;
0899     err_data->ue_count += ded_count;
0900 
0901     gfx_v9_4_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
0902     mutex_unlock(&adev->grbm_idx_mutex);
0903 
0904     gfx_v9_4_query_utc_edc_status(adev, err_data);
0905 
0906 }
0907 
0908 static void gfx_v9_4_reset_ras_error_count(struct amdgpu_device *adev)
0909 {
0910     int i, j, k;
0911 
0912     if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
0913         return;
0914 
0915     mutex_lock(&adev->grbm_idx_mutex);
0916     for (i = 0; i < ARRAY_SIZE(gfx_v9_4_edc_counter_regs); i++) {
0917         for (j = 0; j < gfx_v9_4_edc_counter_regs[i].se_num; j++) {
0918             for (k = 0; k < gfx_v9_4_edc_counter_regs[i].instance;
0919                  k++) {
0920                 gfx_v9_4_select_se_sh(adev, j, 0x0, k);
0921                 RREG32(SOC15_REG_ENTRY_OFFSET(
0922                     gfx_v9_4_edc_counter_regs[i]));
0923             }
0924         }
0925     }
0926     WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
0927     mutex_unlock(&adev->grbm_idx_mutex);
0928 
0929     WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, 255);
0930     WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL, 0);
0931     WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, 255);
0932     WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL, 0);
0933     WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, 255);
0934     WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL, 0);
0935 
0936     WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, 255);
0937     WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
0938     WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, 255);
0939     WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
0940 
0941     for (i = 0; i < ARRAY_SIZE(vml2_mems); i++) {
0942         WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, i);
0943         RREG32_SOC15(GC, 0, mmVML2_MEM_ECC_CNTL);
0944     }
0945 
0946     for (i = 0; i < ARRAY_SIZE(vml2_walker_mems); i++) {
0947         WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, i);
0948         RREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_CNTL);
0949     }
0950 
0951     for (i = 0; i < ARRAY_SIZE(utcl2_router_mems); i++) {
0952         WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, i);
0953         RREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_CNTL);
0954     }
0955 
0956     for (i = 0; i < ARRAY_SIZE(atc_l2_cache_2m_mems); i++) {
0957         WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, i);
0958         RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL);
0959     }
0960 
0961     for (i = 0; i < ARRAY_SIZE(atc_l2_cache_4k_mems); i++) {
0962         WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, i);
0963         RREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_CNTL);
0964     }
0965 
0966     WREG32_SOC15(GC, 0, mmVML2_MEM_ECC_INDEX, 255);
0967     WREG32_SOC15(GC, 0, mmVML2_WALKER_MEM_ECC_INDEX, 255);
0968     WREG32_SOC15(GC, 0, mmUTCL2_MEM_ECC_INDEX, 255);
0969     WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_INDEX, 255);
0970     WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_DSM_INDEX, 255);
0971 }
0972 
0973 static int gfx_v9_4_ras_error_inject(struct amdgpu_device *adev,
0974                      void *inject_if)
0975 {
0976     struct ras_inject_if *info = (struct ras_inject_if *)inject_if;
0977     int ret;
0978     struct ta_ras_trigger_error_input block_info = { 0 };
0979 
0980     if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
0981         return -EINVAL;
0982 
0983     block_info.block_id = amdgpu_ras_block_to_ta(info->head.block);
0984     block_info.sub_block_index = info->head.sub_block_index;
0985     block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type);
0986     block_info.address = info->address;
0987     block_info.value = info->value;
0988 
0989     mutex_lock(&adev->grbm_idx_mutex);
0990     ret = psp_ras_trigger_error(&adev->psp, &block_info);
0991     mutex_unlock(&adev->grbm_idx_mutex);
0992 
0993     return ret;
0994 }
0995 
0996 static const struct soc15_reg_entry gfx_v9_4_ea_err_status_regs =
0997     { SOC15_REG_ENTRY(GC, 0, mmGCEA_ERR_STATUS), 0, 1, 32 };
0998 
0999 static void gfx_v9_4_query_ras_error_status(struct amdgpu_device *adev)
1000 {
1001     uint32_t i, j;
1002     uint32_t reg_value;
1003 
1004     if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX))
1005         return;
1006 
1007     mutex_lock(&adev->grbm_idx_mutex);
1008 
1009     for (i = 0; i < gfx_v9_4_ea_err_status_regs.se_num; i++) {
1010         for (j = 0; j < gfx_v9_4_ea_err_status_regs.instance;
1011              j++) {
1012             gfx_v9_4_select_se_sh(adev, i, 0, j);
1013             reg_value = RREG32(SOC15_REG_ENTRY_OFFSET(
1014                 gfx_v9_4_ea_err_status_regs));
1015             if (REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_STATUS) ||
1016                 REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_WRRSP_STATUS) ||
1017                 REG_GET_FIELD(reg_value, GCEA_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
1018                 /* SDP read/write error/parity error in FUE_IS_FATAL mode
1019                  * can cause system fatal error in arcturas. Harvest the error
1020                  * status before GPU reset */
1021                 dev_warn(adev->dev, "GCEA err detected at instance: %d, status: 0x%x!\n",
1022                         j, reg_value);
1023             }
1024         }
1025     }
1026 
1027     gfx_v9_4_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1028     mutex_unlock(&adev->grbm_idx_mutex);
1029 }
1030 
1031 
1032 const struct amdgpu_ras_block_hw_ops  gfx_v9_4_ras_ops = {
1033     .ras_error_inject = &gfx_v9_4_ras_error_inject,
1034     .query_ras_error_count = &gfx_v9_4_query_ras_error_count,
1035     .reset_ras_error_count = &gfx_v9_4_reset_ras_error_count,
1036     .query_ras_error_status = &gfx_v9_4_query_ras_error_status,
1037 };
1038 
1039 struct amdgpu_gfx_ras gfx_v9_4_ras = {
1040     .ras_block = {
1041         .hw_ops = &gfx_v9_4_ras_ops,
1042     },
1043 };
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