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0001 /*
0002  * Copyright 2015 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include <linux/firmware.h>
0024 #include <linux/module.h>
0025 
0026 #include "amdgpu.h"
0027 #include "amdgpu_ih.h"
0028 #include "amdgpu_gfx.h"
0029 #include "amdgpu_ucode.h"
0030 #include "clearstate_si.h"
0031 #include "bif/bif_3_0_d.h"
0032 #include "bif/bif_3_0_sh_mask.h"
0033 #include "oss/oss_1_0_d.h"
0034 #include "oss/oss_1_0_sh_mask.h"
0035 #include "gca/gfx_6_0_d.h"
0036 #include "gca/gfx_6_0_sh_mask.h"
0037 #include "gmc/gmc_6_0_d.h"
0038 #include "gmc/gmc_6_0_sh_mask.h"
0039 #include "dce/dce_6_0_d.h"
0040 #include "dce/dce_6_0_sh_mask.h"
0041 #include "gca/gfx_7_2_enum.h"
0042 #include "si_enums.h"
0043 #include "si.h"
0044 
0045 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
0046 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
0047 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
0048 
0049 MODULE_FIRMWARE("amdgpu/tahiti_pfp.bin");
0050 MODULE_FIRMWARE("amdgpu/tahiti_me.bin");
0051 MODULE_FIRMWARE("amdgpu/tahiti_ce.bin");
0052 MODULE_FIRMWARE("amdgpu/tahiti_rlc.bin");
0053 
0054 MODULE_FIRMWARE("amdgpu/pitcairn_pfp.bin");
0055 MODULE_FIRMWARE("amdgpu/pitcairn_me.bin");
0056 MODULE_FIRMWARE("amdgpu/pitcairn_ce.bin");
0057 MODULE_FIRMWARE("amdgpu/pitcairn_rlc.bin");
0058 
0059 MODULE_FIRMWARE("amdgpu/verde_pfp.bin");
0060 MODULE_FIRMWARE("amdgpu/verde_me.bin");
0061 MODULE_FIRMWARE("amdgpu/verde_ce.bin");
0062 MODULE_FIRMWARE("amdgpu/verde_rlc.bin");
0063 
0064 MODULE_FIRMWARE("amdgpu/oland_pfp.bin");
0065 MODULE_FIRMWARE("amdgpu/oland_me.bin");
0066 MODULE_FIRMWARE("amdgpu/oland_ce.bin");
0067 MODULE_FIRMWARE("amdgpu/oland_rlc.bin");
0068 
0069 MODULE_FIRMWARE("amdgpu/hainan_pfp.bin");
0070 MODULE_FIRMWARE("amdgpu/hainan_me.bin");
0071 MODULE_FIRMWARE("amdgpu/hainan_ce.bin");
0072 MODULE_FIRMWARE("amdgpu/hainan_rlc.bin");
0073 
0074 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
0075 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
0076 //static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
0077 static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
0078 
0079 #define ARRAY_MODE(x)                   ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
0080 #define PIPE_CONFIG(x)                  ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
0081 #define TILE_SPLIT(x)                   ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
0082 #define MICRO_TILE_MODE(x)              ((x) << 0)
0083 #define SAMPLE_SPLIT(x)                 ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
0084 #define BANK_WIDTH(x)                   ((x) << 14)
0085 #define BANK_HEIGHT(x)                  ((x) << 16)
0086 #define MACRO_TILE_ASPECT(x)                ((x) << 18)
0087 #define NUM_BANKS(x)                    ((x) << 20)
0088 
0089 static const u32 verde_rlc_save_restore_register_list[] =
0090 {
0091     (0x8000 << 16) | (0x98f4 >> 2),
0092     0x00000000,
0093     (0x8040 << 16) | (0x98f4 >> 2),
0094     0x00000000,
0095     (0x8000 << 16) | (0xe80 >> 2),
0096     0x00000000,
0097     (0x8040 << 16) | (0xe80 >> 2),
0098     0x00000000,
0099     (0x8000 << 16) | (0x89bc >> 2),
0100     0x00000000,
0101     (0x8040 << 16) | (0x89bc >> 2),
0102     0x00000000,
0103     (0x8000 << 16) | (0x8c1c >> 2),
0104     0x00000000,
0105     (0x8040 << 16) | (0x8c1c >> 2),
0106     0x00000000,
0107     (0x9c00 << 16) | (0x98f0 >> 2),
0108     0x00000000,
0109     (0x9c00 << 16) | (0xe7c >> 2),
0110     0x00000000,
0111     (0x8000 << 16) | (0x9148 >> 2),
0112     0x00000000,
0113     (0x8040 << 16) | (0x9148 >> 2),
0114     0x00000000,
0115     (0x9c00 << 16) | (0x9150 >> 2),
0116     0x00000000,
0117     (0x9c00 << 16) | (0x897c >> 2),
0118     0x00000000,
0119     (0x9c00 << 16) | (0x8d8c >> 2),
0120     0x00000000,
0121     (0x9c00 << 16) | (0xac54 >> 2),
0122     0X00000000,
0123     0x3,
0124     (0x9c00 << 16) | (0x98f8 >> 2),
0125     0x00000000,
0126     (0x9c00 << 16) | (0x9910 >> 2),
0127     0x00000000,
0128     (0x9c00 << 16) | (0x9914 >> 2),
0129     0x00000000,
0130     (0x9c00 << 16) | (0x9918 >> 2),
0131     0x00000000,
0132     (0x9c00 << 16) | (0x991c >> 2),
0133     0x00000000,
0134     (0x9c00 << 16) | (0x9920 >> 2),
0135     0x00000000,
0136     (0x9c00 << 16) | (0x9924 >> 2),
0137     0x00000000,
0138     (0x9c00 << 16) | (0x9928 >> 2),
0139     0x00000000,
0140     (0x9c00 << 16) | (0x992c >> 2),
0141     0x00000000,
0142     (0x9c00 << 16) | (0x9930 >> 2),
0143     0x00000000,
0144     (0x9c00 << 16) | (0x9934 >> 2),
0145     0x00000000,
0146     (0x9c00 << 16) | (0x9938 >> 2),
0147     0x00000000,
0148     (0x9c00 << 16) | (0x993c >> 2),
0149     0x00000000,
0150     (0x9c00 << 16) | (0x9940 >> 2),
0151     0x00000000,
0152     (0x9c00 << 16) | (0x9944 >> 2),
0153     0x00000000,
0154     (0x9c00 << 16) | (0x9948 >> 2),
0155     0x00000000,
0156     (0x9c00 << 16) | (0x994c >> 2),
0157     0x00000000,
0158     (0x9c00 << 16) | (0x9950 >> 2),
0159     0x00000000,
0160     (0x9c00 << 16) | (0x9954 >> 2),
0161     0x00000000,
0162     (0x9c00 << 16) | (0x9958 >> 2),
0163     0x00000000,
0164     (0x9c00 << 16) | (0x995c >> 2),
0165     0x00000000,
0166     (0x9c00 << 16) | (0x9960 >> 2),
0167     0x00000000,
0168     (0x9c00 << 16) | (0x9964 >> 2),
0169     0x00000000,
0170     (0x9c00 << 16) | (0x9968 >> 2),
0171     0x00000000,
0172     (0x9c00 << 16) | (0x996c >> 2),
0173     0x00000000,
0174     (0x9c00 << 16) | (0x9970 >> 2),
0175     0x00000000,
0176     (0x9c00 << 16) | (0x9974 >> 2),
0177     0x00000000,
0178     (0x9c00 << 16) | (0x9978 >> 2),
0179     0x00000000,
0180     (0x9c00 << 16) | (0x997c >> 2),
0181     0x00000000,
0182     (0x9c00 << 16) | (0x9980 >> 2),
0183     0x00000000,
0184     (0x9c00 << 16) | (0x9984 >> 2),
0185     0x00000000,
0186     (0x9c00 << 16) | (0x9988 >> 2),
0187     0x00000000,
0188     (0x9c00 << 16) | (0x998c >> 2),
0189     0x00000000,
0190     (0x9c00 << 16) | (0x8c00 >> 2),
0191     0x00000000,
0192     (0x9c00 << 16) | (0x8c14 >> 2),
0193     0x00000000,
0194     (0x9c00 << 16) | (0x8c04 >> 2),
0195     0x00000000,
0196     (0x9c00 << 16) | (0x8c08 >> 2),
0197     0x00000000,
0198     (0x8000 << 16) | (0x9b7c >> 2),
0199     0x00000000,
0200     (0x8040 << 16) | (0x9b7c >> 2),
0201     0x00000000,
0202     (0x8000 << 16) | (0xe84 >> 2),
0203     0x00000000,
0204     (0x8040 << 16) | (0xe84 >> 2),
0205     0x00000000,
0206     (0x8000 << 16) | (0x89c0 >> 2),
0207     0x00000000,
0208     (0x8040 << 16) | (0x89c0 >> 2),
0209     0x00000000,
0210     (0x8000 << 16) | (0x914c >> 2),
0211     0x00000000,
0212     (0x8040 << 16) | (0x914c >> 2),
0213     0x00000000,
0214     (0x8000 << 16) | (0x8c20 >> 2),
0215     0x00000000,
0216     (0x8040 << 16) | (0x8c20 >> 2),
0217     0x00000000,
0218     (0x8000 << 16) | (0x9354 >> 2),
0219     0x00000000,
0220     (0x8040 << 16) | (0x9354 >> 2),
0221     0x00000000,
0222     (0x9c00 << 16) | (0x9060 >> 2),
0223     0x00000000,
0224     (0x9c00 << 16) | (0x9364 >> 2),
0225     0x00000000,
0226     (0x9c00 << 16) | (0x9100 >> 2),
0227     0x00000000,
0228     (0x9c00 << 16) | (0x913c >> 2),
0229     0x00000000,
0230     (0x8000 << 16) | (0x90e0 >> 2),
0231     0x00000000,
0232     (0x8000 << 16) | (0x90e4 >> 2),
0233     0x00000000,
0234     (0x8000 << 16) | (0x90e8 >> 2),
0235     0x00000000,
0236     (0x8040 << 16) | (0x90e0 >> 2),
0237     0x00000000,
0238     (0x8040 << 16) | (0x90e4 >> 2),
0239     0x00000000,
0240     (0x8040 << 16) | (0x90e8 >> 2),
0241     0x00000000,
0242     (0x9c00 << 16) | (0x8bcc >> 2),
0243     0x00000000,
0244     (0x9c00 << 16) | (0x8b24 >> 2),
0245     0x00000000,
0246     (0x9c00 << 16) | (0x88c4 >> 2),
0247     0x00000000,
0248     (0x9c00 << 16) | (0x8e50 >> 2),
0249     0x00000000,
0250     (0x9c00 << 16) | (0x8c0c >> 2),
0251     0x00000000,
0252     (0x9c00 << 16) | (0x8e58 >> 2),
0253     0x00000000,
0254     (0x9c00 << 16) | (0x8e5c >> 2),
0255     0x00000000,
0256     (0x9c00 << 16) | (0x9508 >> 2),
0257     0x00000000,
0258     (0x9c00 << 16) | (0x950c >> 2),
0259     0x00000000,
0260     (0x9c00 << 16) | (0x9494 >> 2),
0261     0x00000000,
0262     (0x9c00 << 16) | (0xac0c >> 2),
0263     0x00000000,
0264     (0x9c00 << 16) | (0xac10 >> 2),
0265     0x00000000,
0266     (0x9c00 << 16) | (0xac14 >> 2),
0267     0x00000000,
0268     (0x9c00 << 16) | (0xae00 >> 2),
0269     0x00000000,
0270     (0x9c00 << 16) | (0xac08 >> 2),
0271     0x00000000,
0272     (0x9c00 << 16) | (0x88d4 >> 2),
0273     0x00000000,
0274     (0x9c00 << 16) | (0x88c8 >> 2),
0275     0x00000000,
0276     (0x9c00 << 16) | (0x88cc >> 2),
0277     0x00000000,
0278     (0x9c00 << 16) | (0x89b0 >> 2),
0279     0x00000000,
0280     (0x9c00 << 16) | (0x8b10 >> 2),
0281     0x00000000,
0282     (0x9c00 << 16) | (0x8a14 >> 2),
0283     0x00000000,
0284     (0x9c00 << 16) | (0x9830 >> 2),
0285     0x00000000,
0286     (0x9c00 << 16) | (0x9834 >> 2),
0287     0x00000000,
0288     (0x9c00 << 16) | (0x9838 >> 2),
0289     0x00000000,
0290     (0x9c00 << 16) | (0x9a10 >> 2),
0291     0x00000000,
0292     (0x8000 << 16) | (0x9870 >> 2),
0293     0x00000000,
0294     (0x8000 << 16) | (0x9874 >> 2),
0295     0x00000000,
0296     (0x8001 << 16) | (0x9870 >> 2),
0297     0x00000000,
0298     (0x8001 << 16) | (0x9874 >> 2),
0299     0x00000000,
0300     (0x8040 << 16) | (0x9870 >> 2),
0301     0x00000000,
0302     (0x8040 << 16) | (0x9874 >> 2),
0303     0x00000000,
0304     (0x8041 << 16) | (0x9870 >> 2),
0305     0x00000000,
0306     (0x8041 << 16) | (0x9874 >> 2),
0307     0x00000000,
0308     0x00000000
0309 };
0310 
0311 static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
0312 {
0313     const char *chip_name;
0314     char fw_name[30];
0315     int err;
0316     const struct gfx_firmware_header_v1_0 *cp_hdr;
0317     const struct rlc_firmware_header_v1_0 *rlc_hdr;
0318 
0319     DRM_DEBUG("\n");
0320 
0321     switch (adev->asic_type) {
0322     case CHIP_TAHITI:
0323         chip_name = "tahiti";
0324         break;
0325     case CHIP_PITCAIRN:
0326         chip_name = "pitcairn";
0327         break;
0328     case CHIP_VERDE:
0329         chip_name = "verde";
0330         break;
0331     case CHIP_OLAND:
0332         chip_name = "oland";
0333         break;
0334     case CHIP_HAINAN:
0335         chip_name = "hainan";
0336         break;
0337     default: BUG();
0338     }
0339 
0340     snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
0341     err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
0342     if (err)
0343         goto out;
0344     err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
0345     if (err)
0346         goto out;
0347     cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
0348     adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
0349     adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
0350 
0351     snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
0352     err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
0353     if (err)
0354         goto out;
0355     err = amdgpu_ucode_validate(adev->gfx.me_fw);
0356     if (err)
0357         goto out;
0358     cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
0359     adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
0360     adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
0361 
0362     snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
0363     err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
0364     if (err)
0365         goto out;
0366     err = amdgpu_ucode_validate(adev->gfx.ce_fw);
0367     if (err)
0368         goto out;
0369     cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
0370     adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
0371     adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
0372 
0373     snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
0374     err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
0375     if (err)
0376         goto out;
0377     err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
0378     rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
0379     adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
0380     adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
0381 
0382 out:
0383     if (err) {
0384         pr_err("gfx6: Failed to load firmware \"%s\"\n", fw_name);
0385         release_firmware(adev->gfx.pfp_fw);
0386         adev->gfx.pfp_fw = NULL;
0387         release_firmware(adev->gfx.me_fw);
0388         adev->gfx.me_fw = NULL;
0389         release_firmware(adev->gfx.ce_fw);
0390         adev->gfx.ce_fw = NULL;
0391         release_firmware(adev->gfx.rlc_fw);
0392         adev->gfx.rlc_fw = NULL;
0393     }
0394     return err;
0395 }
0396 
0397 static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
0398 {
0399     const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
0400     u32 reg_offset, split_equal_to_row_size, *tilemode;
0401 
0402     memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array));
0403     tilemode = adev->gfx.config.tile_mode_array;
0404 
0405     switch (adev->gfx.config.mem_row_size_in_kb) {
0406     case 1:
0407         split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
0408         break;
0409     case 2:
0410     default:
0411         split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
0412         break;
0413     case 4:
0414         split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
0415         break;
0416     }
0417 
0418     if (adev->asic_type == CHIP_VERDE) {
0419         tilemode[0] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
0420                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0421                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0422                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
0423                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0424                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0425                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
0426                 NUM_BANKS(ADDR_SURF_16_BANK);
0427         tilemode[1] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
0428                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0429                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0430                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
0431                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0432                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0433                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
0434                 NUM_BANKS(ADDR_SURF_16_BANK);
0435         tilemode[2] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
0436                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0437                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0438                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
0439                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0440                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0441                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
0442                 NUM_BANKS(ADDR_SURF_16_BANK);
0443         tilemode[3] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
0444                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0445                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0446                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0447                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
0448                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
0449                 NUM_BANKS(ADDR_SURF_8_BANK) |
0450                 TILE_SPLIT(split_equal_to_row_size);
0451         tilemode[4] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
0452                 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
0453                 PIPE_CONFIG(ADDR_SURF_P4_8x16);
0454         tilemode[5] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
0455                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0456                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0457                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
0458                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0459                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
0460                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
0461                 NUM_BANKS(ADDR_SURF_4_BANK);
0462         tilemode[6] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
0463                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0464                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0465                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
0466                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0467                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0468                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
0469                 NUM_BANKS(ADDR_SURF_4_BANK);
0470         tilemode[7] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
0471                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0472                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0473                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
0474                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0475                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0476                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
0477                 NUM_BANKS(ADDR_SURF_2_BANK);
0478         tilemode[8] =   ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
0479         tilemode[9] =   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
0480                 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
0481                 PIPE_CONFIG(ADDR_SURF_P4_8x16);
0482         tilemode[10] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
0483                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0484                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0485                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
0486                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0487                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0488                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
0489                 NUM_BANKS(ADDR_SURF_16_BANK);
0490         tilemode[11] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
0491                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0492                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0493                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
0494                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0495                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
0496                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
0497                 NUM_BANKS(ADDR_SURF_16_BANK);
0498         tilemode[12] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
0499                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0500                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0501                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
0502                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0503                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
0504                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
0505                 NUM_BANKS(ADDR_SURF_16_BANK);
0506         tilemode[13] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0507                 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
0508                 PIPE_CONFIG(ADDR_SURF_P4_8x16);
0509         tilemode[14] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0510                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0511                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0512                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
0513                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0514                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0515                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
0516                 NUM_BANKS(ADDR_SURF_16_BANK);
0517         tilemode[15] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0518                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0519                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0520                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
0521                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0522                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
0523                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
0524                 NUM_BANKS(ADDR_SURF_16_BANK);
0525         tilemode[16] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0526                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0527                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0528                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
0529                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0530                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
0531                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
0532                 NUM_BANKS(ADDR_SURF_16_BANK);
0533         tilemode[17] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0534                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0535                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0536                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0537                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
0538                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
0539                 NUM_BANKS(ADDR_SURF_16_BANK) |
0540                 TILE_SPLIT(split_equal_to_row_size);
0541         tilemode[18] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0542                 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
0543                 PIPE_CONFIG(ADDR_SURF_P4_8x16);
0544         tilemode[19] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0545                 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
0546                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0547                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0548                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
0549                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
0550                 NUM_BANKS(ADDR_SURF_16_BANK) |
0551                 TILE_SPLIT(split_equal_to_row_size);
0552         tilemode[20] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0553                 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
0554                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0555                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0556                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
0557                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
0558                 NUM_BANKS(ADDR_SURF_16_BANK) |
0559                 TILE_SPLIT(split_equal_to_row_size);
0560         tilemode[21] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0561                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0562                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0563                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
0564                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0565                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0566                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
0567                 NUM_BANKS(ADDR_SURF_8_BANK);
0568         tilemode[22] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0569                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0570                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0571                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
0572                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0573                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
0574                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
0575                 NUM_BANKS(ADDR_SURF_8_BANK);
0576         tilemode[23] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0577                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0578                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0579                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
0580                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0581                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0582                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
0583                 NUM_BANKS(ADDR_SURF_4_BANK);
0584         tilemode[24] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0585                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0586                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0587                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
0588                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0589                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
0590                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
0591                 NUM_BANKS(ADDR_SURF_4_BANK);
0592         tilemode[25] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0593                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0594                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0595                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
0596                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0597                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0598                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
0599                 NUM_BANKS(ADDR_SURF_2_BANK);
0600         tilemode[26] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0601                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0602                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0603                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
0604                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0605                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0606                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
0607                 NUM_BANKS(ADDR_SURF_2_BANK);
0608         tilemode[27] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0609                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0610                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0611                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
0612                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0613                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0614                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
0615                 NUM_BANKS(ADDR_SURF_2_BANK);
0616         tilemode[28] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0617                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0618                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0619                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
0620                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0621                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0622                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
0623                 NUM_BANKS(ADDR_SURF_2_BANK);
0624         tilemode[29] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0625                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0626                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0627                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
0628                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0629                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0630                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
0631                 NUM_BANKS(ADDR_SURF_2_BANK);
0632         tilemode[30] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0633                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0634                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0635                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
0636                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0637                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
0638                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
0639                 NUM_BANKS(ADDR_SURF_2_BANK);
0640         for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
0641             WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
0642     } else if (adev->asic_type == CHIP_OLAND) {
0643         tilemode[0] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
0644                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0645                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0646                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
0647                 NUM_BANKS(ADDR_SURF_16_BANK) |
0648                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0649                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0650                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
0651         tilemode[1] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
0652                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0653                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0654                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
0655                 NUM_BANKS(ADDR_SURF_16_BANK) |
0656                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0657                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0658                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
0659         tilemode[2] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
0660                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0661                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0662                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
0663                 NUM_BANKS(ADDR_SURF_16_BANK) |
0664                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0665                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0666                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
0667         tilemode[3] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
0668                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0669                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0670                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
0671                 NUM_BANKS(ADDR_SURF_16_BANK) |
0672                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0673                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0674                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
0675         tilemode[4] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
0676                 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
0677                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0678                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
0679                 NUM_BANKS(ADDR_SURF_16_BANK) |
0680                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0681                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
0682                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
0683         tilemode[5] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
0684                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0685                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0686                 TILE_SPLIT(split_equal_to_row_size) |
0687                 NUM_BANKS(ADDR_SURF_16_BANK) |
0688                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0689                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
0690                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
0691         tilemode[6] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
0692                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0693                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0694                 TILE_SPLIT(split_equal_to_row_size) |
0695                 NUM_BANKS(ADDR_SURF_16_BANK) |
0696                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0697                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
0698                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
0699         tilemode[7] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
0700                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0701                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0702                 TILE_SPLIT(split_equal_to_row_size) |
0703                 NUM_BANKS(ADDR_SURF_16_BANK) |
0704                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0705                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0706                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
0707         tilemode[8] =   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
0708                 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
0709                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0710                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
0711                 NUM_BANKS(ADDR_SURF_16_BANK) |
0712                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0713                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
0714                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
0715         tilemode[9] =   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
0716                 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
0717                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0718                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
0719                 NUM_BANKS(ADDR_SURF_16_BANK) |
0720                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0721                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
0722                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
0723         tilemode[10] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
0724                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0725                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0726                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
0727                 NUM_BANKS(ADDR_SURF_16_BANK) |
0728                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0729                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0730                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
0731         tilemode[11] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
0732                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0733                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0734                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
0735                 NUM_BANKS(ADDR_SURF_16_BANK) |
0736                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0737                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
0738                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
0739         tilemode[12] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
0740                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0741                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0742                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
0743                 NUM_BANKS(ADDR_SURF_16_BANK) |
0744                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0745                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
0746                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
0747         tilemode[13] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0748                 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
0749                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0750                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
0751                 NUM_BANKS(ADDR_SURF_16_BANK) |
0752                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0753                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
0754                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
0755         tilemode[14] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0756                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0757                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0758                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
0759                 NUM_BANKS(ADDR_SURF_16_BANK) |
0760                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0761                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0762                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
0763         tilemode[15] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0764                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0765                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0766                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
0767                 NUM_BANKS(ADDR_SURF_16_BANK) |
0768                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0769                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
0770                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
0771         tilemode[16] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0772                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0773                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0774                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
0775                 NUM_BANKS(ADDR_SURF_16_BANK) |
0776                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0777                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
0778                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
0779         tilemode[17] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0780                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0781                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0782                 TILE_SPLIT(split_equal_to_row_size) |
0783                 NUM_BANKS(ADDR_SURF_16_BANK) |
0784                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0785                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
0786                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
0787         tilemode[18] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0788                 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
0789                 PIPE_CONFIG(ADDR_SURF_P4_8x16);
0790         tilemode[19] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0791                 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
0792                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0793                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0794                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
0795                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
0796                 NUM_BANKS(ADDR_SURF_16_BANK) |
0797                 TILE_SPLIT(split_equal_to_row_size);
0798         tilemode[20] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0799                 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
0800                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
0801                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0802                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
0803                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
0804                 NUM_BANKS(ADDR_SURF_16_BANK) |
0805                 TILE_SPLIT(split_equal_to_row_size);
0806         tilemode[21] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0807                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0808                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
0809                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
0810                 NUM_BANKS(ADDR_SURF_16_BANK) |
0811                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
0812                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0813                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
0814         tilemode[22] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0815                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0816                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
0817                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
0818                 NUM_BANKS(ADDR_SURF_16_BANK) |
0819                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0820                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0821                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
0822         tilemode[23] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0823                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0824                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
0825                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
0826                 NUM_BANKS(ADDR_SURF_16_BANK) |
0827                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0828                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
0829                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
0830         tilemode[24] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0831                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0832                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
0833                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
0834                 NUM_BANKS(ADDR_SURF_16_BANK) |
0835                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0836                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
0837                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
0838         tilemode[25] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0839                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0840                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
0841                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
0842                 NUM_BANKS(ADDR_SURF_8_BANK) |
0843                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0844                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
0845                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1);
0846         for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
0847             WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
0848     } else if (adev->asic_type == CHIP_HAINAN) {
0849         tilemode[0] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
0850                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0851                 PIPE_CONFIG(ADDR_SURF_P2) |
0852                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
0853                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0854                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0855                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
0856                 NUM_BANKS(ADDR_SURF_16_BANK);
0857         tilemode[1] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
0858                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0859                 PIPE_CONFIG(ADDR_SURF_P2) |
0860                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
0861                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0862                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0863                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
0864                 NUM_BANKS(ADDR_SURF_16_BANK);
0865         tilemode[2] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
0866                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0867                 PIPE_CONFIG(ADDR_SURF_P2) |
0868                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
0869                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0870                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0871                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
0872                 NUM_BANKS(ADDR_SURF_16_BANK);
0873         tilemode[3] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
0874                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0875                 PIPE_CONFIG(ADDR_SURF_P2) |
0876                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0877                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
0878                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
0879                 NUM_BANKS(ADDR_SURF_8_BANK) |
0880                 TILE_SPLIT(split_equal_to_row_size);
0881         tilemode[4] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
0882                 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
0883                 PIPE_CONFIG(ADDR_SURF_P2);
0884         tilemode[5] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
0885                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0886                 PIPE_CONFIG(ADDR_SURF_P2) |
0887                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
0888                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0889                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
0890                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
0891                 NUM_BANKS(ADDR_SURF_8_BANK);
0892         tilemode[6] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
0893                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0894                 PIPE_CONFIG(ADDR_SURF_P2) |
0895                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
0896                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0897                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
0898                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
0899                 NUM_BANKS(ADDR_SURF_8_BANK);
0900         tilemode[7] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
0901                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0902                 PIPE_CONFIG(ADDR_SURF_P2) |
0903                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
0904                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0905                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
0906                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
0907                 NUM_BANKS(ADDR_SURF_4_BANK);
0908         tilemode[8] =   ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
0909         tilemode[9] =   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
0910                 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
0911                 PIPE_CONFIG(ADDR_SURF_P2);
0912         tilemode[10] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
0913                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0914                 PIPE_CONFIG(ADDR_SURF_P2) |
0915                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
0916                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0917                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0918                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
0919                 NUM_BANKS(ADDR_SURF_16_BANK);
0920         tilemode[11] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
0921                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0922                 PIPE_CONFIG(ADDR_SURF_P2) |
0923                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
0924                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0925                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
0926                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
0927                 NUM_BANKS(ADDR_SURF_16_BANK);
0928         tilemode[12] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
0929                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0930                 PIPE_CONFIG(ADDR_SURF_P2) |
0931                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
0932                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0933                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
0934                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
0935                 NUM_BANKS(ADDR_SURF_16_BANK);
0936         tilemode[13] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0937                 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
0938                 PIPE_CONFIG(ADDR_SURF_P2);
0939         tilemode[14] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0940                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0941                 PIPE_CONFIG(ADDR_SURF_P2) |
0942                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
0943                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0944                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0945                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
0946                 NUM_BANKS(ADDR_SURF_16_BANK);
0947         tilemode[15] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0948                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0949                 PIPE_CONFIG(ADDR_SURF_P2) |
0950                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
0951                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0952                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
0953                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
0954                 NUM_BANKS(ADDR_SURF_16_BANK);
0955         tilemode[16] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0956                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0957                 PIPE_CONFIG(ADDR_SURF_P2) |
0958                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
0959                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0960                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
0961                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
0962                 NUM_BANKS(ADDR_SURF_16_BANK);
0963         tilemode[17] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0964                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0965                 PIPE_CONFIG(ADDR_SURF_P2) |
0966                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0967                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
0968                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
0969                 NUM_BANKS(ADDR_SURF_16_BANK) |
0970                 TILE_SPLIT(split_equal_to_row_size);
0971         tilemode[18] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0972                 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
0973                 PIPE_CONFIG(ADDR_SURF_P2);
0974         tilemode[19] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0975                 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
0976                 PIPE_CONFIG(ADDR_SURF_P2) |
0977                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0978                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
0979                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
0980                 NUM_BANKS(ADDR_SURF_16_BANK) |
0981                 TILE_SPLIT(split_equal_to_row_size);
0982         tilemode[20] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0983                 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
0984                 PIPE_CONFIG(ADDR_SURF_P2) |
0985                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
0986                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
0987                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
0988                 NUM_BANKS(ADDR_SURF_16_BANK) |
0989                 TILE_SPLIT(split_equal_to_row_size);
0990         tilemode[21] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0991                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
0992                 PIPE_CONFIG(ADDR_SURF_P2) |
0993                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
0994                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
0995                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
0996                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
0997                 NUM_BANKS(ADDR_SURF_8_BANK);
0998         tilemode[22] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
0999                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1000                 PIPE_CONFIG(ADDR_SURF_P2) |
1001                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1002                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1003                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1004                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1005                 NUM_BANKS(ADDR_SURF_8_BANK);
1006         tilemode[23] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1007                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1008                 PIPE_CONFIG(ADDR_SURF_P2) |
1009                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1010                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1011                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1012                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1013                 NUM_BANKS(ADDR_SURF_8_BANK);
1014         tilemode[24] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1015                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1016                 PIPE_CONFIG(ADDR_SURF_P2) |
1017                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1018                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1019                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1020                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1021                 NUM_BANKS(ADDR_SURF_8_BANK);
1022         tilemode[25] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1023                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1024                 PIPE_CONFIG(ADDR_SURF_P2) |
1025                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1026                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1027                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1028                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1029                 NUM_BANKS(ADDR_SURF_4_BANK);
1030         tilemode[26] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1031                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1032                 PIPE_CONFIG(ADDR_SURF_P2) |
1033                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1034                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1035                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1036                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1037                 NUM_BANKS(ADDR_SURF_4_BANK);
1038         tilemode[27] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1039                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1040                 PIPE_CONFIG(ADDR_SURF_P2) |
1041                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1042                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1043                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1044                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1045                 NUM_BANKS(ADDR_SURF_4_BANK);
1046         tilemode[28] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1047                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1048                 PIPE_CONFIG(ADDR_SURF_P2) |
1049                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1050                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1051                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1052                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1053                 NUM_BANKS(ADDR_SURF_4_BANK);
1054         tilemode[29] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1055                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1056                 PIPE_CONFIG(ADDR_SURF_P2) |
1057                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1058                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1059                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1060                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1061                 NUM_BANKS(ADDR_SURF_4_BANK);
1062         tilemode[30] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1063                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1064                 PIPE_CONFIG(ADDR_SURF_P2) |
1065                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1066                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1067                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1068                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1069                 NUM_BANKS(ADDR_SURF_4_BANK);
1070         for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1071             WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1072     } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
1073         tilemode[0] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1074                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1075                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1076                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1077                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1078                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1079                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1080                 NUM_BANKS(ADDR_SURF_16_BANK);
1081         tilemode[1] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1082                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1083                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1084                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1085                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1086                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1087                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1088                 NUM_BANKS(ADDR_SURF_16_BANK);
1089         tilemode[2] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1090                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1091                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1092                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1093                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1094                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1095                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1096                 NUM_BANKS(ADDR_SURF_16_BANK);
1097         tilemode[3] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1098                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1099                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1100                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1101                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1102                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1103                 NUM_BANKS(ADDR_SURF_4_BANK) |
1104                 TILE_SPLIT(split_equal_to_row_size);
1105         tilemode[4] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1106                 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1107                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1108         tilemode[5] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1109                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1110                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1111                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1112                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1113                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1114                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1115                 NUM_BANKS(ADDR_SURF_2_BANK);
1116         tilemode[6] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1117                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1118                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1119                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1120                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1121                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1122                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1123                 NUM_BANKS(ADDR_SURF_2_BANK);
1124         tilemode[7] =   MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1125                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1126                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1127                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1128                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1129                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1130                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1131                 NUM_BANKS(ADDR_SURF_2_BANK);
1132         tilemode[8] =   ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
1133         tilemode[9] =   MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1134                 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1135                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1136         tilemode[10] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1137                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1138                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1139                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1140                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1141                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1142                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1143                 NUM_BANKS(ADDR_SURF_16_BANK);
1144         tilemode[11] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1145                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1146                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1147                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1148                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1149                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1150                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1151                 NUM_BANKS(ADDR_SURF_16_BANK);
1152         tilemode[12] =  MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1153                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1154                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1155                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1156                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1157                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1158                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1159                 NUM_BANKS(ADDR_SURF_16_BANK);
1160         tilemode[13] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1161                 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1162                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1163         tilemode[14] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1164                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1165                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1166                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1167                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1168                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1169                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1170                 NUM_BANKS(ADDR_SURF_16_BANK);
1171         tilemode[15] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1172                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1173                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1174                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1175                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1176                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1177                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1178                 NUM_BANKS(ADDR_SURF_16_BANK);
1179         tilemode[16] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1180                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1181                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1182                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1183                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1184                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1185                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1186                 NUM_BANKS(ADDR_SURF_16_BANK);
1187         tilemode[17] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1188                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1189                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1190                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1191                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1192                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1193                 NUM_BANKS(ADDR_SURF_16_BANK) |
1194                 TILE_SPLIT(split_equal_to_row_size);
1195         tilemode[18] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1196                 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1197                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1198         tilemode[19] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1199                 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1200                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1201                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1202                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1203                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1204                 NUM_BANKS(ADDR_SURF_16_BANK) |
1205                 TILE_SPLIT(split_equal_to_row_size);
1206         tilemode[20] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1207                 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1208                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1209                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1210                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1211                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1212                 NUM_BANKS(ADDR_SURF_16_BANK) |
1213                 TILE_SPLIT(split_equal_to_row_size);
1214         tilemode[21] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1215                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1216                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1217                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1218                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1219                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1220                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1221                 NUM_BANKS(ADDR_SURF_4_BANK);
1222         tilemode[22] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1223                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1224                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1225                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1226                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1227                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1228                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1229                 NUM_BANKS(ADDR_SURF_4_BANK);
1230         tilemode[23] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1231                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1232                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1233                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1234                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1235                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1236                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1237                 NUM_BANKS(ADDR_SURF_2_BANK);
1238         tilemode[24] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1239                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1240                 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1241                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1242                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1243                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1244                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1245                 NUM_BANKS(ADDR_SURF_2_BANK);
1246         tilemode[25] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1247                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1248                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1249                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1250                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1251                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1252                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1253                 NUM_BANKS(ADDR_SURF_2_BANK);
1254         tilemode[26] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1255                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1256                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1257                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1258                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1259                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1260                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1261                 NUM_BANKS(ADDR_SURF_2_BANK);
1262         tilemode[27] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1263                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1264                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1265                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1266                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1267                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1268                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1269                 NUM_BANKS(ADDR_SURF_2_BANK);
1270         tilemode[28] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1271                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1272                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1273                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1274                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1275                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1276                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1277                 NUM_BANKS(ADDR_SURF_2_BANK);
1278         tilemode[29] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1279                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1280                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1281                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1282                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1283                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1284                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1285                 NUM_BANKS(ADDR_SURF_2_BANK);
1286         tilemode[30] =  MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1287                 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1288                 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1289                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1290                 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1291                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1292                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1293                 NUM_BANKS(ADDR_SURF_2_BANK);
1294         for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1295             WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1296     } else {
1297         DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1298     }
1299 }
1300 
1301 static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1302                   u32 sh_num, u32 instance)
1303 {
1304     u32 data;
1305 
1306     if (instance == 0xffffffff)
1307         data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1308     else
1309         data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1310 
1311     if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1312         data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1313             GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1314     else if (se_num == 0xffffffff)
1315         data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1316             (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1317     else if (sh_num == 0xffffffff)
1318         data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1319             (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1320     else
1321         data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1322             (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1323     WREG32(mmGRBM_GFX_INDEX, data);
1324 }
1325 
1326 static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1327 {
1328     u32 data, mask;
1329 
1330     data = RREG32(mmCC_RB_BACKEND_DISABLE) |
1331         RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1332 
1333     data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
1334 
1335     mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/
1336                      adev->gfx.config.max_sh_per_se);
1337 
1338     return ~data & mask;
1339 }
1340 
1341 static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
1342 {
1343     switch (adev->asic_type) {
1344     case CHIP_TAHITI:
1345     case CHIP_PITCAIRN:
1346         *rconf |=
1347                (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) |
1348                (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1349                (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1350                (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) |
1351                (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) |
1352                (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) |
1353                (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT);
1354         break;
1355     case CHIP_VERDE:
1356         *rconf |=
1357                (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1358                (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1359                (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT);
1360         break;
1361     case CHIP_OLAND:
1362         *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT);
1363         break;
1364     case CHIP_HAINAN:
1365         *rconf |= 0x0;
1366         break;
1367     default:
1368         DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1369         break;
1370     }
1371 }
1372 
1373 static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1374                             u32 raster_config, unsigned rb_mask,
1375                             unsigned num_rb)
1376 {
1377     unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1378     unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1379     unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1380     unsigned rb_per_se = num_rb / num_se;
1381     unsigned se_mask[4];
1382     unsigned se;
1383 
1384     se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1385     se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1386     se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1387     se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1388 
1389     WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1390     WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1391     WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1392 
1393     for (se = 0; se < num_se; se++) {
1394         unsigned raster_config_se = raster_config;
1395         unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1396         unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1397         int idx = (se / 2) * 2;
1398 
1399         if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1400             raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK;
1401 
1402             if (!se_mask[idx])
1403                 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1404             else
1405                 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1406         }
1407 
1408         pkr0_mask &= rb_mask;
1409         pkr1_mask &= rb_mask;
1410         if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1411             raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK;
1412 
1413             if (!pkr0_mask)
1414                 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1415             else
1416                 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1417         }
1418 
1419         if (rb_per_se >= 2) {
1420             unsigned rb0_mask = 1 << (se * rb_per_se);
1421             unsigned rb1_mask = rb0_mask << 1;
1422 
1423             rb0_mask &= rb_mask;
1424             rb1_mask &= rb_mask;
1425             if (!rb0_mask || !rb1_mask) {
1426                 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK;
1427 
1428                 if (!rb0_mask)
1429                     raster_config_se |=
1430                         RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1431                 else
1432                     raster_config_se |=
1433                         RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1434             }
1435 
1436             if (rb_per_se > 2) {
1437                 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1438                 rb1_mask = rb0_mask << 1;
1439                 rb0_mask &= rb_mask;
1440                 rb1_mask &= rb_mask;
1441                 if (!rb0_mask || !rb1_mask) {
1442                     raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK;
1443 
1444                     if (!rb0_mask)
1445                         raster_config_se |=
1446                             RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1447                     else
1448                         raster_config_se |=
1449                             RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1450                 }
1451             }
1452         }
1453 
1454         /* GRBM_GFX_INDEX has a different offset on SI */
1455         gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1456         WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1457     }
1458 
1459     /* GRBM_GFX_INDEX has a different offset on SI */
1460     gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1461 }
1462 
1463 static void gfx_v6_0_setup_rb(struct amdgpu_device *adev)
1464 {
1465     int i, j;
1466     u32 data;
1467     u32 raster_config = 0;
1468     u32 active_rbs = 0;
1469     u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1470                     adev->gfx.config.max_sh_per_se;
1471     unsigned num_rb_pipes;
1472 
1473     mutex_lock(&adev->grbm_idx_mutex);
1474     for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1475         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1476             gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1477             data = gfx_v6_0_get_rb_active_bitmap(adev);
1478             active_rbs |= data <<
1479                 ((i * adev->gfx.config.max_sh_per_se + j) *
1480                  rb_bitmap_width_per_sh);
1481         }
1482     }
1483     gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1484 
1485     adev->gfx.config.backend_enable_mask = active_rbs;
1486     adev->gfx.config.num_rbs = hweight32(active_rbs);
1487 
1488     num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1489                  adev->gfx.config.max_shader_engines, 16);
1490 
1491     gfx_v6_0_raster_config(adev, &raster_config);
1492 
1493     if (!adev->gfx.config.backend_enable_mask ||
1494          adev->gfx.config.num_rbs >= num_rb_pipes)
1495         WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1496     else
1497         gfx_v6_0_write_harvested_raster_configs(adev, raster_config,
1498                             adev->gfx.config.backend_enable_mask,
1499                             num_rb_pipes);
1500 
1501     /* cache the values for userspace */
1502     for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1503         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1504             gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1505             adev->gfx.config.rb_config[i][j].rb_backend_disable =
1506                 RREG32(mmCC_RB_BACKEND_DISABLE);
1507             adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1508                 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1509             adev->gfx.config.rb_config[i][j].raster_config =
1510                 RREG32(mmPA_SC_RASTER_CONFIG);
1511         }
1512     }
1513     gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1514     mutex_unlock(&adev->grbm_idx_mutex);
1515 }
1516 
1517 static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
1518                          u32 bitmap)
1519 {
1520     u32 data;
1521 
1522     if (!bitmap)
1523         return;
1524 
1525     data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
1526     data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
1527 
1528     WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
1529 }
1530 
1531 static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev)
1532 {
1533     u32 data, mask;
1534 
1535     data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
1536         RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
1537 
1538     mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
1539     return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
1540 }
1541 
1542 
1543 static void gfx_v6_0_setup_spi(struct amdgpu_device *adev)
1544 {
1545     int i, j, k;
1546     u32 data, mask;
1547     u32 active_cu = 0;
1548 
1549     mutex_lock(&adev->grbm_idx_mutex);
1550     for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1551         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1552             gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1553             data = RREG32(mmSPI_STATIC_THREAD_MGMT_3);
1554             active_cu = gfx_v6_0_get_cu_enabled(adev);
1555 
1556             mask = 1;
1557             for (k = 0; k < 16; k++) {
1558                 mask <<= k;
1559                 if (active_cu & mask) {
1560                     data &= ~mask;
1561                     WREG32(mmSPI_STATIC_THREAD_MGMT_3, data);
1562                     break;
1563                 }
1564             }
1565         }
1566     }
1567     gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1568     mutex_unlock(&adev->grbm_idx_mutex);
1569 }
1570 
1571 static void gfx_v6_0_config_init(struct amdgpu_device *adev)
1572 {
1573     adev->gfx.config.double_offchip_lds_buf = 0;
1574 }
1575 
1576 static void gfx_v6_0_constants_init(struct amdgpu_device *adev)
1577 {
1578     u32 gb_addr_config = 0;
1579     u32 mc_arb_ramcfg;
1580     u32 sx_debug_1;
1581     u32 hdp_host_path_cntl;
1582     u32 tmp;
1583 
1584     switch (adev->asic_type) {
1585     case CHIP_TAHITI:
1586         adev->gfx.config.max_shader_engines = 2;
1587         adev->gfx.config.max_tile_pipes = 12;
1588         adev->gfx.config.max_cu_per_sh = 8;
1589         adev->gfx.config.max_sh_per_se = 2;
1590         adev->gfx.config.max_backends_per_se = 4;
1591         adev->gfx.config.max_texture_channel_caches = 12;
1592         adev->gfx.config.max_gprs = 256;
1593         adev->gfx.config.max_gs_threads = 32;
1594         adev->gfx.config.max_hw_contexts = 8;
1595 
1596         adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1597         adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1598         adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1599         adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1600         gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1601         break;
1602     case CHIP_PITCAIRN:
1603         adev->gfx.config.max_shader_engines = 2;
1604         adev->gfx.config.max_tile_pipes = 8;
1605         adev->gfx.config.max_cu_per_sh = 5;
1606         adev->gfx.config.max_sh_per_se = 2;
1607         adev->gfx.config.max_backends_per_se = 4;
1608         adev->gfx.config.max_texture_channel_caches = 8;
1609         adev->gfx.config.max_gprs = 256;
1610         adev->gfx.config.max_gs_threads = 32;
1611         adev->gfx.config.max_hw_contexts = 8;
1612 
1613         adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1614         adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1615         adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1616         adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1617         gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1618         break;
1619     case CHIP_VERDE:
1620         adev->gfx.config.max_shader_engines = 1;
1621         adev->gfx.config.max_tile_pipes = 4;
1622         adev->gfx.config.max_cu_per_sh = 5;
1623         adev->gfx.config.max_sh_per_se = 2;
1624         adev->gfx.config.max_backends_per_se = 4;
1625         adev->gfx.config.max_texture_channel_caches = 4;
1626         adev->gfx.config.max_gprs = 256;
1627         adev->gfx.config.max_gs_threads = 32;
1628         adev->gfx.config.max_hw_contexts = 8;
1629 
1630         adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1631         adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1632         adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1633         adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1634         gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1635         break;
1636     case CHIP_OLAND:
1637         adev->gfx.config.max_shader_engines = 1;
1638         adev->gfx.config.max_tile_pipes = 4;
1639         adev->gfx.config.max_cu_per_sh = 6;
1640         adev->gfx.config.max_sh_per_se = 1;
1641         adev->gfx.config.max_backends_per_se = 2;
1642         adev->gfx.config.max_texture_channel_caches = 4;
1643         adev->gfx.config.max_gprs = 256;
1644         adev->gfx.config.max_gs_threads = 16;
1645         adev->gfx.config.max_hw_contexts = 8;
1646 
1647         adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1648         adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1649         adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1650         adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1651         gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1652         break;
1653     case CHIP_HAINAN:
1654         adev->gfx.config.max_shader_engines = 1;
1655         adev->gfx.config.max_tile_pipes = 4;
1656         adev->gfx.config.max_cu_per_sh = 5;
1657         adev->gfx.config.max_sh_per_se = 1;
1658         adev->gfx.config.max_backends_per_se = 1;
1659         adev->gfx.config.max_texture_channel_caches = 2;
1660         adev->gfx.config.max_gprs = 256;
1661         adev->gfx.config.max_gs_threads = 16;
1662         adev->gfx.config.max_hw_contexts = 8;
1663 
1664         adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1665         adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1666         adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1667         adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1668         gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
1669         break;
1670     default:
1671         BUG();
1672         break;
1673     }
1674 
1675     WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1676     WREG32(mmSRBM_INT_CNTL, 1);
1677     WREG32(mmSRBM_INT_ACK, 1);
1678 
1679     WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
1680 
1681     adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1682     mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1683 
1684     adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1685     adev->gfx.config.mem_max_burst_length_bytes = 256;
1686     tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
1687     adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1688     if (adev->gfx.config.mem_row_size_in_kb > 4)
1689         adev->gfx.config.mem_row_size_in_kb = 4;
1690     adev->gfx.config.shader_engine_tile_size = 32;
1691     adev->gfx.config.num_gpus = 1;
1692     adev->gfx.config.multi_gpu_tile_size = 64;
1693 
1694     gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
1695     switch (adev->gfx.config.mem_row_size_in_kb) {
1696     case 1:
1697     default:
1698         gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1699         break;
1700     case 2:
1701         gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1702         break;
1703     case 4:
1704         gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1705         break;
1706     }
1707     gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK;
1708     if (adev->gfx.config.max_shader_engines == 2)
1709         gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT;
1710     adev->gfx.config.gb_addr_config = gb_addr_config;
1711 
1712     WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
1713     WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config);
1714     WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
1715     WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
1716     WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1717     WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1718 
1719 #if 0
1720     if (adev->has_uvd) {
1721         WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
1722         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1723         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1724     }
1725 #endif
1726     gfx_v6_0_tiling_mode_table_init(adev);
1727 
1728     gfx_v6_0_setup_rb(adev);
1729 
1730     gfx_v6_0_setup_spi(adev);
1731 
1732     gfx_v6_0_get_cu_info(adev);
1733     gfx_v6_0_config_init(adev);
1734 
1735     WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
1736                        (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
1737     WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1738                     (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1739 
1740     sx_debug_1 = RREG32(mmSX_DEBUG_1);
1741     WREG32(mmSX_DEBUG_1, sx_debug_1);
1742 
1743     WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1744 
1745     WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1746                    (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1747                    (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1748                    (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1749 
1750     WREG32(mmVGT_NUM_INSTANCES, 1);
1751     WREG32(mmCP_PERFMON_CNTL, 0);
1752     WREG32(mmSQ_CONFIG, 0);
1753     WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1754                       (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1755 
1756     WREG32(mmVGT_CACHE_INVALIDATION,
1757         (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1758         (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1759 
1760     WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1761     WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1762 
1763     WREG32(mmCB_PERFCOUNTER0_SELECT0, 0);
1764     WREG32(mmCB_PERFCOUNTER0_SELECT1, 0);
1765     WREG32(mmCB_PERFCOUNTER1_SELECT0, 0);
1766     WREG32(mmCB_PERFCOUNTER1_SELECT1, 0);
1767     WREG32(mmCB_PERFCOUNTER2_SELECT0, 0);
1768     WREG32(mmCB_PERFCOUNTER2_SELECT1, 0);
1769     WREG32(mmCB_PERFCOUNTER3_SELECT0, 0);
1770     WREG32(mmCB_PERFCOUNTER3_SELECT1, 0);
1771 
1772     hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL);
1773     WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1774 
1775     WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1776                 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1777 
1778     udelay(50);
1779 }
1780 
1781 static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1782 {
1783     struct amdgpu_device *adev = ring->adev;
1784     uint32_t tmp = 0;
1785     unsigned i;
1786     int r;
1787 
1788     WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
1789 
1790     r = amdgpu_ring_alloc(ring, 3);
1791     if (r)
1792         return r;
1793 
1794     amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1795     amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START);
1796     amdgpu_ring_write(ring, 0xDEADBEEF);
1797     amdgpu_ring_commit(ring);
1798 
1799     for (i = 0; i < adev->usec_timeout; i++) {
1800         tmp = RREG32(mmSCRATCH_REG0);
1801         if (tmp == 0xDEADBEEF)
1802             break;
1803         udelay(1);
1804     }
1805 
1806     if (i >= adev->usec_timeout)
1807         r = -ETIMEDOUT;
1808     return r;
1809 }
1810 
1811 static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
1812 {
1813     amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
1814     amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
1815         EVENT_INDEX(0));
1816 }
1817 
1818 static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1819                      u64 seq, unsigned flags)
1820 {
1821     bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1822     bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1823     /* flush read cache over gart */
1824     amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1825     amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1826     amdgpu_ring_write(ring, 0);
1827     amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1828     amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1829               PACKET3_TC_ACTION_ENA |
1830               PACKET3_SH_KCACHE_ACTION_ENA |
1831               PACKET3_SH_ICACHE_ACTION_ENA);
1832     amdgpu_ring_write(ring, 0xFFFFFFFF);
1833     amdgpu_ring_write(ring, 0);
1834     amdgpu_ring_write(ring, 10); /* poll interval */
1835     /* EVENT_WRITE_EOP - flush caches, send int */
1836     amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1837     amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1838     amdgpu_ring_write(ring, addr & 0xfffffffc);
1839     amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1840                 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) |
1841                 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT));
1842     amdgpu_ring_write(ring, lower_32_bits(seq));
1843     amdgpu_ring_write(ring, upper_32_bits(seq));
1844 }
1845 
1846 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1847                   struct amdgpu_job *job,
1848                   struct amdgpu_ib *ib,
1849                   uint32_t flags)
1850 {
1851     unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1852     u32 header, control = 0;
1853 
1854     /* insert SWITCH_BUFFER packet before first IB in the ring frame */
1855     if (flags & AMDGPU_HAVE_CTX_SWITCH) {
1856         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1857         amdgpu_ring_write(ring, 0);
1858     }
1859 
1860     if (ib->flags & AMDGPU_IB_FLAG_CE)
1861         header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1862     else
1863         header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1864 
1865     control |= ib->length_dw | (vmid << 24);
1866 
1867     amdgpu_ring_write(ring, header);
1868     amdgpu_ring_write(ring,
1869 #ifdef __BIG_ENDIAN
1870               (2 << 0) |
1871 #endif
1872               (ib->gpu_addr & 0xFFFFFFFC));
1873     amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1874     amdgpu_ring_write(ring, control);
1875 }
1876 
1877 /**
1878  * gfx_v6_0_ring_test_ib - basic ring IB test
1879  *
1880  * @ring: amdgpu_ring structure holding ring information
1881  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1882  *
1883  * Allocate an IB and execute it on the gfx ring (SI).
1884  * Provides a basic gfx ring test to verify that IBs are working.
1885  * Returns 0 on success, error on failure.
1886  */
1887 static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1888 {
1889     struct amdgpu_device *adev = ring->adev;
1890     struct dma_fence *f = NULL;
1891     struct amdgpu_ib ib;
1892     uint32_t tmp = 0;
1893     long r;
1894 
1895     WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
1896     memset(&ib, 0, sizeof(ib));
1897     r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
1898     if (r)
1899         return r;
1900 
1901     ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1902     ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START;
1903     ib.ptr[2] = 0xDEADBEEF;
1904     ib.length_dw = 3;
1905 
1906     r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1907     if (r)
1908         goto error;
1909 
1910     r = dma_fence_wait_timeout(f, false, timeout);
1911     if (r == 0) {
1912         r = -ETIMEDOUT;
1913         goto error;
1914     } else if (r < 0) {
1915         goto error;
1916     }
1917     tmp = RREG32(mmSCRATCH_REG0);
1918     if (tmp == 0xDEADBEEF)
1919         r = 0;
1920     else
1921         r = -EINVAL;
1922 
1923 error:
1924     amdgpu_ib_free(adev, &ib, NULL);
1925     dma_fence_put(f);
1926     return r;
1927 }
1928 
1929 static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1930 {
1931     if (enable) {
1932         WREG32(mmCP_ME_CNTL, 0);
1933     } else {
1934         WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
1935                       CP_ME_CNTL__PFP_HALT_MASK |
1936                       CP_ME_CNTL__CE_HALT_MASK));
1937         WREG32(mmSCRATCH_UMSK, 0);
1938     }
1939     udelay(50);
1940 }
1941 
1942 static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1943 {
1944     unsigned i;
1945     const struct gfx_firmware_header_v1_0 *pfp_hdr;
1946     const struct gfx_firmware_header_v1_0 *ce_hdr;
1947     const struct gfx_firmware_header_v1_0 *me_hdr;
1948     const __le32 *fw_data;
1949     u32 fw_size;
1950 
1951     if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1952         return -EINVAL;
1953 
1954     gfx_v6_0_cp_gfx_enable(adev, false);
1955     pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1956     ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1957     me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1958 
1959     amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1960     amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1961     amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1962 
1963     /* PFP */
1964     fw_data = (const __le32 *)
1965         (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1966     fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1967     WREG32(mmCP_PFP_UCODE_ADDR, 0);
1968     for (i = 0; i < fw_size; i++)
1969         WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
1970     WREG32(mmCP_PFP_UCODE_ADDR, 0);
1971 
1972     /* CE */
1973     fw_data = (const __le32 *)
1974         (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1975     fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1976     WREG32(mmCP_CE_UCODE_ADDR, 0);
1977     for (i = 0; i < fw_size; i++)
1978         WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
1979     WREG32(mmCP_CE_UCODE_ADDR, 0);
1980 
1981     /* ME */
1982     fw_data = (const __be32 *)
1983         (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
1984     fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
1985     WREG32(mmCP_ME_RAM_WADDR, 0);
1986     for (i = 0; i < fw_size; i++)
1987         WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
1988     WREG32(mmCP_ME_RAM_WADDR, 0);
1989 
1990     WREG32(mmCP_PFP_UCODE_ADDR, 0);
1991     WREG32(mmCP_CE_UCODE_ADDR, 0);
1992     WREG32(mmCP_ME_RAM_WADDR, 0);
1993     WREG32(mmCP_ME_RAM_RADDR, 0);
1994     return 0;
1995 }
1996 
1997 static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev)
1998 {
1999     const struct cs_section_def *sect = NULL;
2000     const struct cs_extent_def *ext = NULL;
2001     struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2002     int r, i;
2003 
2004     r = amdgpu_ring_alloc(ring, 7 + 4);
2005     if (r) {
2006         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2007         return r;
2008     }
2009     amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2010     amdgpu_ring_write(ring, 0x1);
2011     amdgpu_ring_write(ring, 0x0);
2012     amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);
2013     amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2014     amdgpu_ring_write(ring, 0);
2015     amdgpu_ring_write(ring, 0);
2016 
2017     amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2018     amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2019     amdgpu_ring_write(ring, 0xc000);
2020     amdgpu_ring_write(ring, 0xe000);
2021     amdgpu_ring_commit(ring);
2022 
2023     gfx_v6_0_cp_gfx_enable(adev, true);
2024 
2025     r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10);
2026     if (r) {
2027         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2028         return r;
2029     }
2030 
2031     amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2032     amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2033 
2034     for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2035         for (ext = sect->section; ext->extent != NULL; ++ext) {
2036             if (sect->id == SECT_CONTEXT) {
2037                 amdgpu_ring_write(ring,
2038                           PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2039                 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2040                 for (i = 0; i < ext->reg_count; i++)
2041                     amdgpu_ring_write(ring, ext->extent[i]);
2042             }
2043         }
2044     }
2045 
2046     amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2047     amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2048 
2049     amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2050     amdgpu_ring_write(ring, 0);
2051 
2052     amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2053     amdgpu_ring_write(ring, 0x00000316);
2054     amdgpu_ring_write(ring, 0x0000000e);
2055     amdgpu_ring_write(ring, 0x00000010);
2056 
2057     amdgpu_ring_commit(ring);
2058 
2059     return 0;
2060 }
2061 
2062 static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
2063 {
2064     struct amdgpu_ring *ring;
2065     u32 tmp;
2066     u32 rb_bufsz;
2067     int r;
2068     u64 rptr_addr;
2069 
2070     WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2071     WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2072 
2073     /* Set the write pointer delay */
2074     WREG32(mmCP_RB_WPTR_DELAY, 0);
2075 
2076     WREG32(mmCP_DEBUG, 0);
2077     WREG32(mmSCRATCH_ADDR, 0);
2078 
2079     /* ring 0 - compute and gfx */
2080     /* Set ring buffer size */
2081     ring = &adev->gfx.gfx_ring[0];
2082     rb_bufsz = order_base_2(ring->ring_size / 8);
2083     tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2084 
2085 #ifdef __BIG_ENDIAN
2086     tmp |= BUF_SWAP_32BIT;
2087 #endif
2088     WREG32(mmCP_RB0_CNTL, tmp);
2089 
2090     /* Initialize the ring buffer's read and write pointers */
2091     WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2092     ring->wptr = 0;
2093     WREG32(mmCP_RB0_WPTR, ring->wptr);
2094 
2095     /* set the wb address whether it's enabled or not */
2096     rptr_addr = ring->rptr_gpu_addr;
2097     WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2098     WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2099 
2100     WREG32(mmSCRATCH_UMSK, 0);
2101 
2102     mdelay(1);
2103     WREG32(mmCP_RB0_CNTL, tmp);
2104 
2105     WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8);
2106 
2107     /* start the rings */
2108     gfx_v6_0_cp_gfx_start(adev);
2109     r = amdgpu_ring_test_helper(ring);
2110     if (r)
2111         return r;
2112 
2113     return 0;
2114 }
2115 
2116 static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
2117 {
2118     return *ring->rptr_cpu_addr;
2119 }
2120 
2121 static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
2122 {
2123     struct amdgpu_device *adev = ring->adev;
2124 
2125     if (ring == &adev->gfx.gfx_ring[0])
2126         return RREG32(mmCP_RB0_WPTR);
2127     else if (ring == &adev->gfx.compute_ring[0])
2128         return RREG32(mmCP_RB1_WPTR);
2129     else if (ring == &adev->gfx.compute_ring[1])
2130         return RREG32(mmCP_RB2_WPTR);
2131     else
2132         BUG();
2133 }
2134 
2135 static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2136 {
2137     struct amdgpu_device *adev = ring->adev;
2138 
2139     WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2140     (void)RREG32(mmCP_RB0_WPTR);
2141 }
2142 
2143 static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2144 {
2145     struct amdgpu_device *adev = ring->adev;
2146 
2147     if (ring == &adev->gfx.compute_ring[0]) {
2148         WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2149         (void)RREG32(mmCP_RB1_WPTR);
2150     } else if (ring == &adev->gfx.compute_ring[1]) {
2151         WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr));
2152         (void)RREG32(mmCP_RB2_WPTR);
2153     } else {
2154         BUG();
2155     }
2156 
2157 }
2158 
2159 static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
2160 {
2161     struct amdgpu_ring *ring;
2162     u32 tmp;
2163     u32 rb_bufsz;
2164     int i, r;
2165     u64 rptr_addr;
2166 
2167     /* ring1  - compute only */
2168     /* Set ring buffer size */
2169 
2170     ring = &adev->gfx.compute_ring[0];
2171     rb_bufsz = order_base_2(ring->ring_size / 8);
2172     tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2173 #ifdef __BIG_ENDIAN
2174     tmp |= BUF_SWAP_32BIT;
2175 #endif
2176     WREG32(mmCP_RB1_CNTL, tmp);
2177 
2178     WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK);
2179     ring->wptr = 0;
2180     WREG32(mmCP_RB1_WPTR, ring->wptr);
2181 
2182     rptr_addr = ring->rptr_gpu_addr;
2183     WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2184     WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2185 
2186     mdelay(1);
2187     WREG32(mmCP_RB1_CNTL, tmp);
2188     WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8);
2189 
2190     ring = &adev->gfx.compute_ring[1];
2191     rb_bufsz = order_base_2(ring->ring_size / 8);
2192     tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2193 #ifdef __BIG_ENDIAN
2194     tmp |= BUF_SWAP_32BIT;
2195 #endif
2196     WREG32(mmCP_RB2_CNTL, tmp);
2197 
2198     WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK);
2199     ring->wptr = 0;
2200     WREG32(mmCP_RB2_WPTR, ring->wptr);
2201     rptr_addr = ring->rptr_gpu_addr;
2202     WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
2203     WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2204 
2205     mdelay(1);
2206     WREG32(mmCP_RB2_CNTL, tmp);
2207     WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8);
2208 
2209 
2210     for (i = 0; i < 2; i++) {
2211         r = amdgpu_ring_test_helper(&adev->gfx.compute_ring[i]);
2212         if (r)
2213             return r;
2214     }
2215 
2216     return 0;
2217 }
2218 
2219 static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
2220 {
2221     gfx_v6_0_cp_gfx_enable(adev, enable);
2222 }
2223 
2224 static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
2225 {
2226     return gfx_v6_0_cp_gfx_load_microcode(adev);
2227 }
2228 
2229 static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2230                            bool enable)
2231 {
2232     u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2233     u32 mask;
2234     int i;
2235 
2236     if (enable)
2237         tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2238             CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2239     else
2240         tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2241              CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2242     WREG32(mmCP_INT_CNTL_RING0, tmp);
2243 
2244     if (!enable) {
2245         /* read a gfx register */
2246         tmp = RREG32(mmDB_DEPTH_INFO);
2247 
2248         mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
2249         for (i = 0; i < adev->usec_timeout; i++) {
2250             if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
2251                 break;
2252             udelay(1);
2253         }
2254     }
2255 }
2256 
2257 static int gfx_v6_0_cp_resume(struct amdgpu_device *adev)
2258 {
2259     int r;
2260 
2261     gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2262 
2263     r = gfx_v6_0_cp_load_microcode(adev);
2264     if (r)
2265         return r;
2266 
2267     r = gfx_v6_0_cp_gfx_resume(adev);
2268     if (r)
2269         return r;
2270     r = gfx_v6_0_cp_compute_resume(adev);
2271     if (r)
2272         return r;
2273 
2274     gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2275 
2276     return 0;
2277 }
2278 
2279 static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2280 {
2281     int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2282     uint32_t seq = ring->fence_drv.sync_seq;
2283     uint64_t addr = ring->fence_drv.gpu_addr;
2284 
2285     amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2286     amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
2287                  WAIT_REG_MEM_FUNCTION(3) | /* equal */
2288                  WAIT_REG_MEM_ENGINE(usepfp)));   /* pfp or me */
2289     amdgpu_ring_write(ring, addr & 0xfffffffc);
2290     amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
2291     amdgpu_ring_write(ring, seq);
2292     amdgpu_ring_write(ring, 0xffffffff);
2293     amdgpu_ring_write(ring, 4); /* poll interval */
2294 
2295     if (usepfp) {
2296         /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2297         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2298         amdgpu_ring_write(ring, 0);
2299         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2300         amdgpu_ring_write(ring, 0);
2301     }
2302 }
2303 
2304 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2305                     unsigned vmid, uint64_t pd_addr)
2306 {
2307     int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2308 
2309     amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
2310 
2311     /* wait for the invalidate to complete */
2312     amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2313     amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) |  /* always */
2314                  WAIT_REG_MEM_ENGINE(0))); /* me */
2315     amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2316     amdgpu_ring_write(ring, 0);
2317     amdgpu_ring_write(ring, 0); /* ref */
2318     amdgpu_ring_write(ring, 0); /* mask */
2319     amdgpu_ring_write(ring, 0x20); /* poll interval */
2320 
2321     if (usepfp) {
2322         /* sync PFP to ME, otherwise we might get invalid PFP reads */
2323         amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2324         amdgpu_ring_write(ring, 0x0);
2325 
2326         /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2327         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2328         amdgpu_ring_write(ring, 0);
2329         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2330         amdgpu_ring_write(ring, 0);
2331     }
2332 }
2333 
2334 static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
2335                     uint32_t reg, uint32_t val)
2336 {
2337     int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2338 
2339     amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2340     amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
2341                  WRITE_DATA_DST_SEL(0)));
2342     amdgpu_ring_write(ring, reg);
2343     amdgpu_ring_write(ring, 0);
2344     amdgpu_ring_write(ring, val);
2345 }
2346 
2347 static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2348 {
2349     const u32 *src_ptr;
2350     volatile u32 *dst_ptr;
2351     u32 dws;
2352     u64 reg_list_mc_addr;
2353     const struct cs_section_def *cs_data;
2354     int r;
2355 
2356     adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
2357     adev->gfx.rlc.reg_list_size =
2358             (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
2359 
2360     adev->gfx.rlc.cs_data = si_cs_data;
2361     src_ptr = adev->gfx.rlc.reg_list;
2362     dws = adev->gfx.rlc.reg_list_size;
2363     cs_data = adev->gfx.rlc.cs_data;
2364 
2365     if (src_ptr) {
2366         /* init save restore block */
2367         r = amdgpu_gfx_rlc_init_sr(adev, dws);
2368         if (r)
2369             return r;
2370     }
2371 
2372     if (cs_data) {
2373         /* clear state block */
2374         adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
2375         dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2376 
2377         r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
2378                           AMDGPU_GEM_DOMAIN_VRAM,
2379                           &adev->gfx.rlc.clear_state_obj,
2380                           &adev->gfx.rlc.clear_state_gpu_addr,
2381                           (void **)&adev->gfx.rlc.cs_ptr);
2382         if (r) {
2383             dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2384             amdgpu_gfx_rlc_fini(adev);
2385             return r;
2386         }
2387 
2388         /* set up the cs buffer */
2389         dst_ptr = adev->gfx.rlc.cs_ptr;
2390         reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;
2391         dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
2392         dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
2393         dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);
2394         gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]);
2395         amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
2396         amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2397     }
2398 
2399     return 0;
2400 }
2401 
2402 static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2403 {
2404     WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
2405 
2406     if (!enable) {
2407         gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2408         WREG32(mmSPI_LB_CU_MASK, 0x00ff);
2409     }
2410 }
2411 
2412 static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2413 {
2414     int i;
2415 
2416     for (i = 0; i < adev->usec_timeout; i++) {
2417         if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0)
2418             break;
2419         udelay(1);
2420     }
2421 
2422     for (i = 0; i < adev->usec_timeout; i++) {
2423         if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0)
2424             break;
2425         udelay(1);
2426     }
2427 }
2428 
2429 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2430 {
2431     u32 tmp;
2432 
2433     tmp = RREG32(mmRLC_CNTL);
2434     if (tmp != rlc)
2435         WREG32(mmRLC_CNTL, rlc);
2436 }
2437 
2438 static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2439 {
2440     u32 data, orig;
2441 
2442     orig = data = RREG32(mmRLC_CNTL);
2443 
2444     if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2445         data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
2446         WREG32(mmRLC_CNTL, data);
2447 
2448         gfx_v6_0_wait_for_rlc_serdes(adev);
2449     }
2450 
2451     return orig;
2452 }
2453 
2454 static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2455 {
2456     WREG32(mmRLC_CNTL, 0);
2457 
2458     gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2459     gfx_v6_0_wait_for_rlc_serdes(adev);
2460 }
2461 
2462 static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2463 {
2464     WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
2465 
2466     gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2467 
2468     udelay(50);
2469 }
2470 
2471 static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2472 {
2473     WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2474     udelay(50);
2475     WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2476     udelay(50);
2477 }
2478 
2479 static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2480 {
2481     u32 tmp;
2482 
2483     /* Enable LBPW only for DDR3 */
2484     tmp = RREG32(mmMC_SEQ_MISC0);
2485     if ((tmp & 0xF0000000) == 0xB0000000)
2486         return true;
2487     return false;
2488 }
2489 
2490 static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2491 {
2492 }
2493 
2494 static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2495 {
2496     u32 i;
2497     const struct rlc_firmware_header_v1_0 *hdr;
2498     const __le32 *fw_data;
2499     u32 fw_size;
2500 
2501 
2502     if (!adev->gfx.rlc_fw)
2503         return -EINVAL;
2504 
2505     adev->gfx.rlc.funcs->stop(adev);
2506     adev->gfx.rlc.funcs->reset(adev);
2507     gfx_v6_0_init_pg(adev);
2508     gfx_v6_0_init_cg(adev);
2509 
2510     WREG32(mmRLC_RL_BASE, 0);
2511     WREG32(mmRLC_RL_SIZE, 0);
2512     WREG32(mmRLC_LB_CNTL, 0);
2513     WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff);
2514     WREG32(mmRLC_LB_CNTR_INIT, 0);
2515     WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
2516 
2517     WREG32(mmRLC_MC_CNTL, 0);
2518     WREG32(mmRLC_UCODE_CNTL, 0);
2519 
2520     hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2521     fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2522     fw_data = (const __le32 *)
2523         (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2524 
2525     amdgpu_ucode_print_rlc_hdr(&hdr->header);
2526 
2527     for (i = 0; i < fw_size; i++) {
2528         WREG32(mmRLC_UCODE_ADDR, i);
2529         WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++));
2530     }
2531     WREG32(mmRLC_UCODE_ADDR, 0);
2532 
2533     gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2534     adev->gfx.rlc.funcs->start(adev);
2535 
2536     return 0;
2537 }
2538 
2539 static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2540 {
2541     u32 data, orig, tmp;
2542 
2543     orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
2544 
2545     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2546         gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2547 
2548         WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080);
2549 
2550         tmp = gfx_v6_0_halt_rlc(adev);
2551 
2552         WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2553         WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2554         WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff);
2555 
2556         gfx_v6_0_wait_for_rlc_serdes(adev);
2557         gfx_v6_0_update_rlc(adev, tmp);
2558 
2559         WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff);
2560 
2561         data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2562     } else {
2563         gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2564 
2565         RREG32(mmCB_CGTT_SCLK_CTRL);
2566         RREG32(mmCB_CGTT_SCLK_CTRL);
2567         RREG32(mmCB_CGTT_SCLK_CTRL);
2568         RREG32(mmCB_CGTT_SCLK_CTRL);
2569 
2570         data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2571     }
2572 
2573     if (orig != data)
2574         WREG32(mmRLC_CGCG_CGLS_CTRL, data);
2575 
2576 }
2577 
2578 static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2579 {
2580 
2581     u32 data, orig, tmp = 0;
2582 
2583     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2584         orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2585         data = 0x96940200;
2586         if (orig != data)
2587             WREG32(mmCGTS_SM_CTRL_REG, data);
2588 
2589         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2590             orig = data = RREG32(mmCP_MEM_SLP_CNTL);
2591             data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2592             if (orig != data)
2593                 WREG32(mmCP_MEM_SLP_CNTL, data);
2594         }
2595 
2596         orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2597         data &= 0xffffffc0;
2598         if (orig != data)
2599             WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2600 
2601         tmp = gfx_v6_0_halt_rlc(adev);
2602 
2603         WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2604         WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2605         WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff);
2606 
2607         gfx_v6_0_update_rlc(adev, tmp);
2608     } else {
2609         orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2610         data |= 0x00000003;
2611         if (orig != data)
2612             WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2613 
2614         data = RREG32(mmCP_MEM_SLP_CNTL);
2615         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2616             data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2617             WREG32(mmCP_MEM_SLP_CNTL, data);
2618         }
2619         orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2620         data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK;
2621         if (orig != data)
2622             WREG32(mmCGTS_SM_CTRL_REG, data);
2623 
2624         tmp = gfx_v6_0_halt_rlc(adev);
2625 
2626         WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2627         WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2628         WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff);
2629 
2630         gfx_v6_0_update_rlc(adev, tmp);
2631     }
2632 }
2633 /*
2634 static void gfx_v6_0_update_cg(struct amdgpu_device *adev,
2635                    bool enable)
2636 {
2637     gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2638     if (enable) {
2639         gfx_v6_0_enable_mgcg(adev, true);
2640         gfx_v6_0_enable_cgcg(adev, true);
2641     } else {
2642         gfx_v6_0_enable_cgcg(adev, false);
2643         gfx_v6_0_enable_mgcg(adev, false);
2644     }
2645     gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2646 }
2647 */
2648 
2649 static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2650                         bool enable)
2651 {
2652 }
2653 
2654 static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
2655                         bool enable)
2656 {
2657 }
2658 
2659 static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2660 {
2661     u32 data, orig;
2662 
2663     orig = data = RREG32(mmRLC_PG_CNTL);
2664     if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2665         data &= ~0x8000;
2666     else
2667         data |= 0x8000;
2668     if (orig != data)
2669         WREG32(mmRLC_PG_CNTL, data);
2670 }
2671 
2672 static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
2673 {
2674 }
2675 /*
2676 static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev)
2677 {
2678     const __le32 *fw_data;
2679     volatile u32 *dst_ptr;
2680     int me, i, max_me = 4;
2681     u32 bo_offset = 0;
2682     u32 table_offset, table_size;
2683 
2684     if (adev->asic_type == CHIP_KAVERI)
2685         max_me = 5;
2686 
2687     if (adev->gfx.rlc.cp_table_ptr == NULL)
2688         return;
2689 
2690     dst_ptr = adev->gfx.rlc.cp_table_ptr;
2691     for (me = 0; me < max_me; me++) {
2692         if (me == 0) {
2693             const struct gfx_firmware_header_v1_0 *hdr =
2694                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2695             fw_data = (const __le32 *)
2696                 (adev->gfx.ce_fw->data +
2697                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2698             table_offset = le32_to_cpu(hdr->jt_offset);
2699             table_size = le32_to_cpu(hdr->jt_size);
2700         } else if (me == 1) {
2701             const struct gfx_firmware_header_v1_0 *hdr =
2702                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2703             fw_data = (const __le32 *)
2704                 (adev->gfx.pfp_fw->data +
2705                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2706             table_offset = le32_to_cpu(hdr->jt_offset);
2707             table_size = le32_to_cpu(hdr->jt_size);
2708         } else if (me == 2) {
2709             const struct gfx_firmware_header_v1_0 *hdr =
2710                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2711             fw_data = (const __le32 *)
2712                 (adev->gfx.me_fw->data +
2713                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2714             table_offset = le32_to_cpu(hdr->jt_offset);
2715             table_size = le32_to_cpu(hdr->jt_size);
2716         } else if (me == 3) {
2717             const struct gfx_firmware_header_v1_0 *hdr =
2718                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2719             fw_data = (const __le32 *)
2720                 (adev->gfx.mec_fw->data +
2721                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2722             table_offset = le32_to_cpu(hdr->jt_offset);
2723             table_size = le32_to_cpu(hdr->jt_size);
2724         } else {
2725             const struct gfx_firmware_header_v1_0 *hdr =
2726                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2727             fw_data = (const __le32 *)
2728                 (adev->gfx.mec2_fw->data +
2729                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2730             table_offset = le32_to_cpu(hdr->jt_offset);
2731             table_size = le32_to_cpu(hdr->jt_size);
2732         }
2733 
2734         for (i = 0; i < table_size; i ++) {
2735             dst_ptr[bo_offset + i] =
2736                 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
2737         }
2738 
2739         bo_offset += table_size;
2740     }
2741 }
2742 */
2743 static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2744                      bool enable)
2745 {
2746     if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2747         WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10));
2748         WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1);
2749         WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1);
2750     } else {
2751         WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0);
2752         (void)RREG32(mmDB_RENDER_CONTROL);
2753     }
2754 }
2755 
2756 static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2757 {
2758     u32 tmp;
2759 
2760     WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
2761 
2762     tmp = RREG32(mmRLC_MAX_PG_CU);
2763     tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
2764     tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
2765     WREG32(mmRLC_MAX_PG_CU, tmp);
2766 }
2767 
2768 static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2769                         bool enable)
2770 {
2771     u32 data, orig;
2772 
2773     orig = data = RREG32(mmRLC_PG_CNTL);
2774     if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
2775         data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2776     else
2777         data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2778     if (orig != data)
2779         WREG32(mmRLC_PG_CNTL, data);
2780 }
2781 
2782 static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2783                          bool enable)
2784 {
2785     u32 data, orig;
2786 
2787     orig = data = RREG32(mmRLC_PG_CNTL);
2788     if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
2789         data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2790     else
2791         data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2792     if (orig != data)
2793         WREG32(mmRLC_PG_CNTL, data);
2794 }
2795 
2796 static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2797 {
2798     u32 tmp;
2799 
2800     WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2801     WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1);
2802     WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2803 
2804     tmp = RREG32(mmRLC_AUTO_PG_CTRL);
2805     tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2806     tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2807     tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK;
2808     WREG32(mmRLC_AUTO_PG_CTRL, tmp);
2809 }
2810 
2811 static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
2812 {
2813     gfx_v6_0_enable_gfx_cgpg(adev, enable);
2814     gfx_v6_0_enable_gfx_static_mgpg(adev, enable);
2815     gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);
2816 }
2817 
2818 static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)
2819 {
2820     u32 count = 0;
2821     const struct cs_section_def *sect = NULL;
2822     const struct cs_extent_def *ext = NULL;
2823 
2824     if (adev->gfx.rlc.cs_data == NULL)
2825         return 0;
2826 
2827     /* begin clear state */
2828     count += 2;
2829     /* context control state */
2830     count += 3;
2831 
2832     for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2833         for (ext = sect->section; ext->extent != NULL; ++ext) {
2834             if (sect->id == SECT_CONTEXT)
2835                 count += 2 + ext->reg_count;
2836             else
2837                 return 0;
2838         }
2839     }
2840     /* pa_sc_raster_config */
2841     count += 3;
2842     /* end clear state */
2843     count += 2;
2844     /* clear state */
2845     count += 2;
2846 
2847     return count;
2848 }
2849 
2850 static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2851                     volatile u32 *buffer)
2852 {
2853     u32 count = 0, i;
2854     const struct cs_section_def *sect = NULL;
2855     const struct cs_extent_def *ext = NULL;
2856 
2857     if (adev->gfx.rlc.cs_data == NULL)
2858         return;
2859     if (buffer == NULL)
2860         return;
2861 
2862     buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2863     buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2864     buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2865     buffer[count++] = cpu_to_le32(0x80000000);
2866     buffer[count++] = cpu_to_le32(0x80000000);
2867 
2868     for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2869         for (ext = sect->section; ext->extent != NULL; ++ext) {
2870             if (sect->id == SECT_CONTEXT) {
2871                 buffer[count++] =
2872                     cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2873                 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
2874                 for (i = 0; i < ext->reg_count; i++)
2875                     buffer[count++] = cpu_to_le32(ext->extent[i]);
2876             } else {
2877                 return;
2878             }
2879         }
2880     }
2881 
2882     buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2883     buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2884     buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
2885 
2886     buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2887     buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
2888 
2889     buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
2890     buffer[count++] = cpu_to_le32(0);
2891 }
2892 
2893 static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
2894 {
2895     if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2896                   AMD_PG_SUPPORT_GFX_SMG |
2897                   AMD_PG_SUPPORT_GFX_DMG |
2898                   AMD_PG_SUPPORT_CP |
2899                   AMD_PG_SUPPORT_GDS |
2900                   AMD_PG_SUPPORT_RLC_SMU_HS)) {
2901         gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);
2902         gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);
2903         if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2904             gfx_v6_0_init_gfx_cgpg(adev);
2905             gfx_v6_0_enable_cp_pg(adev, true);
2906             gfx_v6_0_enable_gds_pg(adev, true);
2907         } else {
2908             WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2909             WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2910 
2911         }
2912         gfx_v6_0_init_ao_cu_mask(adev);
2913         gfx_v6_0_update_gfx_pg(adev, true);
2914     } else {
2915 
2916         WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2917         WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2918     }
2919 }
2920 
2921 static void gfx_v6_0_fini_pg(struct amdgpu_device *adev)
2922 {
2923     if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2924                   AMD_PG_SUPPORT_GFX_SMG |
2925                   AMD_PG_SUPPORT_GFX_DMG |
2926                   AMD_PG_SUPPORT_CP |
2927                   AMD_PG_SUPPORT_GDS |
2928                   AMD_PG_SUPPORT_RLC_SMU_HS)) {
2929         gfx_v6_0_update_gfx_pg(adev, false);
2930         if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2931             gfx_v6_0_enable_cp_pg(adev, false);
2932             gfx_v6_0_enable_gds_pg(adev, false);
2933         }
2934     }
2935 }
2936 
2937 static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2938 {
2939     uint64_t clock;
2940 
2941     mutex_lock(&adev->gfx.gpu_clock_mutex);
2942     WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
2943     clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
2944             ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
2945     mutex_unlock(&adev->gfx.gpu_clock_mutex);
2946     return clock;
2947 }
2948 
2949 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2950 {
2951     if (flags & AMDGPU_HAVE_CTX_SWITCH)
2952         gfx_v6_0_ring_emit_vgt_flush(ring);
2953     amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2954     amdgpu_ring_write(ring, 0x80000000);
2955     amdgpu_ring_write(ring, 0);
2956 }
2957 
2958 
2959 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
2960 {
2961     WREG32(mmSQ_IND_INDEX,
2962         (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
2963         (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
2964         (address << SQ_IND_INDEX__INDEX__SHIFT) |
2965         (SQ_IND_INDEX__FORCE_READ_MASK));
2966     return RREG32(mmSQ_IND_DATA);
2967 }
2968 
2969 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
2970                uint32_t wave, uint32_t thread,
2971                uint32_t regno, uint32_t num, uint32_t *out)
2972 {
2973     WREG32(mmSQ_IND_INDEX,
2974         (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
2975         (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
2976         (regno << SQ_IND_INDEX__INDEX__SHIFT) |
2977         (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
2978         (SQ_IND_INDEX__FORCE_READ_MASK) |
2979         (SQ_IND_INDEX__AUTO_INCR_MASK));
2980     while (num--)
2981         *(out++) = RREG32(mmSQ_IND_DATA);
2982 }
2983 
2984 static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
2985 {
2986     /* type 0 wave data */
2987     dst[(*no_fields)++] = 0;
2988     dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
2989     dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
2990     dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
2991     dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
2992     dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
2993     dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
2994     dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
2995     dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
2996     dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
2997     dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
2998     dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
2999     dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
3000     dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
3001     dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
3002     dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
3003     dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
3004     dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
3005     dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
3006     dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE);
3007 }
3008 
3009 static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
3010                      uint32_t wave, uint32_t start,
3011                      uint32_t size, uint32_t *dst)
3012 {
3013     wave_read_regs(
3014         adev, simd, wave, 0,
3015         start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
3016 }
3017 
3018 static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev,
3019                   u32 me, u32 pipe, u32 q, u32 vm)
3020 {
3021     DRM_INFO("Not implemented\n");
3022 }
3023 
3024 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
3025     .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
3026     .select_se_sh = &gfx_v6_0_select_se_sh,
3027     .read_wave_data = &gfx_v6_0_read_wave_data,
3028     .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs,
3029     .select_me_pipe_q = &gfx_v6_0_select_me_pipe_q
3030 };
3031 
3032 static const struct amdgpu_rlc_funcs gfx_v6_0_rlc_funcs = {
3033     .init = gfx_v6_0_rlc_init,
3034     .resume = gfx_v6_0_rlc_resume,
3035     .stop = gfx_v6_0_rlc_stop,
3036     .reset = gfx_v6_0_rlc_reset,
3037     .start = gfx_v6_0_rlc_start
3038 };
3039 
3040 static int gfx_v6_0_early_init(void *handle)
3041 {
3042     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3043 
3044     adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
3045     adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
3046                       GFX6_NUM_COMPUTE_RINGS);
3047     adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
3048     adev->gfx.rlc.funcs = &gfx_v6_0_rlc_funcs;
3049     gfx_v6_0_set_ring_funcs(adev);
3050     gfx_v6_0_set_irq_funcs(adev);
3051 
3052     return 0;
3053 }
3054 
3055 static int gfx_v6_0_sw_init(void *handle)
3056 {
3057     struct amdgpu_ring *ring;
3058     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3059     int i, r;
3060 
3061     r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
3062     if (r)
3063         return r;
3064 
3065     r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq);
3066     if (r)
3067         return r;
3068 
3069     r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq);
3070     if (r)
3071         return r;
3072 
3073     r = gfx_v6_0_init_microcode(adev);
3074     if (r) {
3075         DRM_ERROR("Failed to load gfx firmware!\n");
3076         return r;
3077     }
3078 
3079     r = adev->gfx.rlc.funcs->init(adev);
3080     if (r) {
3081         DRM_ERROR("Failed to init rlc BOs!\n");
3082         return r;
3083     }
3084 
3085     for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3086         ring = &adev->gfx.gfx_ring[i];
3087         ring->ring_obj = NULL;
3088         sprintf(ring->name, "gfx");
3089         r = amdgpu_ring_init(adev, ring, 1024,
3090                      &adev->gfx.eop_irq,
3091                      AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP,
3092                      AMDGPU_RING_PRIO_DEFAULT, NULL);
3093         if (r)
3094             return r;
3095     }
3096 
3097     for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3098         unsigned irq_type;
3099 
3100         if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
3101             DRM_ERROR("Too many (%d) compute rings!\n", i);
3102             break;
3103         }
3104         ring = &adev->gfx.compute_ring[i];
3105         ring->ring_obj = NULL;
3106         ring->use_doorbell = false;
3107         ring->doorbell_index = 0;
3108         ring->me = 1;
3109         ring->pipe = i;
3110         ring->queue = i;
3111         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
3112         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
3113         r = amdgpu_ring_init(adev, ring, 1024,
3114                      &adev->gfx.eop_irq, irq_type,
3115                      AMDGPU_RING_PRIO_DEFAULT, NULL);
3116         if (r)
3117             return r;
3118     }
3119 
3120     return r;
3121 }
3122 
3123 static int gfx_v6_0_sw_fini(void *handle)
3124 {
3125     int i;
3126     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3127 
3128     for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3129         amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
3130     for (i = 0; i < adev->gfx.num_compute_rings; i++)
3131         amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
3132 
3133     amdgpu_gfx_rlc_fini(adev);
3134 
3135     return 0;
3136 }
3137 
3138 static int gfx_v6_0_hw_init(void *handle)
3139 {
3140     int r;
3141     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3142 
3143     gfx_v6_0_constants_init(adev);
3144 
3145     r = adev->gfx.rlc.funcs->resume(adev);
3146     if (r)
3147         return r;
3148 
3149     r = gfx_v6_0_cp_resume(adev);
3150     if (r)
3151         return r;
3152 
3153     adev->gfx.ce_ram_size = 0x8000;
3154 
3155     return r;
3156 }
3157 
3158 static int gfx_v6_0_hw_fini(void *handle)
3159 {
3160     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3161 
3162     gfx_v6_0_cp_enable(adev, false);
3163     adev->gfx.rlc.funcs->stop(adev);
3164     gfx_v6_0_fini_pg(adev);
3165 
3166     return 0;
3167 }
3168 
3169 static int gfx_v6_0_suspend(void *handle)
3170 {
3171     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3172 
3173     return gfx_v6_0_hw_fini(adev);
3174 }
3175 
3176 static int gfx_v6_0_resume(void *handle)
3177 {
3178     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3179 
3180     return gfx_v6_0_hw_init(adev);
3181 }
3182 
3183 static bool gfx_v6_0_is_idle(void *handle)
3184 {
3185     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3186 
3187     if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
3188         return false;
3189     else
3190         return true;
3191 }
3192 
3193 static int gfx_v6_0_wait_for_idle(void *handle)
3194 {
3195     unsigned i;
3196     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3197 
3198     for (i = 0; i < adev->usec_timeout; i++) {
3199         if (gfx_v6_0_is_idle(handle))
3200             return 0;
3201         udelay(1);
3202     }
3203     return -ETIMEDOUT;
3204 }
3205 
3206 static int gfx_v6_0_soft_reset(void *handle)
3207 {
3208     return 0;
3209 }
3210 
3211 static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3212                          enum amdgpu_interrupt_state state)
3213 {
3214     u32 cp_int_cntl;
3215 
3216     switch (state) {
3217     case AMDGPU_IRQ_STATE_DISABLE:
3218         cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3219         cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3220         WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3221         break;
3222     case AMDGPU_IRQ_STATE_ENABLE:
3223         cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3224         cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3225         WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3226         break;
3227     default:
3228         break;
3229     }
3230 }
3231 
3232 static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3233                              int ring,
3234                              enum amdgpu_interrupt_state state)
3235 {
3236     u32 cp_int_cntl;
3237     switch (state){
3238     case AMDGPU_IRQ_STATE_DISABLE:
3239         if (ring == 0) {
3240             cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3241             cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3242             WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3243             break;
3244         } else {
3245             cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3246             cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3247             WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3248             break;
3249 
3250         }
3251     case AMDGPU_IRQ_STATE_ENABLE:
3252         if (ring == 0) {
3253             cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3254             cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3255             WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3256             break;
3257         } else {
3258             cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3259             cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3260             WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3261             break;
3262 
3263         }
3264 
3265     default:
3266         BUG();
3267         break;
3268 
3269     }
3270 }
3271 
3272 static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3273                          struct amdgpu_irq_src *src,
3274                          unsigned type,
3275                          enum amdgpu_interrupt_state state)
3276 {
3277     u32 cp_int_cntl;
3278 
3279     switch (state) {
3280     case AMDGPU_IRQ_STATE_DISABLE:
3281         cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3282         cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3283         WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3284         break;
3285     case AMDGPU_IRQ_STATE_ENABLE:
3286         cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3287         cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3288         WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3289         break;
3290     default:
3291         break;
3292     }
3293 
3294     return 0;
3295 }
3296 
3297 static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3298                           struct amdgpu_irq_src *src,
3299                           unsigned type,
3300                           enum amdgpu_interrupt_state state)
3301 {
3302     u32 cp_int_cntl;
3303 
3304     switch (state) {
3305     case AMDGPU_IRQ_STATE_DISABLE:
3306         cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3307         cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3308         WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3309         break;
3310     case AMDGPU_IRQ_STATE_ENABLE:
3311         cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3312         cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3313         WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3314         break;
3315     default:
3316         break;
3317     }
3318 
3319     return 0;
3320 }
3321 
3322 static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3323                         struct amdgpu_irq_src *src,
3324                         unsigned type,
3325                         enum amdgpu_interrupt_state state)
3326 {
3327     switch (type) {
3328     case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
3329         gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
3330         break;
3331     case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3332         gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state);
3333         break;
3334     case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3335         gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state);
3336         break;
3337     default:
3338         break;
3339     }
3340     return 0;
3341 }
3342 
3343 static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3344                 struct amdgpu_irq_src *source,
3345                 struct amdgpu_iv_entry *entry)
3346 {
3347     switch (entry->ring_id) {
3348     case 0:
3349         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3350         break;
3351     case 1:
3352     case 2:
3353         amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]);
3354         break;
3355     default:
3356         break;
3357     }
3358     return 0;
3359 }
3360 
3361 static void gfx_v6_0_fault(struct amdgpu_device *adev,
3362                struct amdgpu_iv_entry *entry)
3363 {
3364     struct amdgpu_ring *ring;
3365 
3366     switch (entry->ring_id) {
3367     case 0:
3368         ring = &adev->gfx.gfx_ring[0];
3369         break;
3370     case 1:
3371     case 2:
3372         ring = &adev->gfx.compute_ring[entry->ring_id - 1];
3373         break;
3374     default:
3375         return;
3376     }
3377     drm_sched_fault(&ring->sched);
3378 }
3379 
3380 static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev,
3381                  struct amdgpu_irq_src *source,
3382                  struct amdgpu_iv_entry *entry)
3383 {
3384     DRM_ERROR("Illegal register access in command stream\n");
3385     gfx_v6_0_fault(adev, entry);
3386     return 0;
3387 }
3388 
3389 static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
3390                   struct amdgpu_irq_src *source,
3391                   struct amdgpu_iv_entry *entry)
3392 {
3393     DRM_ERROR("Illegal instruction in command stream\n");
3394     gfx_v6_0_fault(adev, entry);
3395     return 0;
3396 }
3397 
3398 static int gfx_v6_0_set_clockgating_state(void *handle,
3399                       enum amd_clockgating_state state)
3400 {
3401     bool gate = false;
3402     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3403 
3404     if (state == AMD_CG_STATE_GATE)
3405         gate = true;
3406 
3407     gfx_v6_0_enable_gui_idle_interrupt(adev, false);
3408     if (gate) {
3409         gfx_v6_0_enable_mgcg(adev, true);
3410         gfx_v6_0_enable_cgcg(adev, true);
3411     } else {
3412         gfx_v6_0_enable_cgcg(adev, false);
3413         gfx_v6_0_enable_mgcg(adev, false);
3414     }
3415     gfx_v6_0_enable_gui_idle_interrupt(adev, true);
3416 
3417     return 0;
3418 }
3419 
3420 static int gfx_v6_0_set_powergating_state(void *handle,
3421                       enum amd_powergating_state state)
3422 {
3423     bool gate = false;
3424     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3425 
3426     if (state == AMD_PG_STATE_GATE)
3427         gate = true;
3428 
3429     if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3430                   AMD_PG_SUPPORT_GFX_SMG |
3431                   AMD_PG_SUPPORT_GFX_DMG |
3432                   AMD_PG_SUPPORT_CP |
3433                   AMD_PG_SUPPORT_GDS |
3434                   AMD_PG_SUPPORT_RLC_SMU_HS)) {
3435         gfx_v6_0_update_gfx_pg(adev, gate);
3436         if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3437             gfx_v6_0_enable_cp_pg(adev, gate);
3438             gfx_v6_0_enable_gds_pg(adev, gate);
3439         }
3440     }
3441 
3442     return 0;
3443 }
3444 
3445 static void gfx_v6_0_emit_mem_sync(struct amdgpu_ring *ring)
3446 {
3447     amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3448     amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
3449               PACKET3_TC_ACTION_ENA |
3450               PACKET3_SH_KCACHE_ACTION_ENA |
3451               PACKET3_SH_ICACHE_ACTION_ENA);  /* CP_COHER_CNTL */
3452     amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
3453     amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE */
3454     amdgpu_ring_write(ring, 0x0000000A); /* poll interval */
3455 }
3456 
3457 static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
3458     .name = "gfx_v6_0",
3459     .early_init = gfx_v6_0_early_init,
3460     .late_init = NULL,
3461     .sw_init = gfx_v6_0_sw_init,
3462     .sw_fini = gfx_v6_0_sw_fini,
3463     .hw_init = gfx_v6_0_hw_init,
3464     .hw_fini = gfx_v6_0_hw_fini,
3465     .suspend = gfx_v6_0_suspend,
3466     .resume = gfx_v6_0_resume,
3467     .is_idle = gfx_v6_0_is_idle,
3468     .wait_for_idle = gfx_v6_0_wait_for_idle,
3469     .soft_reset = gfx_v6_0_soft_reset,
3470     .set_clockgating_state = gfx_v6_0_set_clockgating_state,
3471     .set_powergating_state = gfx_v6_0_set_powergating_state,
3472 };
3473 
3474 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
3475     .type = AMDGPU_RING_TYPE_GFX,
3476     .align_mask = 0xff,
3477     .nop = 0x80000000,
3478     .support_64bit_ptrs = false,
3479     .get_rptr = gfx_v6_0_ring_get_rptr,
3480     .get_wptr = gfx_v6_0_ring_get_wptr,
3481     .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
3482     .emit_frame_size =
3483         5 + 5 + /* hdp flush / invalidate */
3484         14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3485         7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
3486         SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
3487         3 + 2 + /* gfx_v6_ring_emit_cntxcntl including vgt flush */
3488         5, /* SURFACE_SYNC */
3489     .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3490     .emit_ib = gfx_v6_0_ring_emit_ib,
3491     .emit_fence = gfx_v6_0_ring_emit_fence,
3492     .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3493     .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3494     .test_ring = gfx_v6_0_ring_test_ring,
3495     .test_ib = gfx_v6_0_ring_test_ib,
3496     .insert_nop = amdgpu_ring_insert_nop,
3497     .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
3498     .emit_wreg = gfx_v6_0_ring_emit_wreg,
3499     .emit_mem_sync = gfx_v6_0_emit_mem_sync,
3500 };
3501 
3502 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
3503     .type = AMDGPU_RING_TYPE_COMPUTE,
3504     .align_mask = 0xff,
3505     .nop = 0x80000000,
3506     .get_rptr = gfx_v6_0_ring_get_rptr,
3507     .get_wptr = gfx_v6_0_ring_get_wptr,
3508     .set_wptr = gfx_v6_0_ring_set_wptr_compute,
3509     .emit_frame_size =
3510         5 + 5 + /* hdp flush / invalidate */
3511         7 + /* gfx_v6_0_ring_emit_pipeline_sync */
3512         SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */
3513         14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3514         5, /* SURFACE_SYNC */
3515     .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3516     .emit_ib = gfx_v6_0_ring_emit_ib,
3517     .emit_fence = gfx_v6_0_ring_emit_fence,
3518     .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3519     .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3520     .test_ring = gfx_v6_0_ring_test_ring,
3521     .test_ib = gfx_v6_0_ring_test_ib,
3522     .insert_nop = amdgpu_ring_insert_nop,
3523     .emit_wreg = gfx_v6_0_ring_emit_wreg,
3524     .emit_mem_sync = gfx_v6_0_emit_mem_sync,
3525 };
3526 
3527 static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
3528 {
3529     int i;
3530 
3531     for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3532         adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;
3533     for (i = 0; i < adev->gfx.num_compute_rings; i++)
3534         adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;
3535 }
3536 
3537 static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = {
3538     .set = gfx_v6_0_set_eop_interrupt_state,
3539     .process = gfx_v6_0_eop_irq,
3540 };
3541 
3542 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = {
3543     .set = gfx_v6_0_set_priv_reg_fault_state,
3544     .process = gfx_v6_0_priv_reg_irq,
3545 };
3546 
3547 static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = {
3548     .set = gfx_v6_0_set_priv_inst_fault_state,
3549     .process = gfx_v6_0_priv_inst_irq,
3550 };
3551 
3552 static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3553 {
3554     adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3555     adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;
3556 
3557     adev->gfx.priv_reg_irq.num_types = 1;
3558     adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;
3559 
3560     adev->gfx.priv_inst_irq.num_types = 1;
3561     adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;
3562 }
3563 
3564 static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3565 {
3566     int i, j, k, counter, active_cu_number = 0;
3567     u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3568     struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3569     unsigned disable_masks[4 * 2];
3570     u32 ao_cu_num;
3571 
3572     if (adev->flags & AMD_IS_APU)
3573         ao_cu_num = 2;
3574     else
3575         ao_cu_num = adev->gfx.config.max_cu_per_sh;
3576 
3577     memset(cu_info, 0, sizeof(*cu_info));
3578 
3579     amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
3580 
3581     mutex_lock(&adev->grbm_idx_mutex);
3582     for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3583         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3584             mask = 1;
3585             ao_bitmap = 0;
3586             counter = 0;
3587             gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
3588             if (i < 4 && j < 2)
3589                 gfx_v6_0_set_user_cu_inactive_bitmap(
3590                     adev, disable_masks[i * 2 + j]);
3591             bitmap = gfx_v6_0_get_cu_enabled(adev);
3592             cu_info->bitmap[i][j] = bitmap;
3593 
3594             for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
3595                 if (bitmap & mask) {
3596                     if (counter < ao_cu_num)
3597                         ao_bitmap |= mask;
3598                     counter ++;
3599                 }
3600                 mask <<= 1;
3601             }
3602             active_cu_number += counter;
3603             if (i < 2 && j < 2)
3604                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3605             cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
3606         }
3607     }
3608 
3609     gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3610     mutex_unlock(&adev->grbm_idx_mutex);
3611 
3612     cu_info->number = active_cu_number;
3613     cu_info->ao_cu_mask = ao_cu_mask;
3614 }
3615 
3616 const struct amdgpu_ip_block_version gfx_v6_0_ip_block =
3617 {
3618     .type = AMD_IP_BLOCK_TYPE_GFX,
3619     .major = 6,
3620     .minor = 0,
3621     .rev = 0,
3622     .funcs = &gfx_v6_0_ip_funcs,
3623 };
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