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OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #include <linux/delay.h>
0025 #include <linux/kernel.h>
0026 #include <linux/firmware.h>
0027 #include <linux/module.h>
0028 #include <linux/pci.h>
0029 #include "amdgpu.h"
0030 #include "amdgpu_gfx.h"
0031 #include "amdgpu_psp.h"
0032 #include "nv.h"
0033 #include "nvd.h"
0034 
0035 #include "gc/gc_10_1_0_offset.h"
0036 #include "gc/gc_10_1_0_sh_mask.h"
0037 #include "smuio/smuio_11_0_0_offset.h"
0038 #include "smuio/smuio_11_0_0_sh_mask.h"
0039 #include "navi10_enum.h"
0040 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
0041 
0042 #include "soc15.h"
0043 #include "soc15d.h"
0044 #include "soc15_common.h"
0045 #include "clearstate_gfx10.h"
0046 #include "v10_structs.h"
0047 #include "gfx_v10_0.h"
0048 #include "nbio_v2_3.h"
0049 
0050 /*
0051  * Navi10 has two graphic rings to share each graphic pipe.
0052  * 1. Primary ring
0053  * 2. Async ring
0054  */
0055 #define GFX10_NUM_GFX_RINGS_NV1X    1
0056 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid  2
0057 #define GFX10_MEC_HPD_SIZE  2048
0058 
0059 #define F32_CE_PROGRAM_RAM_SIZE     65536
0060 #define RLCG_UCODE_LOADING_START_ADDRESS    0x00002000L
0061 
0062 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
0063 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
0064 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
0065 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
0066 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
0067 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
0068 
0069 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
0070 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
0071 
0072 #define mmCGTS_TCC_DISABLE_gc_10_3                 0x5006
0073 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX        1
0074 #define mmCGTS_USER_TCC_DISABLE_gc_10_3            0x5007
0075 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX   1
0076 
0077 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
0078 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
0079 #define mmRLC_SAFE_MODE_Sienna_Cichlid          0x4ca0
0080 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX     1
0081 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid      0x4ca1
0082 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1
0083 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid            0x11ec
0084 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX       0
0085 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid     0x0fc1
0086 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
0087 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid     0x0fc2
0088 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
0089 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid           0x0fc3
0090 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX  0
0091 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid       0x0fc4
0092 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
0093 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid     0x0fc5
0094 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
0095 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid      0x0fc6
0096 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
0097 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
0098 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK  0x04000000L
0099 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
0100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
0101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
0102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid           0x1580
0103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX  0
0104 
0105 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
0106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
0107 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
0108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
0109 
0110 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6                0x002d
0111 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX       1
0112 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6                0x002e
0113 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX       1
0114 
0115 #define mmSPI_CONFIG_CNTL_1_Vangogh      0x2441
0116 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX     1
0117 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
0118 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
0119 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
0120 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
0121 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
0122 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
0123 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
0124 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
0125 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
0126 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
0127 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
0128 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
0129 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
0130 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
0131 #define mmGCR_GENERAL_CNTL_Vangogh               0x1580
0132 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
0133 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh   0x0000FFFFL
0134 
0135 #define mmCP_HYP_PFP_UCODE_ADDR         0x5814
0136 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX    1
0137 #define mmCP_HYP_PFP_UCODE_DATA         0x5815
0138 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX    1
0139 #define mmCP_HYP_CE_UCODE_ADDR          0x5818
0140 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX     1
0141 #define mmCP_HYP_CE_UCODE_DATA          0x5819
0142 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX     1
0143 #define mmCP_HYP_ME_UCODE_ADDR          0x5816
0144 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX     1
0145 #define mmCP_HYP_ME_UCODE_DATA          0x5817
0146 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX     1
0147 
0148 #define mmCPG_PSP_DEBUG             0x5c10
0149 #define mmCPG_PSP_DEBUG_BASE_IDX        1
0150 #define mmCPC_PSP_DEBUG             0x5c11
0151 #define mmCPC_PSP_DEBUG_BASE_IDX        1
0152 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK    0x00000008L
0153 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK    0x00000008L
0154 
0155 //CC_GC_SA_UNIT_DISABLE
0156 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
0157 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
0158 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT    0x8
0159 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK      0x0000FF00L
0160 //GC_USER_SA_UNIT_DISABLE
0161 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
0162 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
0163 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT  0x8
0164 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK    0x0000FF00L
0165 //PA_SC_ENHANCE_3
0166 #define mmPA_SC_ENHANCE_3                       0x1085
0167 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
0168 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
0169 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
0170 
0171 #define mmCGTT_SPI_CS_CLK_CTRL          0x507c
0172 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
0173 
0174 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid      0x16f3
0175 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
0176 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
0177 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
0178 
0179 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
0180 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
0181 
0182 #define mmRLC_SPARE_INT_0_Sienna_Cichlid               0x4ca5
0183 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX      1
0184 
0185 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
0186 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
0187 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
0188 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
0189 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
0190 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
0191 
0192 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
0193 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
0194 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
0195 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
0196 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
0197 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
0198 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
0199 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
0200 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
0201 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
0202 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
0203 
0204 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
0205 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
0206 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
0207 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
0208 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
0209 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
0210 
0211 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
0212 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
0213 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
0214 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
0215 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
0216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
0217 
0218 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
0219 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
0220 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
0221 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
0222 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
0223 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
0224 
0225 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
0226 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
0227 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
0228 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
0229 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
0230 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
0231 
0232 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
0233 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
0234 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
0235 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
0236 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
0237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
0238 
0239 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
0240 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
0241 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
0242 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
0243 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
0244 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
0245 
0246 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
0247 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
0248 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
0249 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
0250 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
0251 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
0252 
0253 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin");
0254 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin");
0255 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin");
0256 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
0257 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
0258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
0259 
0260 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");
0261 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");
0262 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");
0263 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");
0264 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");
0265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");
0266 
0267 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
0268 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
0269 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
0270 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
0271 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
0272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
0273 
0274 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
0275 {
0276     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
0277     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
0278     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
0279     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
0280     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
0281     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
0282     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
0283     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
0284     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
0285     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
0286     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
0287     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
0288     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
0289     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
0290     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
0291     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
0292     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
0293     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
0294     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
0295     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
0296     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
0297     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
0298     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
0299     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
0300     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
0301     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
0302     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
0303     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
0304     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
0305     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
0306     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
0307     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
0308     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
0309     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
0310     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
0311     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
0312     SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
0313     SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
0314     SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
0315     SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
0316 };
0317 
0318 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
0319 {
0320     /* Pending on emulation bring up */
0321 };
0322 
0323 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
0324 {
0325     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
0326     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0327     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
0328     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0329     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
0330     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0331     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
0332     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0333     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
0334     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0335     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
0336     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0337     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
0338     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0339     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
0340     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0341     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
0342     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0343     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
0344     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0345     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
0346     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0347     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
0348     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0349     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
0350     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0351     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
0352     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0353     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
0354     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0355     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
0356     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0357     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
0358     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0359     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
0360     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0361     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
0362     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0363     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
0364     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0365     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
0366     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0367     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
0368     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0369     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
0370     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0371     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
0372     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0373     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
0374     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0375     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
0376     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0377     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
0378     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0379     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
0380     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0381     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
0382     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0383     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
0384     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0385     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
0386     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0387     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
0388     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0389     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
0390     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0391     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
0392     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0393     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
0394     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0395     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
0396     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0397     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
0398     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0399     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
0400     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0401     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
0402     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0403     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
0404     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0405     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
0406     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0407     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
0408     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0409     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
0410     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0411     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
0412     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0413     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
0414     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0415     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
0416     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0417     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
0418     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0419     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
0420     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0421     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
0422     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0423     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
0424     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0425     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
0426     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0427     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
0428     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0429     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
0430     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0431     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
0432     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0433     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
0434     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0435     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
0436     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0437     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
0438     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0439     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
0440     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0441     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
0442     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0443     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
0444     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0445     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
0446     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0447     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
0448     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0449     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
0450     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0451     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
0452     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0453     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
0454     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0455     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
0456     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0457     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
0458     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0459     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
0460     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0461     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
0462     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0463     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
0464     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0465     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
0466     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0467     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
0468     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0469     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
0470     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0471     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
0472     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0473     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
0474     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0475     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
0476     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0477     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
0478     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0479     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
0480     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0481     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
0482     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0483     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
0484     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0485     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
0486     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0487     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
0488     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0489     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
0490     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0491     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
0492     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0493     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
0494     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0495     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
0496     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0497     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
0498     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0499     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
0500     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0501     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
0502     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0503     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
0504     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0505     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
0506     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0507     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
0508     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0509     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
0510     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0511     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
0512     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0513     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
0514     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0515     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
0516     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0517     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
0518     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0519     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
0520     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0521     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
0522     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0523     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
0524     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0525     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
0526     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0527     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
0528     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0529     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
0530     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0531     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
0532     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0533     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
0534     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0535     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
0536     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0537     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
0538     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0539     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
0540     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0541     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
0542     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0543     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
0544     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0545     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
0546     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0547     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
0548     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0549     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
0550     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0551     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
0552     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0553     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
0554     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0555     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
0556     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0557     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
0558     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0559     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
0560     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0561     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
0562     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0563     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
0564     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0565     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
0566     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0567     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
0568     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0569     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
0570     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0571     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
0572     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0573     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
0574     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0575     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
0576     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0577     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
0578     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0579     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
0580     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0581     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
0582     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0583     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
0584     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0585     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
0586     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0587     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
0588     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0589     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
0590     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0591     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
0592     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0593     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
0594     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0595     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
0596     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0597     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
0598     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0599     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
0600     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0601     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
0602     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0603     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
0604     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0605     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
0606     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0607     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
0608     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0609     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
0610     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0611     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
0612     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0613     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
0614     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0615     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
0616     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0617     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
0618     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0619     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
0620     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0621     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
0622     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0623     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
0624     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0625     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
0626     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0627     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
0628     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0629     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
0630     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0631     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
0632     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0633     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
0634     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0635     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
0636     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0637     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
0638     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0639     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
0640     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0641     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
0642     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0643     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
0644     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0645     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
0646     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0647     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
0648     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0649     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
0650     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0651     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
0652     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0653     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
0654     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0655     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
0656     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0657     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
0658     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0659     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
0660     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0661     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
0662     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0663     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
0664     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0665     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
0666     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0667     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
0668     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0669     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
0670     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0671     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
0672     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0673     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
0674     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0675     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
0676     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0677     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
0678     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0679     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
0680     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0681     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
0682     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0683     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
0684     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0685     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
0686     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0687     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
0688     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0689     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
0690     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0691     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
0692     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0693     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
0694     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0695     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
0696     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0697     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
0698     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0699     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
0700     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0701     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
0702     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0703     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
0704     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0705     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
0706     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0707     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
0708     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0709     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
0710     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0711     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
0712     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0713     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
0714     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0715     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
0716     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0717     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
0718     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0719     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
0720     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0721     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
0722     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0723     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
0724     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0725     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
0726     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0727     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
0728     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0729     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
0730     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0731     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
0732     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0733     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
0734     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0735     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
0736     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0737     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
0738     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0739     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
0740     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0741     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
0742     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0743     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
0744     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0745     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
0746     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0747     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
0748     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0749     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
0750     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0751     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
0752     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0753     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
0754     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0755     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
0756     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0757     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
0758     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0759     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
0760     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0761     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
0762     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0763     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
0764     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0765     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
0766     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0767     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
0768     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0769     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
0770     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0771     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
0772     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0773     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
0774     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0775     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
0776     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0777     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
0778     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0779     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
0780     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0781     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
0782     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0783     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
0784     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0785     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
0786     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0787     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
0788     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0789     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
0790     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0791     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
0792     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0793     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
0794     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0795     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
0796     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0797     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
0798     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0799     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
0800     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0801     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
0802     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0803     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
0804     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0805     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
0806     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0807     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
0808     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0809     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
0810     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0811     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
0812     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0813     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
0814     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0815     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
0816     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0817     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
0818     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0819     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
0820     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0821     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
0822     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0823     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
0824     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0825     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
0826     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0827     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
0828     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0829     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
0830     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0831     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
0832     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0833     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
0834     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0835     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
0836     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0837     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
0838     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0839     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
0840     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0841     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
0842     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0843     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
0844     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0845     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
0846     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0847     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
0848     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0849     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
0850     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0851     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
0852     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0853     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
0854     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0855     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
0856     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0857     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
0858     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0859     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
0860     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0861     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
0862     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0863     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
0864     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0865     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
0866     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0867     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
0868     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0869     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
0870     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0871     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
0872     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0873     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
0874     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0875     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
0876     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0877     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
0878     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0879     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
0880     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0881     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
0882     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0883     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
0884     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0885     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
0886     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0887     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
0888     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0889     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
0890     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0891     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
0892     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0893     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
0894     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0895     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
0896     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0897     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
0898     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0899     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
0900     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0901     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
0902     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0903     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
0904     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0905     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
0906     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0907     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
0908     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0909     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
0910     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0911     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
0912     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0913     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
0914     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0915     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
0916     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0917     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
0918     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0919     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
0920     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0921     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
0922     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0923     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
0924     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0925     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
0926     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0927     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
0928     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0929     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
0930     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0931     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
0932     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0933     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
0934     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0935     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
0936     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0937     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
0938     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0939     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
0940     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0941     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
0942     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0943     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
0944     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0945     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
0946     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0947     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
0948     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0949     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
0950     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0951     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
0952     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0953     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
0954     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0955     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
0956     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0957     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
0958     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0959     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
0960     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0961     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
0962     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0963     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
0964     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0965     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
0966     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0967     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
0968     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0969     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
0970     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0971     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
0972     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0973     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
0974     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0975     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
0976     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0977     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
0978     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0979     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
0980     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0981     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
0982     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0983     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
0984     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0985     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
0986     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0987     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
0988     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0989     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
0990     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0991     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
0992     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0993     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
0994     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0995     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
0996     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
0997     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
0998     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
0999     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1000     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1001     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1002     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1003     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1004     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1005     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1006     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1007     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1008     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1009     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1010     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1011     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1012     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1013     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1014     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1015     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1016     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1017     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1018     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1019     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1020     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1021     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1022     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1023     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1024     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1025     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1026     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1027     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1028     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1029     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1030     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1031     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1032     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1033     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1034     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1035     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1036     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1037     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1038     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1039     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1040     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1041     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1042     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1043     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1044     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1045     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1046     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1047     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1048     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1049     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1050     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1051     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1052     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1053     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1054     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1055     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1056     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1057     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1058     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1059     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1060     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1061     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1062     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1063     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1064     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1065     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1066     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1067     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1068     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1069     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1070     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1071     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1072     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1073     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1074     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1075     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1076     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1077     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1078     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1079     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1080     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1081     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1082     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1083     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1084     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1085     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1086     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1087     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1088     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1089     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1090     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1091     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1092     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1093     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1094     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1095     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1096     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1097     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1098     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1099     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1100     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1101     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1102     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1103     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1104     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1105     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1106     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1107     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1108     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1109     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1110     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1111     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1112     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1113     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1114     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1115     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1116     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1117     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1118     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1119     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1120     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1121     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1122     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1123     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1124     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1125     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1126     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1127     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1128     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1129     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1130     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1131     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1132     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1133     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1134     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1135     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1136     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1137     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1138     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1139     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1140     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1141     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1142     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1143     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1144     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1145     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1146     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1147     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1148     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1149     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1150     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1151     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1152     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1153     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1154     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1155     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1156     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1157     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1158     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1159     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1160     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1161     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1162     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1163     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1164     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1165     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1166     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1167     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1168     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1169     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1170     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1171     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1172     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1173     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1174     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1175     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1176     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1177     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1178     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1179     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1180     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1181     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1182     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1183     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1184     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1185     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1186     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1187     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1188     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1189     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1190     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1191     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1192     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1193     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1194     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1195     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1196     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1197     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1198     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1199     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1200     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1201     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1202     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1203     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1204     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1205     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1206     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1207     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1208     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1209     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1210     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1211     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1212     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1213     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1214     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1215     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1216     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1217     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1218     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1219     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1220     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1221     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1222     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1223     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1224     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1225     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1226     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1227     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1228     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1229     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1230     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1231     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1232     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1233     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1234     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1235     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1236     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1237     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1238     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1239     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1240     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1241     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1242     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1243     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1244     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1245     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1246     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1247     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1248     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1249     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1250     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1251     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1252     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1253     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1254     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1255     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1256     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1257     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1258     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1259     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1260     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1261     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1262     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1263     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1264     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1265     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1266     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1267     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1268     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1269     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1270     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1271     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1272     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1273     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1274     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1275     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1276     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1277     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1278     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1279     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1280     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1281     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1282     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1283     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1284     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1285     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1286     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1287     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1288     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1289     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1290     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1291     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1292     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1293     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1294     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1295     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1296     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1297     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1298     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1299     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1300     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1301     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1302     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1303     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1304     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1305     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1306     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1307     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1308     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1309     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1310     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1311     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1312     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1313     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1314     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1315     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1316     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1317     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1318     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1319     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1320     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1321     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1322     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1323     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1324     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1325     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1326     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1327     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1328     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1329     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1330     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1331     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1332     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1333     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1334     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1335     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1336     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1337     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1338     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1339     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1340     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1341     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1342     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1343     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1344     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1345     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1346     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1347     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1348     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1349     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1350     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1351     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1352     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1353     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1354     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1355     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1356     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1357     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1358     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1359     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1360     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1361     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1362     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1363     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1364     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1365     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1366     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1367     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1368     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1369     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1370     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1371     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1372     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1373     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1374     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1375     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1376     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1377 };
1378 
1379 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1380 {
1381     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1382     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1383     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1384     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1385     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1386     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1387     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1388     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1389     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1390     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1391     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1392     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1393     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1394     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1395     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1396     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1397     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1398     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1399     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1400     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1401     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1402     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1403     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1404     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1405     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1406     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1407     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1408     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1409     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1410     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1411     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1412     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1413     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1414     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1415     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1416     SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1417     SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1418     SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1419 };
1420 
1421 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1422 {
1423     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1424     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1425     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1426     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1427     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1428     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1429     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1430     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1431     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1432     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1433     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1434     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1435     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1436     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1437     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1438     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1439     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1440     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1441     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1442     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1443     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1444     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1445     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1446     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1447     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1448     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1449     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1450     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1451     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1452     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1453     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1454     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1455     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1456     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1457     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1458     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1459     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1460     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1461     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1462     SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1463     SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1464     SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1465 };
1466 
1467 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1468 {
1469     /* Pending on emulation bring up */
1470 };
1471 
1472 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1473 {
1474     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1475     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1476     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1477     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1478     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1479     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1481     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1483     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1484     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1485     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1486     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1487     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1489     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1491     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1492     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1493     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1494     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1495     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1497     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1499     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1500     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1501     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1502     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1503     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1505     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1507     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1508     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1509     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1510     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1511     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1513     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1515     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1517     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1519     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1521     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1523     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1524     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1525     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1526     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1527     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1529     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1531     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1532     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1533     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1534     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1535     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1537     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1539     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1541     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1543     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1545     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1546     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1547     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1549     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1550     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1551     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1553     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1554     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1555     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1556     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1557     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1558     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1559     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1560     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1561     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1562     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1563     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1564     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1565     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1566     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1567     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1568     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1569     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1570     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1571     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1572     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1573     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1574     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1575     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1576     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1577     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1578     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1579     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1580     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1581     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1582     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1583     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1584     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1585     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1586     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1587     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1588     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1589     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1590     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1591     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1592     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1593     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1594     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1595     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1596     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1597     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1598     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1599     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1600     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1601     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1602     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1603     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1604     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1605     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1606     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1607     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1608     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1609     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1610     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1611     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1612     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1613     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1614     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1615     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1616     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1617     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1618     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1619     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1620     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1621     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1622     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1623     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1624     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1625     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1626     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1627     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1628     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1629     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1630     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1631     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1632     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1633     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1634     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1635     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1636     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1637     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1638     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1639     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1640     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1641     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1642     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1643     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1644     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1645     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1646     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1647     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1648     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1649     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1651     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1653     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1655     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1657     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1659     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1661     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1663     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1665     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1667     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1669     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1671     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1673     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1675     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1677     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1679     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1681     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1683     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1685     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1687     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1689     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1691     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1693     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1695     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1697     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1699     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1701     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1703     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1705     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1707     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1709     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1711     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1713     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1715     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1717     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1719     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1721     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1723     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1725     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1727     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1729     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1731     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1733     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1735     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1737     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1739     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1741     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1743     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1745     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1747     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1749     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1751     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1753     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1755     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1757     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1759     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1761     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1763     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1765     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1767     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1769     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1771     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1773     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1775     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1777     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1779     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1781     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1783     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1785     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1787     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1789     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1791     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1793     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1795     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1797     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1799     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1801     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1803     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1805     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1807     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1809     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1811     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1813     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1815     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1817     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1819     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1821     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1823     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1825     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1827     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1829     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1831     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1833     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1835     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1837     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1839     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1841     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1843     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1845     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1847     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1849     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1851     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1853     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1855     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1857     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1859     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1861     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1863     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1865     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1867     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1869     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1871     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1873     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1875     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1877     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1879     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1881     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1883     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1885     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1887     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1889     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1891     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1893     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1895     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1897     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1899     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1901     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1903     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1905     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1907     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1909     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1911     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1913     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1915     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1917     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1919     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1921     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1923     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1925     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1927     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1929     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1931     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1933     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1935     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1937     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1939     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1941     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1943     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1945     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1947     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1949     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1951     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1953     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1955     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1957     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1959     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1961     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1963     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1965     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1967     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1969     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1971     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1973     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1975     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1977     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1979     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1981     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1983     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1985     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1987     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1989     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1991     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1993     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1995     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1997     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1999     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2001     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2003     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2005     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2007     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2008     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2009     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2011     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2012     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2013     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2015     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2016     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2017     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2018     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2019     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2020     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2021     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2022     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2023     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2024     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2025     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2027     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2028     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2029     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2030     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2031     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2032     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2033     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2034     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2035     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2036     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2037     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2038     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2039     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2040     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2041     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2042     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2043     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2044     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2045     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2046     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2047     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2049     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2051     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2053     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2054     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2055     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2056     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2057     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2058     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2059     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2061     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2063     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2065     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2067     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2069     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2070     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2071     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2073     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2074     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2075     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2076     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2077     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2078     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2079     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2080     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2081     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2082     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2083     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2084     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2085     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2086     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2087     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2088     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2089     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2090     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2091     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2092     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2093     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2094 };
2095 
2096 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2097 {
2098     /* Pending on emulation bring up */
2099 };
2100 
2101 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2102 {
2103     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2104     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2106     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2108     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2109     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2110     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2112     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2113     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2114     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2115     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2116     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2118     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2120     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2122     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2124     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2126     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2128     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2130     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2132     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2134     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2136     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2138     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2140     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2142     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2144     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2146     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2148     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2150     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2152     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2154     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2156     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2158     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2160     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2161     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2162     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2163     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2164     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2166     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2168     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2170     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2172     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2174     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2176     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2178     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2180     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2182     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2184     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2186     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2188     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2190     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2192     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2194     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2196     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2198     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2200     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2202     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2204     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2206     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2208     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2210     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2212     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2214     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2216     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2218     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2220     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2222     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2224     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2226     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2228     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2230     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2232     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2234     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2236     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2238     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2240     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2242     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2244     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2246     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2248     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2250     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2252     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2254     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2256     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2258     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2259     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2260     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2262     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2263     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2264     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2265     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2266     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2267     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2268     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2269     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2270     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2271     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2272     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2273     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2274     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2275     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2276     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2278     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2279     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2280     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2281     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2282     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2284     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2285     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2286     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2287     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2288     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2289     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2290     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2292     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2294     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2295     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2296     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2297     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2298     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2300     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2302     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2303     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2304     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2305     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2306     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2308     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2310     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2311     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2312     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2313     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2314     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2316     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2318     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2319     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2320     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2321     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2322     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2324     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2326     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2327     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2328     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2329     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2330     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2331     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2332     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2333     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2334     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2335     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2336     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2337     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2338     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2339     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2340     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2341     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2342     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2343     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2344     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2345     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2346     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2347     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2348     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2349     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2350     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2351     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2352     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2353     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2354     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2355     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2356     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2357     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2358     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2359     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2360     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2361     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2362     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2363     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2364     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2365     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2366     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2367     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2368     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2369     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2370     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2371     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2372     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2373     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2374     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2375     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2376     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2377     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2378     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2379     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2380     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2381     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2382     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2383     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2384     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2385     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2386     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2387     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2388     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2389     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2390     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2391     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2392     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2393     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2394     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2395     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2396     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2397     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2398     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2399     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2400     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2401     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2402     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2403     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2404     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2405     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2406     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2407     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2408     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2409     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2410     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2411     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2412     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2413     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2414     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2415     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2416     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2417     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2418     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2419     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2420     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2421     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2422     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2423     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2424     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2425     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2426     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2427     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2428     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2429     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2430     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2431     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2432     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2433     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2434     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2435     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2436     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2437     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2438     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2439     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2440     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2441     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2442     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2443     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2444     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2445     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2446     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2447     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2448     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2449     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2450     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2451     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2452     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2453     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2454     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2455     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2456     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2457     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2458     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2459     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2460     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2461     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2462     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2463     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2464     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2465     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2466     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2467     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2468     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2469     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2470     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2471     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2472     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2473     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2474     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2475     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2476     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2477     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2478     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2479     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2480     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2481     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2482     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2483     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2484     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2485     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2486     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2487     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2488     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2489     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2490     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2491     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2492     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2493     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2494     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2495     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2496     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2497     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2498     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2499     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2500     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2501     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2502     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2503     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2504     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2505     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2506     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2507     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2508     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2509     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2510     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2511     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2512     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2513     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2514     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2515     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2516     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2517     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2518     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2519     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2520     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2521     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2522     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2523     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2524     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2525     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2526     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2527     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2528     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2529     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2530     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2531     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2532     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2533     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2534     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2535     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2536     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2537     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2538     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2539     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2540     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2541     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2542     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2543     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2544     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2545     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2546     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2547     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2548     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2549     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2550     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2551     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2552     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2553     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2554     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2555     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2556     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2557     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2558     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2559     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2560     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2561     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2562     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2563     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2564     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2565     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2566     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2567     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2568     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2569     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2570     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2571     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2572     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2573     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2574     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2575     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2576     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2577     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2578     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2579     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2580     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2581     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2582     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2583     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2584     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2585     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2586     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2587     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2588     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2589     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2590     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2591     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2592     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2593     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2594     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2595     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2596     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2597     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2598     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2599     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2600     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2601     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2602     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2603     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2604     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2605     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2606     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2607     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2608     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2609     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2610     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2611     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2612     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2613     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2614     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2615     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2616     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2617     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2618     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2619     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2620     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2621     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2622     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2623     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2624     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2625     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2626     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2627     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2628     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2629     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2630     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2631     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2632     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2633     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2634     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2635     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2636     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2637     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2638     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2639     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2640     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2641     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2642     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2643     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2644     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2645     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2646     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2647     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2648     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2649     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2650     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2651     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2652     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2653     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2654     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2655     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2656     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2657     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2658     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2659     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2660     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2661     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2662     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2663     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2664     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2665     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2666     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2667     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2668     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2669     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2670     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2671     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2672     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2673     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2674     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2675     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2676     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2677     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2678     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2679     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2680     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2681     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2682     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2683     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2684     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2685     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2686     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2687     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2688     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2689     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2690     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2691     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2692     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2693     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2694     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2695     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2696     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2697     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2698     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2699     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2700     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2701     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2702     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2703     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2704     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2705     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2706     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2707     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2708     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2709     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2710     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2711     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2712     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2713     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2714     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2715     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2716     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2717     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2718     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2719     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2720     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2721     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2722     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2723     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2724     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2725     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2726     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2727     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2728     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2729     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2730     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2731     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2732     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2733     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2734     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2735     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2736     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2737     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2738     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2739     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2740     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2741     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2742     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2743     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2744     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2745     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2746     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2747     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2748     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2749     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2750     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2751     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2752     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2753     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2754     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2755     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2756     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2757     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2758     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2759     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2760     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2761     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2762     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2763     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2764     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2765     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2766     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2767     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2768     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2769     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2770     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2771     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2772     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2773     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2774     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2775     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2776     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2777     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2778     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2779     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2780     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2781     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2782     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2783     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2784     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2785     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2786     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2787     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2788     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2789     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2790     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2791     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2792     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2793     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2794     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2795     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2796     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2797     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2798     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2799     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2800     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2801     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2802     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2803     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2804     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2805     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2806     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2807     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2808     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2809     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2810     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2811     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2812     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2813     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2814     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2815     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2816     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2817     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2818     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2819     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2820     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2821     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2822     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2823     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2824     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2825     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2826     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2827     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2828     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2829     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2830     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2831     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2832     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2833     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2834     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2835     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2836     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2837     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2838     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2839     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2840     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2841     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2842     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2843     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2844     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2845     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2846     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2847     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2848     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2849     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2850     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2851     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2852     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2853     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2854     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2855     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2856     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2857     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2858     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2859     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2860     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2861     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2862     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2863     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2864     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2865     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2866     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2867     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2868     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2869     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2870     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2871     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2872     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2873     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2874     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2875     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2876     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2877     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2878     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2879     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2880     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2881     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2882     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2883     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2884     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2885     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2886     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2887     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2888     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2889     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2890     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2891     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2892     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2893     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2894     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2895     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2896     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2897     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2898     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2899     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2900     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2901     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2902     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2903     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2904     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2905     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2906     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2907     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2908     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2909     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2910     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2911     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2912     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2913     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2914     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2915     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2916     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2917     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2918     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2919     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2920     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2921     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2922     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2923     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2924     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2925     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2926     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2927     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2928     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2929     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2930     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2931     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2932     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2933     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2934     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2935     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2936     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2937     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2938     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2939     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2940     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2941     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2942     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2943     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2944     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2945     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2946     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2947     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2948     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2949     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2950     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2951     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2952     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2953     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2954     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2955     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2956     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2957     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2958     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2959     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2960     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2961     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2962     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2963     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2964     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2965     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2966     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2967     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2968     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2969     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2970     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2971     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2972     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2973     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2974     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2975     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2976     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2977     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2978     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2979     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2980     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2981     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2982     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2983     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2984     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2985     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2986     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2987     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2988     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2989     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2990     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2991     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2992     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2993     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2994     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2995     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2996     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2997     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2998     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2999     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3000     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3001     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3002     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3003     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3004     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3005     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3006     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3007     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3008     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3009     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3010     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3011     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3012     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3013     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3014     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3015     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3016     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3017     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3018     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3019     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3020     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3021     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3022     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3023     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3024     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3025     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3026     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3027     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3028     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3029     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3030     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3031     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3032     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3033     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3034     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3035     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3036     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3037     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3038     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3039     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3040     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3041     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3042     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3043     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3044     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3045     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3046     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3047     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3048     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3049     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3050     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3051     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3052     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3053     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3054     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3055     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3056     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3057     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3058     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3059     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3060     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3061     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3062     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3063     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3064     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3065     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3066     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3067     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3068     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3069     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3070     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3071     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3072     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3073     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3074     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3075     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3076     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3077     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3078     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3079     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3080     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3081     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3082     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3083     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3084     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3085     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3086     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3087     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3088     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3089     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3090     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3091     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3092     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3093     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3094     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3095     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3096     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3097     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3098     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3099     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3100     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3101     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3102     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3103     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3104     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3105     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3106     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3107     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3108     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3109     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3110     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3111     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3112     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3113     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3114     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3115     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3116     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3117     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3118     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3119     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3120     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3121     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3122     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3123     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3124     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3125     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3126     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3127     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3128     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3129     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3130     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3131     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3132     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3133     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3134     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3135     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3136     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3137     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3138     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3139     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3140     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3141     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3142     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3143     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3144     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3145     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3146     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3147     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3148     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3149     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3150     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3151     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3152     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3153     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3154     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3155 };
3156 
3157 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3158 {
3159     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3160     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3161     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3162     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3163     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3164     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3165     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3166     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3167     SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3168     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3169     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3170     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3171     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3172     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3173     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3174     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3175     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3176     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3177     SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3178     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3179     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3180     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3181     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3182     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3183     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3184     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3185     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3186     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3187     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3188     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3189     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3190     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3191     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3192     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3193     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3194     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3195     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3196     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3197     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3198     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3199     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3200     SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3201     SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3202 };
3203 
3204 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3205 {
3206     /* Pending on emulation bring up */
3207 };
3208 
3209 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3210 {
3211     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3212     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3213     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3214     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3215     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3216     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3217     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3218     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3219     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3220     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3221     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3222     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3223     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3224     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3225     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3226     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3227     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3228     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3229     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3230     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3231     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3232     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3233     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3234     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3235     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3236     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3237     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3238     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3239     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3240     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3241     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3242     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3243     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3244     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3245     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3246     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3247     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3248     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3249     SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3250     SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3251     SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3252 
3253     /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3254     SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3255 };
3256 
3257 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3258 {
3259     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3260     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3261     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3262     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3263     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3264     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3265     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3266     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3267     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3268     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3269     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3270     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3271     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3272     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3273     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3274     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3275     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3276     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3277     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3278     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3279     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3280     SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3281     SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3282     SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3283 
3284     /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3285     SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3286 };
3287 
3288 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] =
3289 {
3290     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3291     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3292     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3293     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3294     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3295     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
3296     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3297     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3298     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3299     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3300     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3301     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3302     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3303     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3304     SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3305     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3306     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3307     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3308     SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3309     SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3310 };
3311 
3312 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
3313 {
3314     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3315     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3316     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3317     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3318     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3319     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3320     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3321     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3322     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3323     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3324     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3325     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3326     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3327     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3328     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3329     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3330     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3331     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3332     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3333     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3334     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3335     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3336     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3337     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3338     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3339     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3340     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3341     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3342     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3343     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3344     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3345     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3346     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3347     SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3348     SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3349     SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3350 };
3351 
3352 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3353     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3354     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
3355     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
3356     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3357     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3358     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3359     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3360     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3361     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3362     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3363     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3364     SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3365     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3366     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3367     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3368     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3369     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3370     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3371     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3372     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3373     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3374     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3375     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3376     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3377     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3378     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3379     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3380     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3381     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3382     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3383     SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX,0xfff7ffff, 0x01030000),
3384     SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3385 };
3386 
3387 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {
3388     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000),
3389     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e),
3390     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
3391     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100),
3392     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000),
3393     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014),
3394     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3395     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8),
3396     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003),
3397     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
3398     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
3399     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3400     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
3401     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210),
3402     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
3403     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500),
3404     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff),
3405     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3406     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8),
3407     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130),
3408     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130),
3409     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3410     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3411     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
3412     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f),
3413     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188),
3414     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009),
3415     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02),
3416     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000),
3417     SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101),
3418     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
3419     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
3420     SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),
3421     SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
3422 };
3423 
3424 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] =
3425 {
3426     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3427     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),
3428     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3429     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3430     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3431     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),
3432     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3433     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),
3434     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3435     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3436     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3437     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3438     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3439     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3440     SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3441     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3442     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3443     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3444     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3445     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3446     SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3447     SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3448 };
3449 
3450 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
3451     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3452     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3453     SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3454     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3455     SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3456     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),
3457     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3458     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3459     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3460     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3461     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3462     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3463     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3464     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3465     SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3466     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),
3467     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3468     SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3469     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3470     SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3471     SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3472     SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3473 };
3474 
3475 #define DEFAULT_SH_MEM_CONFIG \
3476     ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3477      (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3478      (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3479      (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3480 
3481 /* TODO: pending on golden setting value of gb address config */
3482 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044
3483 
3484 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3485 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3486 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3487 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3488 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev);
3489 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3490                  struct amdgpu_cu_info *cu_info);
3491 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3492 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3493                    u32 sh_num, u32 instance);
3494 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3495 
3496 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3497 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3498 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3499 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3500 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3501 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3502 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3503 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3504 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3505 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3506 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
3507                        uint16_t pasid, uint32_t flush_type,
3508                        bool all_hub, uint8_t dst_sel);
3509 
3510 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3511 {
3512     amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3513     amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3514               PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3515     amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3516     amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3517     amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3518     amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3519     amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3520     amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3521 }
3522 
3523 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3524                  struct amdgpu_ring *ring)
3525 {
3526     uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3527     uint64_t wptr_addr = ring->wptr_gpu_addr;
3528     uint32_t eng_sel = 0;
3529 
3530     switch (ring->funcs->type) {
3531     case AMDGPU_RING_TYPE_COMPUTE:
3532         eng_sel = 0;
3533         break;
3534     case AMDGPU_RING_TYPE_GFX:
3535         eng_sel = 4;
3536         break;
3537     case AMDGPU_RING_TYPE_MES:
3538         eng_sel = 5;
3539         break;
3540     default:
3541         WARN_ON(1);
3542     }
3543 
3544     amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3545     /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3546     amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3547               PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3548               PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3549               PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3550               PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3551               PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3552               PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3553               PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3554               PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3555               PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3556     amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3557     amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3558     amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3559     amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3560     amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3561 }
3562 
3563 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3564                    struct amdgpu_ring *ring,
3565                    enum amdgpu_unmap_queues_action action,
3566                    u64 gpu_addr, u64 seq)
3567 {
3568     struct amdgpu_device *adev = kiq_ring->adev;
3569     uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3570 
3571     if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) {
3572         amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);
3573         return;
3574     }
3575 
3576     amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3577     amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3578               PACKET3_UNMAP_QUEUES_ACTION(action) |
3579               PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3580               PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3581               PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3582     amdgpu_ring_write(kiq_ring,
3583           PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3584 
3585     if (action == PREEMPT_QUEUES_NO_UNMAP) {
3586         amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3587         amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3588         amdgpu_ring_write(kiq_ring, seq);
3589     } else {
3590         amdgpu_ring_write(kiq_ring, 0);
3591         amdgpu_ring_write(kiq_ring, 0);
3592         amdgpu_ring_write(kiq_ring, 0);
3593     }
3594 }
3595 
3596 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3597                    struct amdgpu_ring *ring,
3598                    u64 addr,
3599                    u64 seq)
3600 {
3601     uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3602 
3603     amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3604     amdgpu_ring_write(kiq_ring,
3605               PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3606               PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3607               PACKET3_QUERY_STATUS_COMMAND(2));
3608     amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3609               PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3610               PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3611     amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3612     amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3613     amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3614     amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3615 }
3616 
3617 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3618                 uint16_t pasid, uint32_t flush_type,
3619                 bool all_hub)
3620 {
3621     gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
3622 }
3623 
3624 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3625     .kiq_set_resources = gfx10_kiq_set_resources,
3626     .kiq_map_queues = gfx10_kiq_map_queues,
3627     .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3628     .kiq_query_status = gfx10_kiq_query_status,
3629     .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3630     .set_resources_size = 8,
3631     .map_queues_size = 7,
3632     .unmap_queues_size = 6,
3633     .query_status_size = 7,
3634     .invalidate_tlbs_size = 2,
3635 };
3636 
3637 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3638 {
3639     adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3640 }
3641 
3642 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3643 {
3644     switch (adev->ip_versions[GC_HWIP][0]) {
3645     case IP_VERSION(10, 1, 10):
3646         soc15_program_register_sequence(adev,
3647                         golden_settings_gc_rlc_spm_10_0_nv10,
3648                         (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3649         break;
3650     case IP_VERSION(10, 1, 1):
3651         soc15_program_register_sequence(adev,
3652                         golden_settings_gc_rlc_spm_10_1_nv14,
3653                         (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3654         break;
3655     case IP_VERSION(10, 1, 2):
3656         soc15_program_register_sequence(adev,
3657                         golden_settings_gc_rlc_spm_10_1_2_nv12,
3658                         (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3659         break;
3660     default:
3661         break;
3662     }
3663 }
3664 
3665 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3666 {
3667     switch (adev->ip_versions[GC_HWIP][0]) {
3668     case IP_VERSION(10, 1, 10):
3669         soc15_program_register_sequence(adev,
3670                         golden_settings_gc_10_1,
3671                         (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3672         soc15_program_register_sequence(adev,
3673                         golden_settings_gc_10_0_nv10,
3674                         (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3675         break;
3676     case IP_VERSION(10, 1, 1):
3677         soc15_program_register_sequence(adev,
3678                         golden_settings_gc_10_1_1,
3679                         (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3680         soc15_program_register_sequence(adev,
3681                         golden_settings_gc_10_1_nv14,
3682                         (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3683         break;
3684     case IP_VERSION(10, 1, 2):
3685         soc15_program_register_sequence(adev,
3686                         golden_settings_gc_10_1_2,
3687                         (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3688         soc15_program_register_sequence(adev,
3689                         golden_settings_gc_10_1_2_nv12,
3690                         (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3691         break;
3692     case IP_VERSION(10, 3, 0):
3693         soc15_program_register_sequence(adev,
3694                         golden_settings_gc_10_3,
3695                         (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3696         soc15_program_register_sequence(adev,
3697                         golden_settings_gc_10_3_sienna_cichlid,
3698                         (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3699         break;
3700     case IP_VERSION(10, 3, 2):
3701         soc15_program_register_sequence(adev,
3702                         golden_settings_gc_10_3_2,
3703                         (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3704         break;
3705     case IP_VERSION(10, 3, 1):
3706         soc15_program_register_sequence(adev,
3707                         golden_settings_gc_10_3_vangogh,
3708                         (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3709         break;
3710     case IP_VERSION(10, 3, 3):
3711         soc15_program_register_sequence(adev,
3712                         golden_settings_gc_10_3_3,
3713                         (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
3714         break;
3715     case IP_VERSION(10, 3, 4):
3716         soc15_program_register_sequence(adev,
3717                                                 golden_settings_gc_10_3_4,
3718                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3719         break;
3720     case IP_VERSION(10, 3, 5):
3721         soc15_program_register_sequence(adev,
3722                         golden_settings_gc_10_3_5,
3723                         (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
3724         break;
3725     case IP_VERSION(10, 1, 3):
3726     case IP_VERSION(10, 1, 4):
3727         soc15_program_register_sequence(adev,
3728                         golden_settings_gc_10_0_cyan_skillfish,
3729                         (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
3730         break;
3731     case IP_VERSION(10, 3, 6):
3732         soc15_program_register_sequence(adev,
3733                         golden_settings_gc_10_3_6,
3734                         (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));
3735         break;
3736     case IP_VERSION(10, 3, 7):
3737         soc15_program_register_sequence(adev,
3738                         golden_settings_gc_10_3_7,
3739                         (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));
3740         break;
3741     default:
3742         break;
3743     }
3744     gfx_v10_0_init_spm_golden_registers(adev);
3745 }
3746 
3747 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3748                        bool wc, uint32_t reg, uint32_t val)
3749 {
3750     amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3751     amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3752               WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3753     amdgpu_ring_write(ring, reg);
3754     amdgpu_ring_write(ring, 0);
3755     amdgpu_ring_write(ring, val);
3756 }
3757 
3758 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3759                   int mem_space, int opt, uint32_t addr0,
3760                   uint32_t addr1, uint32_t ref, uint32_t mask,
3761                   uint32_t inv)
3762 {
3763     amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3764     amdgpu_ring_write(ring,
3765               /* memory (1) or register (0) */
3766               (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3767                WAIT_REG_MEM_OPERATION(opt) | /* wait */
3768                WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3769                WAIT_REG_MEM_ENGINE(eng_sel)));
3770 
3771     if (mem_space)
3772         BUG_ON(addr0 & 0x3); /* Dword align */
3773     amdgpu_ring_write(ring, addr0);
3774     amdgpu_ring_write(ring, addr1);
3775     amdgpu_ring_write(ring, ref);
3776     amdgpu_ring_write(ring, mask);
3777     amdgpu_ring_write(ring, inv); /* poll interval */
3778 }
3779 
3780 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3781 {
3782     struct amdgpu_device *adev = ring->adev;
3783     uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3784     uint32_t tmp = 0;
3785     unsigned i;
3786     int r;
3787 
3788     WREG32(scratch, 0xCAFEDEAD);
3789     r = amdgpu_ring_alloc(ring, 3);
3790     if (r) {
3791         DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3792               ring->idx, r);
3793         return r;
3794     }
3795 
3796     amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3797     amdgpu_ring_write(ring, scratch -
3798               PACKET3_SET_UCONFIG_REG_START);
3799     amdgpu_ring_write(ring, 0xDEADBEEF);
3800     amdgpu_ring_commit(ring);
3801 
3802     for (i = 0; i < adev->usec_timeout; i++) {
3803         tmp = RREG32(scratch);
3804         if (tmp == 0xDEADBEEF)
3805             break;
3806         if (amdgpu_emu_mode == 1)
3807             msleep(1);
3808         else
3809             udelay(1);
3810     }
3811 
3812     if (i >= adev->usec_timeout)
3813         r = -ETIMEDOUT;
3814 
3815     return r;
3816 }
3817 
3818 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3819 {
3820     struct amdgpu_device *adev = ring->adev;
3821     struct amdgpu_ib ib;
3822     struct dma_fence *f = NULL;
3823     unsigned index;
3824     uint64_t gpu_addr;
3825     volatile uint32_t *cpu_ptr;
3826     long r;
3827 
3828     memset(&ib, 0, sizeof(ib));
3829 
3830     if (ring->is_mes_queue) {
3831         uint32_t padding, offset;
3832 
3833         offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
3834         padding = amdgpu_mes_ctx_get_offs(ring,
3835                           AMDGPU_MES_CTX_PADDING_OFFS);
3836 
3837         ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
3838         ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
3839 
3840         gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);
3841         cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);
3842         *cpu_ptr = cpu_to_le32(0xCAFEDEAD);
3843     } else {
3844         r = amdgpu_device_wb_get(adev, &index);
3845         if (r)
3846             return r;
3847 
3848         gpu_addr = adev->wb.gpu_addr + (index * 4);
3849         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3850         cpu_ptr = &adev->wb.wb[index];
3851 
3852         r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
3853         if (r) {
3854             DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
3855             goto err1;
3856         }
3857     }
3858 
3859     ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3860     ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3861     ib.ptr[2] = lower_32_bits(gpu_addr);
3862     ib.ptr[3] = upper_32_bits(gpu_addr);
3863     ib.ptr[4] = 0xDEADBEEF;
3864     ib.length_dw = 5;
3865 
3866     r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3867     if (r)
3868         goto err2;
3869 
3870     r = dma_fence_wait_timeout(f, false, timeout);
3871     if (r == 0) {
3872         r = -ETIMEDOUT;
3873         goto err2;
3874     } else if (r < 0) {
3875         goto err2;
3876     }
3877 
3878     if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
3879         r = 0;
3880     else
3881         r = -EINVAL;
3882 err2:
3883     if (!ring->is_mes_queue)
3884         amdgpu_ib_free(adev, &ib, NULL);
3885     dma_fence_put(f);
3886 err1:
3887     if (!ring->is_mes_queue)
3888         amdgpu_device_wb_free(adev, index);
3889     return r;
3890 }
3891 
3892 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3893 {
3894     release_firmware(adev->gfx.pfp_fw);
3895     adev->gfx.pfp_fw = NULL;
3896     release_firmware(adev->gfx.me_fw);
3897     adev->gfx.me_fw = NULL;
3898     release_firmware(adev->gfx.ce_fw);
3899     adev->gfx.ce_fw = NULL;
3900     release_firmware(adev->gfx.rlc_fw);
3901     adev->gfx.rlc_fw = NULL;
3902     release_firmware(adev->gfx.mec_fw);
3903     adev->gfx.mec_fw = NULL;
3904     release_firmware(adev->gfx.mec2_fw);
3905     adev->gfx.mec2_fw = NULL;
3906 
3907     kfree(adev->gfx.rlc.register_list_format);
3908 }
3909 
3910 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3911 {
3912     adev->gfx.cp_fw_write_wait = false;
3913 
3914     switch (adev->ip_versions[GC_HWIP][0]) {
3915     case IP_VERSION(10, 1, 10):
3916     case IP_VERSION(10, 1, 2):
3917     case IP_VERSION(10, 1, 1):
3918     case IP_VERSION(10, 1, 3):
3919     case IP_VERSION(10, 1, 4):
3920         if ((adev->gfx.me_fw_version >= 0x00000046) &&
3921             (adev->gfx.me_feature_version >= 27) &&
3922             (adev->gfx.pfp_fw_version >= 0x00000068) &&
3923             (adev->gfx.pfp_feature_version >= 27) &&
3924             (adev->gfx.mec_fw_version >= 0x0000005b) &&
3925             (adev->gfx.mec_feature_version >= 27))
3926             adev->gfx.cp_fw_write_wait = true;
3927         break;
3928     case IP_VERSION(10, 3, 0):
3929     case IP_VERSION(10, 3, 2):
3930     case IP_VERSION(10, 3, 1):
3931     case IP_VERSION(10, 3, 4):
3932     case IP_VERSION(10, 3, 5):
3933     case IP_VERSION(10, 3, 6):
3934     case IP_VERSION(10, 3, 3):
3935     case IP_VERSION(10, 3, 7):
3936         adev->gfx.cp_fw_write_wait = true;
3937         break;
3938     default:
3939         break;
3940     }
3941 
3942     if (!adev->gfx.cp_fw_write_wait)
3943         DRM_WARN_ONCE("CP firmware version too old, please update!");
3944 }
3945 
3946 
3947 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3948 {
3949     const struct rlc_firmware_header_v2_1 *rlc_hdr;
3950 
3951     rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3952     adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3953     adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3954     adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3955     adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3956     adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3957     adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3958     adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3959     adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3960     adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3961     adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3962     adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3963     adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3964     adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3965             le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3966 }
3967 
3968 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3969 {
3970     const struct rlc_firmware_header_v2_2 *rlc_hdr;
3971 
3972     rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3973     adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3974     adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3975     adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3976     adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3977 }
3978 
3979 static void gfx_v10_0_init_tap_delays_microcode(struct amdgpu_device *adev)
3980 {
3981     const struct rlc_firmware_header_v2_4 *rlc_hdr;
3982 
3983     rlc_hdr = (const struct rlc_firmware_header_v2_4 *)adev->gfx.rlc_fw->data;
3984     adev->gfx.rlc.global_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->global_tap_delays_ucode_size_bytes);
3985     adev->gfx.rlc.global_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->global_tap_delays_ucode_offset_bytes);
3986     adev->gfx.rlc.se0_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_size_bytes);
3987     adev->gfx.rlc.se0_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_offset_bytes);
3988     adev->gfx.rlc.se1_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_size_bytes);
3989     adev->gfx.rlc.se1_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_offset_bytes);
3990     adev->gfx.rlc.se2_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_size_bytes);
3991     adev->gfx.rlc.se2_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_offset_bytes);
3992     adev->gfx.rlc.se3_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_size_bytes);
3993     adev->gfx.rlc.se3_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_offset_bytes);
3994 }
3995 
3996 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3997 {
3998     bool ret = false;
3999 
4000     switch (adev->pdev->revision) {
4001     case 0xc2:
4002     case 0xc3:
4003         ret = true;
4004         break;
4005     default:
4006         ret = false;
4007         break;
4008     }
4009 
4010     return ret ;
4011 }
4012 
4013 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
4014 {
4015     switch (adev->ip_versions[GC_HWIP][0]) {
4016     case IP_VERSION(10, 1, 10):
4017         if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
4018             adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
4019         break;
4020     default:
4021         break;
4022     }
4023 }
4024 
4025 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
4026 {
4027     const char *chip_name;
4028     char fw_name[40];
4029     char *wks = "";
4030     int err;
4031     struct amdgpu_firmware_info *info = NULL;
4032     const struct common_firmware_header *header = NULL;
4033     const struct gfx_firmware_header_v1_0 *cp_hdr;
4034     const struct rlc_firmware_header_v2_0 *rlc_hdr;
4035     unsigned int *tmp = NULL;
4036     unsigned int i = 0;
4037     uint16_t version_major;
4038     uint16_t version_minor;
4039 
4040     DRM_DEBUG("\n");
4041 
4042     switch (adev->ip_versions[GC_HWIP][0]) {
4043     case IP_VERSION(10, 1, 10):
4044         chip_name = "navi10";
4045         break;
4046     case IP_VERSION(10, 1, 1):
4047         chip_name = "navi14";
4048         if (!(adev->pdev->device == 0x7340 &&
4049               adev->pdev->revision != 0x00))
4050             wks = "_wks";
4051         break;
4052     case IP_VERSION(10, 1, 2):
4053         chip_name = "navi12";
4054         break;
4055     case IP_VERSION(10, 3, 0):
4056         chip_name = "sienna_cichlid";
4057         break;
4058     case IP_VERSION(10, 3, 2):
4059         chip_name = "navy_flounder";
4060         break;
4061     case IP_VERSION(10, 3, 1):
4062         chip_name = "vangogh";
4063         break;
4064     case IP_VERSION(10, 3, 4):
4065         chip_name = "dimgrey_cavefish";
4066         break;
4067     case IP_VERSION(10, 3, 5):
4068         chip_name = "beige_goby";
4069         break;
4070     case IP_VERSION(10, 3, 3):
4071         chip_name = "yellow_carp";
4072         break;
4073     case IP_VERSION(10, 3, 6):
4074         chip_name = "gc_10_3_6";
4075         break;
4076     case IP_VERSION(10, 1, 3):
4077     case IP_VERSION(10, 1, 4):
4078         chip_name = "cyan_skillfish2";
4079         break;
4080     case IP_VERSION(10, 3, 7):
4081         chip_name = "gc_10_3_7";
4082         break;
4083     default:
4084         BUG();
4085     }
4086 
4087     snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
4088     err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
4089     if (err)
4090         goto out;
4091     err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
4092     if (err)
4093         goto out;
4094     cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
4095     adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4096     adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4097 
4098     snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
4099     err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
4100     if (err)
4101         goto out;
4102     err = amdgpu_ucode_validate(adev->gfx.me_fw);
4103     if (err)
4104         goto out;
4105     cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
4106     adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4107     adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4108 
4109     snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
4110     err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
4111     if (err)
4112         goto out;
4113     err = amdgpu_ucode_validate(adev->gfx.ce_fw);
4114     if (err)
4115         goto out;
4116     cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
4117     adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4118     adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4119 
4120     if (!amdgpu_sriov_vf(adev)) {
4121         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
4122         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4123         if (err)
4124             goto out;
4125         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
4126         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4127         version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4128         version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4129 
4130         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
4131         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
4132         adev->gfx.rlc.save_and_restore_offset =
4133             le32_to_cpu(rlc_hdr->save_and_restore_offset);
4134         adev->gfx.rlc.clear_state_descriptor_offset =
4135             le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
4136         adev->gfx.rlc.avail_scratch_ram_locations =
4137             le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
4138         adev->gfx.rlc.reg_restore_list_size =
4139             le32_to_cpu(rlc_hdr->reg_restore_list_size);
4140         adev->gfx.rlc.reg_list_format_start =
4141             le32_to_cpu(rlc_hdr->reg_list_format_start);
4142         adev->gfx.rlc.reg_list_format_separate_start =
4143             le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
4144         adev->gfx.rlc.starting_offsets_start =
4145             le32_to_cpu(rlc_hdr->starting_offsets_start);
4146         adev->gfx.rlc.reg_list_format_size_bytes =
4147             le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
4148         adev->gfx.rlc.reg_list_size_bytes =
4149             le32_to_cpu(rlc_hdr->reg_list_size_bytes);
4150         adev->gfx.rlc.register_list_format =
4151             kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
4152                     adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
4153         if (!adev->gfx.rlc.register_list_format) {
4154             err = -ENOMEM;
4155             goto out;
4156         }
4157 
4158         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4159                                le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
4160         for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
4161             adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
4162 
4163         adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
4164 
4165         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
4166                                le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
4167         for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
4168             adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
4169 
4170         if (version_major == 2) {
4171             if (version_minor >= 1)
4172                 gfx_v10_0_init_rlc_ext_microcode(adev);
4173             if (version_minor >= 2)
4174                 gfx_v10_0_init_rlc_iram_dram_microcode(adev);
4175             if (version_minor == 4) {
4176                 gfx_v10_0_init_tap_delays_microcode(adev);
4177             }
4178         }
4179     }
4180 
4181     snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
4182     err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
4183     if (err)
4184         goto out;
4185     err = amdgpu_ucode_validate(adev->gfx.mec_fw);
4186     if (err)
4187         goto out;
4188     cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4189     adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
4190     adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
4191 
4192     snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
4193     err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
4194     if (!err) {
4195         err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
4196         if (err)
4197             goto out;
4198         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
4199         adev->gfx.mec2_fw->data;
4200         adev->gfx.mec2_fw_version =
4201         le32_to_cpu(cp_hdr->header.ucode_version);
4202         adev->gfx.mec2_feature_version =
4203         le32_to_cpu(cp_hdr->ucode_feature_version);
4204     } else {
4205         err = 0;
4206         adev->gfx.mec2_fw = NULL;
4207     }
4208 
4209     if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4210         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
4211         info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
4212         info->fw = adev->gfx.pfp_fw;
4213         header = (const struct common_firmware_header *)info->fw->data;
4214         adev->firmware.fw_size +=
4215             ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4216 
4217         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
4218         info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
4219         info->fw = adev->gfx.me_fw;
4220         header = (const struct common_firmware_header *)info->fw->data;
4221         adev->firmware.fw_size +=
4222             ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4223 
4224         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
4225         info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
4226         info->fw = adev->gfx.ce_fw;
4227         header = (const struct common_firmware_header *)info->fw->data;
4228         adev->firmware.fw_size +=
4229             ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4230 
4231         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
4232         info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
4233         info->fw = adev->gfx.rlc_fw;
4234         if (info->fw) {
4235             header = (const struct common_firmware_header *)info->fw->data;
4236             adev->firmware.fw_size +=
4237                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
4238         }
4239         if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
4240             adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
4241             adev->gfx.rlc.save_restore_list_srm_size_bytes) {
4242             info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
4243             info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
4244             info->fw = adev->gfx.rlc_fw;
4245             adev->firmware.fw_size +=
4246                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
4247 
4248             info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
4249             info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
4250             info->fw = adev->gfx.rlc_fw;
4251             adev->firmware.fw_size +=
4252                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
4253 
4254             info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
4255             info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
4256             info->fw = adev->gfx.rlc_fw;
4257             adev->firmware.fw_size +=
4258                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
4259 
4260             if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
4261                 adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
4262                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
4263                 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
4264                 info->fw = adev->gfx.rlc_fw;
4265                 adev->firmware.fw_size +=
4266                     ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
4267 
4268                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
4269                 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
4270                 info->fw = adev->gfx.rlc_fw;
4271                 adev->firmware.fw_size +=
4272                     ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
4273             }
4274 
4275         }
4276 
4277         if (adev->gfx.rlc.global_tap_delays_ucode_size_bytes) {
4278             info = &adev->firmware.ucode[AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS];
4279             info->ucode_id = AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS;
4280             info->fw = adev->gfx.rlc_fw;
4281             adev->firmware.fw_size +=
4282                 ALIGN(adev->gfx.rlc.global_tap_delays_ucode_size_bytes, PAGE_SIZE);
4283         }
4284 
4285         if (adev->gfx.rlc.se0_tap_delays_ucode_size_bytes) {
4286             info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE0_TAP_DELAYS];
4287             info->ucode_id = AMDGPU_UCODE_ID_SE0_TAP_DELAYS;
4288             info->fw = adev->gfx.rlc_fw;
4289             adev->firmware.fw_size +=
4290                 ALIGN(adev->gfx.rlc.se0_tap_delays_ucode_size_bytes, PAGE_SIZE);
4291         }
4292 
4293         if (adev->gfx.rlc.se1_tap_delays_ucode_size_bytes) {
4294             info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE1_TAP_DELAYS];
4295             info->ucode_id = AMDGPU_UCODE_ID_SE1_TAP_DELAYS;
4296             info->fw = adev->gfx.rlc_fw;
4297             adev->firmware.fw_size +=
4298                 ALIGN(adev->gfx.rlc.se1_tap_delays_ucode_size_bytes, PAGE_SIZE);
4299         }
4300 
4301         if (adev->gfx.rlc.se2_tap_delays_ucode_size_bytes) {
4302             info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE2_TAP_DELAYS];
4303             info->ucode_id = AMDGPU_UCODE_ID_SE2_TAP_DELAYS;
4304             info->fw = adev->gfx.rlc_fw;
4305             adev->firmware.fw_size +=
4306                 ALIGN(adev->gfx.rlc.se2_tap_delays_ucode_size_bytes, PAGE_SIZE);
4307         }
4308 
4309         if (adev->gfx.rlc.se3_tap_delays_ucode_size_bytes) {
4310             info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE3_TAP_DELAYS];
4311             info->ucode_id = AMDGPU_UCODE_ID_SE3_TAP_DELAYS;
4312             info->fw = adev->gfx.rlc_fw;
4313             adev->firmware.fw_size +=
4314                 ALIGN(adev->gfx.rlc.se3_tap_delays_ucode_size_bytes, PAGE_SIZE);
4315         }
4316 
4317         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
4318         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
4319         info->fw = adev->gfx.mec_fw;
4320         header = (const struct common_firmware_header *)info->fw->data;
4321         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4322         adev->firmware.fw_size +=
4323             ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4324                   le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4325 
4326         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
4327         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
4328         info->fw = adev->gfx.mec_fw;
4329         adev->firmware.fw_size +=
4330             ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4331 
4332         if (adev->gfx.mec2_fw) {
4333             info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
4334             info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
4335             info->fw = adev->gfx.mec2_fw;
4336             header = (const struct common_firmware_header *)info->fw->data;
4337             cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4338             adev->firmware.fw_size +=
4339                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4340                       le32_to_cpu(cp_hdr->jt_size) * 4,
4341                       PAGE_SIZE);
4342             info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
4343             info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
4344             info->fw = adev->gfx.mec2_fw;
4345             adev->firmware.fw_size +=
4346                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
4347                       PAGE_SIZE);
4348         }
4349     }
4350 
4351     gfx_v10_0_check_fw_write_wait(adev);
4352 out:
4353     if (err) {
4354         dev_err(adev->dev,
4355             "gfx10: Failed to load firmware \"%s\"\n",
4356             fw_name);
4357         release_firmware(adev->gfx.pfp_fw);
4358         adev->gfx.pfp_fw = NULL;
4359         release_firmware(adev->gfx.me_fw);
4360         adev->gfx.me_fw = NULL;
4361         release_firmware(adev->gfx.ce_fw);
4362         adev->gfx.ce_fw = NULL;
4363         release_firmware(adev->gfx.rlc_fw);
4364         adev->gfx.rlc_fw = NULL;
4365         release_firmware(adev->gfx.mec_fw);
4366         adev->gfx.mec_fw = NULL;
4367         release_firmware(adev->gfx.mec2_fw);
4368         adev->gfx.mec2_fw = NULL;
4369     }
4370 
4371     gfx_v10_0_check_gfxoff_flag(adev);
4372 
4373     return err;
4374 }
4375 
4376 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4377 {
4378     u32 count = 0;
4379     const struct cs_section_def *sect = NULL;
4380     const struct cs_extent_def *ext = NULL;
4381 
4382     /* begin clear state */
4383     count += 2;
4384     /* context control state */
4385     count += 3;
4386 
4387     for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4388         for (ext = sect->section; ext->extent != NULL; ++ext) {
4389             if (sect->id == SECT_CONTEXT)
4390                 count += 2 + ext->reg_count;
4391             else
4392                 return 0;
4393         }
4394     }
4395 
4396     /* set PA_SC_TILE_STEERING_OVERRIDE */
4397     count += 3;
4398     /* end clear state */
4399     count += 2;
4400     /* clear state */
4401     count += 2;
4402 
4403     return count;
4404 }
4405 
4406 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4407                     volatile u32 *buffer)
4408 {
4409     u32 count = 0, i;
4410     const struct cs_section_def *sect = NULL;
4411     const struct cs_extent_def *ext = NULL;
4412     int ctx_reg_offset;
4413 
4414     if (adev->gfx.rlc.cs_data == NULL)
4415         return;
4416     if (buffer == NULL)
4417         return;
4418 
4419     buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4420     buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4421 
4422     buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4423     buffer[count++] = cpu_to_le32(0x80000000);
4424     buffer[count++] = cpu_to_le32(0x80000000);
4425 
4426     for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4427         for (ext = sect->section; ext->extent != NULL; ++ext) {
4428             if (sect->id == SECT_CONTEXT) {
4429                 buffer[count++] =
4430                     cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4431                 buffer[count++] = cpu_to_le32(ext->reg_index -
4432                         PACKET3_SET_CONTEXT_REG_START);
4433                 for (i = 0; i < ext->reg_count; i++)
4434                     buffer[count++] = cpu_to_le32(ext->extent[i]);
4435             } else {
4436                 return;
4437             }
4438         }
4439     }
4440 
4441     ctx_reg_offset =
4442         SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4443     buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4444     buffer[count++] = cpu_to_le32(ctx_reg_offset);
4445     buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4446 
4447     buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4448     buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4449 
4450     buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4451     buffer[count++] = cpu_to_le32(0);
4452 }
4453 
4454 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4455 {
4456     /* clear state block */
4457     amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4458             &adev->gfx.rlc.clear_state_gpu_addr,
4459             (void **)&adev->gfx.rlc.cs_ptr);
4460 
4461     /* jump table block */
4462     amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4463             &adev->gfx.rlc.cp_table_gpu_addr,
4464             (void **)&adev->gfx.rlc.cp_table_ptr);
4465 }
4466 
4467 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
4468 {
4469     struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
4470 
4471     reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl;
4472     reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
4473     reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
4474     reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
4475     reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
4476     reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
4477     reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
4478     switch (adev->ip_versions[GC_HWIP][0]) {
4479         case IP_VERSION(10, 3, 0):
4480             reg_access_ctrl->spare_int =
4481                 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);
4482             break;
4483         default:
4484             reg_access_ctrl->spare_int =
4485                 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
4486             break;
4487     }
4488     adev->gfx.rlc.rlcg_reg_access_supported = true;
4489 }
4490 
4491 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4492 {
4493     const struct cs_section_def *cs_data;
4494     int r;
4495 
4496     adev->gfx.rlc.cs_data = gfx10_cs_data;
4497 
4498     cs_data = adev->gfx.rlc.cs_data;
4499 
4500     if (cs_data) {
4501         /* init clear state block */
4502         r = amdgpu_gfx_rlc_init_csb(adev);
4503         if (r)
4504             return r;
4505     }
4506 
4507     /* init spm vmid with 0xf */
4508     if (adev->gfx.rlc.funcs->update_spm_vmid)
4509         adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4510 
4511 
4512     return 0;
4513 }
4514 
4515 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4516 {
4517     amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4518     amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4519 }
4520 
4521 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4522 {
4523     int r;
4524 
4525     bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4526 
4527     amdgpu_gfx_graphics_queue_acquire(adev);
4528 
4529     r = gfx_v10_0_init_microcode(adev);
4530     if (r)
4531         DRM_ERROR("Failed to load gfx firmware!\n");
4532 
4533     return r;
4534 }
4535 
4536 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4537 {
4538     int r;
4539     u32 *hpd;
4540     const __le32 *fw_data = NULL;
4541     unsigned fw_size;
4542     u32 *fw = NULL;
4543     size_t mec_hpd_size;
4544 
4545     const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4546 
4547     bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4548 
4549     /* take ownership of the relevant compute queues */
4550     amdgpu_gfx_compute_queue_acquire(adev);
4551     mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4552 
4553     if (mec_hpd_size) {
4554         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4555                           AMDGPU_GEM_DOMAIN_GTT,
4556                           &adev->gfx.mec.hpd_eop_obj,
4557                           &adev->gfx.mec.hpd_eop_gpu_addr,
4558                           (void **)&hpd);
4559         if (r) {
4560             dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4561             gfx_v10_0_mec_fini(adev);
4562             return r;
4563         }
4564 
4565         memset(hpd, 0, mec_hpd_size);
4566 
4567         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4568         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4569     }
4570 
4571     if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4572         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4573 
4574         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4575              le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4576         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4577 
4578         r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4579                           PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4580                           &adev->gfx.mec.mec_fw_obj,
4581                           &adev->gfx.mec.mec_fw_gpu_addr,
4582                           (void **)&fw);
4583         if (r) {
4584             dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4585             gfx_v10_0_mec_fini(adev);
4586             return r;
4587         }
4588 
4589         memcpy(fw, fw_data, fw_size);
4590 
4591         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4592         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4593     }
4594 
4595     return 0;
4596 }
4597 
4598 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4599 {
4600     WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4601         (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4602         (address << SQ_IND_INDEX__INDEX__SHIFT));
4603     return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4604 }
4605 
4606 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4607                uint32_t thread, uint32_t regno,
4608                uint32_t num, uint32_t *out)
4609 {
4610     WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4611         (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4612         (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4613         (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4614         (SQ_IND_INDEX__AUTO_INCR_MASK));
4615     while (num--)
4616         *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4617 }
4618 
4619 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4620 {
4621     /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4622      * field when performing a select_se_sh so it should be
4623      * zero here */
4624     WARN_ON(simd != 0);
4625 
4626     /* type 2 wave data */
4627     dst[(*no_fields)++] = 2;
4628     dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4629     dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4630     dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4631     dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4632     dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4633     dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4634     dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4635     dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4636     dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4637     dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4638     dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4639     dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4640     dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4641     dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4642     dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4643     dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
4644 }
4645 
4646 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4647                      uint32_t wave, uint32_t start,
4648                      uint32_t size, uint32_t *dst)
4649 {
4650     WARN_ON(simd != 0);
4651 
4652     wave_read_regs(
4653         adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4654         dst);
4655 }
4656 
4657 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4658                       uint32_t wave, uint32_t thread,
4659                       uint32_t start, uint32_t size,
4660                       uint32_t *dst)
4661 {
4662     wave_read_regs(
4663         adev, wave, thread,
4664         start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4665 }
4666 
4667 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4668                        u32 me, u32 pipe, u32 q, u32 vm)
4669 {
4670     nv_grbm_select(adev, me, pipe, q, vm);
4671 }
4672 
4673 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4674                       bool enable)
4675 {
4676     uint32_t data, def;
4677 
4678     data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4679 
4680     if (enable)
4681         data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4682     else
4683         data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4684 
4685     if (data != def)
4686         WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4687 }
4688 
4689 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4690     .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4691     .select_se_sh = &gfx_v10_0_select_se_sh,
4692     .read_wave_data = &gfx_v10_0_read_wave_data,
4693     .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4694     .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4695     .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4696     .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4697     .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4698 };
4699 
4700 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4701 {
4702     u32 gb_addr_config;
4703 
4704     adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4705 
4706     switch (adev->ip_versions[GC_HWIP][0]) {
4707     case IP_VERSION(10, 1, 10):
4708     case IP_VERSION(10, 1, 1):
4709     case IP_VERSION(10, 1, 2):
4710         adev->gfx.config.max_hw_contexts = 8;
4711         adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4712         adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4713         adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4714         adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4715         gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4716         break;
4717     case IP_VERSION(10, 3, 0):
4718     case IP_VERSION(10, 3, 2):
4719     case IP_VERSION(10, 3, 1):
4720     case IP_VERSION(10, 3, 4):
4721     case IP_VERSION(10, 3, 5):
4722     case IP_VERSION(10, 3, 6):
4723     case IP_VERSION(10, 3, 3):
4724     case IP_VERSION(10, 3, 7):
4725         adev->gfx.config.max_hw_contexts = 8;
4726         adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4727         adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4728         adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4729         adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4730         gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4731         adev->gfx.config.gb_addr_config_fields.num_pkrs =
4732             1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4733         break;
4734     case IP_VERSION(10, 1, 3):
4735     case IP_VERSION(10, 1, 4):
4736         adev->gfx.config.max_hw_contexts = 8;
4737         adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4738         adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4739         adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4740         adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4741         gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN;
4742         break;
4743     default:
4744         BUG();
4745         break;
4746     }
4747 
4748     adev->gfx.config.gb_addr_config = gb_addr_config;
4749 
4750     adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4751             REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4752                       GB_ADDR_CONFIG, NUM_PIPES);
4753 
4754     adev->gfx.config.max_tile_pipes =
4755         adev->gfx.config.gb_addr_config_fields.num_pipes;
4756 
4757     adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4758             REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4759                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4760     adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4761             REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4762                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4763     adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4764             REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4765                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4766     adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4767             REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4768                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4769 }
4770 
4771 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4772                    int me, int pipe, int queue)
4773 {
4774     struct amdgpu_ring *ring;
4775     unsigned int irq_type;
4776     unsigned int hw_prio;
4777 
4778     ring = &adev->gfx.gfx_ring[ring_id];
4779 
4780     ring->me = me;
4781     ring->pipe = pipe;
4782     ring->queue = queue;
4783 
4784     ring->ring_obj = NULL;
4785     ring->use_doorbell = true;
4786 
4787     if (!ring_id)
4788         ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4789     else
4790         ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4791     sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4792 
4793     irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4794     hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
4795             AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4796     return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4797                 hw_prio, NULL);
4798 }
4799 
4800 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4801                        int mec, int pipe, int queue)
4802 {
4803     unsigned irq_type;
4804     struct amdgpu_ring *ring;
4805     unsigned int hw_prio;
4806 
4807     ring = &adev->gfx.compute_ring[ring_id];
4808 
4809     /* mec0 is me1 */
4810     ring->me = mec + 1;
4811     ring->pipe = pipe;
4812     ring->queue = queue;
4813 
4814     ring->ring_obj = NULL;
4815     ring->use_doorbell = true;
4816     ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4817     ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4818                 + (ring_id * GFX10_MEC_HPD_SIZE);
4819     sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4820 
4821     irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4822         + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4823         + ring->pipe;
4824     hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4825             AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
4826     /* type-2 packets are deprecated on MEC, use type-3 instead */
4827     return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4828                  hw_prio, NULL);
4829 }
4830 
4831 static int gfx_v10_0_sw_init(void *handle)
4832 {
4833     int i, j, k, r, ring_id = 0;
4834     struct amdgpu_kiq *kiq;
4835     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4836 
4837     switch (adev->ip_versions[GC_HWIP][0]) {
4838     case IP_VERSION(10, 1, 10):
4839     case IP_VERSION(10, 1, 1):
4840     case IP_VERSION(10, 1, 2):
4841     case IP_VERSION(10, 1, 3):
4842     case IP_VERSION(10, 1, 4):
4843         adev->gfx.me.num_me = 1;
4844         adev->gfx.me.num_pipe_per_me = 1;
4845         adev->gfx.me.num_queue_per_pipe = 1;
4846         adev->gfx.mec.num_mec = 2;
4847         adev->gfx.mec.num_pipe_per_mec = 4;
4848         adev->gfx.mec.num_queue_per_pipe = 8;
4849         break;
4850     case IP_VERSION(10, 3, 0):
4851     case IP_VERSION(10, 3, 2):
4852     case IP_VERSION(10, 3, 1):
4853     case IP_VERSION(10, 3, 4):
4854     case IP_VERSION(10, 3, 5):
4855     case IP_VERSION(10, 3, 6):
4856     case IP_VERSION(10, 3, 3):
4857     case IP_VERSION(10, 3, 7):
4858         adev->gfx.me.num_me = 1;
4859         adev->gfx.me.num_pipe_per_me = 1;
4860         adev->gfx.me.num_queue_per_pipe = 1;
4861         adev->gfx.mec.num_mec = 2;
4862         adev->gfx.mec.num_pipe_per_mec = 4;
4863         adev->gfx.mec.num_queue_per_pipe = 4;
4864         break;
4865     default:
4866         adev->gfx.me.num_me = 1;
4867         adev->gfx.me.num_pipe_per_me = 1;
4868         adev->gfx.me.num_queue_per_pipe = 1;
4869         adev->gfx.mec.num_mec = 1;
4870         adev->gfx.mec.num_pipe_per_mec = 4;
4871         adev->gfx.mec.num_queue_per_pipe = 8;
4872         break;
4873     }
4874 
4875     /* KIQ event */
4876     r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4877                   GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4878                   &adev->gfx.kiq.irq);
4879     if (r)
4880         return r;
4881 
4882     /* EOP Event */
4883     r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4884                   GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4885                   &adev->gfx.eop_irq);
4886     if (r)
4887         return r;
4888 
4889     /* Privileged reg */
4890     r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4891                   &adev->gfx.priv_reg_irq);
4892     if (r)
4893         return r;
4894 
4895     /* Privileged inst */
4896     r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4897                   &adev->gfx.priv_inst_irq);
4898     if (r)
4899         return r;
4900 
4901     adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4902 
4903     r = gfx_v10_0_me_init(adev);
4904     if (r)
4905         return r;
4906 
4907     if (adev->gfx.rlc.funcs) {
4908         if (adev->gfx.rlc.funcs->init) {
4909             r = adev->gfx.rlc.funcs->init(adev);
4910             if (r) {
4911                 dev_err(adev->dev, "Failed to init rlc BOs!\n");
4912                 return r;
4913             }
4914         }
4915     }
4916 
4917     r = gfx_v10_0_mec_init(adev);
4918     if (r) {
4919         DRM_ERROR("Failed to init MEC BOs!\n");
4920         return r;
4921     }
4922 
4923     /* set up the gfx ring */
4924     for (i = 0; i < adev->gfx.me.num_me; i++) {
4925         for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4926             for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4927                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4928                     continue;
4929 
4930                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4931                                 i, k, j);
4932                 if (r)
4933                     return r;
4934                 ring_id++;
4935             }
4936         }
4937     }
4938 
4939     ring_id = 0;
4940     /* set up the compute queues - allocate horizontally across pipes */
4941     for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4942         for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4943             for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4944                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4945                                      j))
4946                     continue;
4947 
4948                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4949                                 i, k, j);
4950                 if (r)
4951                     return r;
4952 
4953                 ring_id++;
4954             }
4955         }
4956     }
4957 
4958     if (!adev->enable_mes_kiq) {
4959         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4960         if (r) {
4961             DRM_ERROR("Failed to init KIQ BOs!\n");
4962             return r;
4963         }
4964 
4965         kiq = &adev->gfx.kiq;
4966         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4967         if (r)
4968             return r;
4969     }
4970 
4971     r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4972     if (r)
4973         return r;
4974 
4975     /* allocate visible FB for rlc auto-loading fw */
4976     if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4977         r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4978         if (r)
4979             return r;
4980     }
4981 
4982     adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4983 
4984     gfx_v10_0_gpu_early_init(adev);
4985 
4986     return 0;
4987 }
4988 
4989 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4990 {
4991     amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4992                   &adev->gfx.pfp.pfp_fw_gpu_addr,
4993                   (void **)&adev->gfx.pfp.pfp_fw_ptr);
4994 }
4995 
4996 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4997 {
4998     amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4999                   &adev->gfx.ce.ce_fw_gpu_addr,
5000                   (void **)&adev->gfx.ce.ce_fw_ptr);
5001 }
5002 
5003 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
5004 {
5005     amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
5006                   &adev->gfx.me.me_fw_gpu_addr,
5007                   (void **)&adev->gfx.me.me_fw_ptr);
5008 }
5009 
5010 static int gfx_v10_0_sw_fini(void *handle)
5011 {
5012     int i;
5013     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5014 
5015     for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5016         amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
5017     for (i = 0; i < adev->gfx.num_compute_rings; i++)
5018         amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
5019 
5020     amdgpu_gfx_mqd_sw_fini(adev);
5021 
5022     if (!adev->enable_mes_kiq) {
5023         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
5024         amdgpu_gfx_kiq_fini(adev);
5025     }
5026 
5027     gfx_v10_0_pfp_fini(adev);
5028     gfx_v10_0_ce_fini(adev);
5029     gfx_v10_0_me_fini(adev);
5030     gfx_v10_0_rlc_fini(adev);
5031     gfx_v10_0_mec_fini(adev);
5032 
5033     if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
5034         gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
5035 
5036     gfx_v10_0_free_microcode(adev);
5037 
5038     return 0;
5039 }
5040 
5041 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
5042                    u32 sh_num, u32 instance)
5043 {
5044     u32 data;
5045 
5046     if (instance == 0xffffffff)
5047         data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
5048                      INSTANCE_BROADCAST_WRITES, 1);
5049     else
5050         data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
5051                      instance);
5052 
5053     if (se_num == 0xffffffff)
5054         data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
5055                      1);
5056     else
5057         data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
5058 
5059     if (sh_num == 0xffffffff)
5060         data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
5061                      1);
5062     else
5063         data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
5064 
5065     WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
5066 }
5067 
5068 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
5069 {
5070     u32 data, mask;
5071 
5072     data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
5073     data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
5074 
5075     data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
5076     data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
5077 
5078     mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
5079                      adev->gfx.config.max_sh_per_se);
5080 
5081     return (~data) & mask;
5082 }
5083 
5084 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
5085 {
5086     int i, j;
5087     u32 data;
5088     u32 active_rbs = 0;
5089     u32 bitmap;
5090     u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
5091                     adev->gfx.config.max_sh_per_se;
5092 
5093     mutex_lock(&adev->grbm_idx_mutex);
5094     for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5095         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5096             bitmap = i * adev->gfx.config.max_sh_per_se + j;
5097             if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
5098                 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
5099                 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6))) &&
5100                 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
5101                 continue;
5102             gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5103             data = gfx_v10_0_get_rb_active_bitmap(adev);
5104             active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
5105                            rb_bitmap_width_per_sh);
5106         }
5107     }
5108     gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5109     mutex_unlock(&adev->grbm_idx_mutex);
5110 
5111     adev->gfx.config.backend_enable_mask = active_rbs;
5112     adev->gfx.config.num_rbs = hweight32(active_rbs);
5113 }
5114 
5115 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
5116 {
5117     uint32_t num_sc;
5118     uint32_t enabled_rb_per_sh;
5119     uint32_t active_rb_bitmap;
5120     uint32_t num_rb_per_sc;
5121     uint32_t num_packer_per_sc;
5122     uint32_t pa_sc_tile_steering_override;
5123 
5124     /* for ASICs that integrates GFX v10.3
5125      * pa_sc_tile_steering_override should be set to 0 */
5126     if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
5127         return 0;
5128 
5129     /* init num_sc */
5130     num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
5131             adev->gfx.config.num_sc_per_sh;
5132     /* init num_rb_per_sc */
5133     active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
5134     enabled_rb_per_sh = hweight32(active_rb_bitmap);
5135     num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
5136     /* init num_packer_per_sc */
5137     num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
5138 
5139     pa_sc_tile_steering_override = 0;
5140     pa_sc_tile_steering_override |=
5141         (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
5142         PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
5143     pa_sc_tile_steering_override |=
5144         (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
5145         PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
5146     pa_sc_tile_steering_override |=
5147         (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
5148         PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
5149 
5150     return pa_sc_tile_steering_override;
5151 }
5152 
5153 #define DEFAULT_SH_MEM_BASES    (0x6000)
5154 
5155 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
5156 {
5157     int i;
5158     uint32_t sh_mem_bases;
5159 
5160     /*
5161      * Configure apertures:
5162      * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
5163      * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
5164      * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
5165      */
5166     sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
5167 
5168     mutex_lock(&adev->srbm_mutex);
5169     for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5170         nv_grbm_select(adev, 0, 0, 0, i);
5171         /* CP and shaders */
5172         WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5173         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
5174     }
5175     nv_grbm_select(adev, 0, 0, 0, 0);
5176     mutex_unlock(&adev->srbm_mutex);
5177 
5178     /* Initialize all compute VMIDs to have no GDS, GWS, or OA
5179        access. These should be enabled by FW for target VMIDs. */
5180     for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
5181         WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
5182         WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
5183         WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
5184         WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
5185     }
5186 }
5187 
5188 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
5189 {
5190     int vmid;
5191 
5192     /*
5193      * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
5194      * access. Compute VMIDs should be enabled by FW for target VMIDs,
5195      * the driver can enable them for graphics. VMID0 should maintain
5196      * access so that HWS firmware can save/restore entries.
5197      */
5198     for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
5199         WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
5200         WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
5201         WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
5202         WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
5203     }
5204 }
5205 
5206 
5207 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
5208 {
5209     int i, j, k;
5210     int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
5211     u32 tmp, wgp_active_bitmap = 0;
5212     u32 gcrd_targets_disable_tcp = 0;
5213     u32 utcl_invreq_disable = 0;
5214     /*
5215      * GCRD_TARGETS_DISABLE field contains
5216      * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
5217      * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
5218      */
5219     u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
5220         2 * max_wgp_per_sh + /* TCP */
5221         max_wgp_per_sh + /* SQC */
5222         4); /* GL1C */
5223     /*
5224      * UTCL1_UTCL0_INVREQ_DISABLE field contains
5225      * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
5226      * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
5227      */
5228     u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
5229         2 * max_wgp_per_sh + /* TCP */
5230         2 * max_wgp_per_sh + /* SQC */
5231         4 + /* RMI */
5232         1); /* SQG */
5233 
5234     mutex_lock(&adev->grbm_idx_mutex);
5235     for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5236         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5237             gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
5238             wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
5239             /*
5240              * Set corresponding TCP bits for the inactive WGPs in
5241              * GCRD_SA_TARGETS_DISABLE
5242              */
5243             gcrd_targets_disable_tcp = 0;
5244             /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
5245             utcl_invreq_disable = 0;
5246 
5247             for (k = 0; k < max_wgp_per_sh; k++) {
5248                 if (!(wgp_active_bitmap & (1 << k))) {
5249                     gcrd_targets_disable_tcp |= 3 << (2 * k);
5250                     gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
5251                     utcl_invreq_disable |= (3 << (2 * k)) |
5252                         (3 << (2 * (max_wgp_per_sh + k)));
5253                 }
5254             }
5255 
5256             tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5257             /* only override TCP & SQC bits */
5258             tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
5259             tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5260             WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5261 
5262             tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5263             /* only override TCP & SQC bits */
5264             tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
5265             tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5266             WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5267         }
5268     }
5269 
5270     gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5271     mutex_unlock(&adev->grbm_idx_mutex);
5272 }
5273 
5274 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5275 {
5276     /* TCCs are global (not instanced). */
5277     uint32_t tcc_disable;
5278 
5279     if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
5280         tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
5281                   RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
5282     } else {
5283         tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
5284                   RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
5285     }
5286 
5287     adev->gfx.config.tcc_disabled_mask =
5288         REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
5289         (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
5290 }
5291 
5292 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5293 {
5294     u32 tmp;
5295     int i;
5296 
5297     WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
5298 
5299     gfx_v10_0_setup_rb(adev);
5300     gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5301     gfx_v10_0_get_tcc_info(adev);
5302     adev->gfx.config.pa_sc_tile_steering_override =
5303         gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5304 
5305     /* XXX SH_MEM regs */
5306     /* where to put LDS, scratch, GPUVM in FSA64 space */
5307     mutex_lock(&adev->srbm_mutex);
5308     for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
5309         nv_grbm_select(adev, 0, 0, 0, i);
5310         /* CP and shaders */
5311         WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5312         if (i != 0) {
5313             tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5314                 (adev->gmc.private_aperture_start >> 48));
5315             tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5316                 (adev->gmc.shared_aperture_start >> 48));
5317             WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5318         }
5319     }
5320     nv_grbm_select(adev, 0, 0, 0, 0);
5321 
5322     mutex_unlock(&adev->srbm_mutex);
5323 
5324     gfx_v10_0_init_compute_vmid(adev);
5325     gfx_v10_0_init_gds_vmid(adev);
5326 
5327 }
5328 
5329 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5330                            bool enable)
5331 {
5332     u32 tmp;
5333 
5334     if (amdgpu_sriov_vf(adev))
5335         return;
5336 
5337     tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5338 
5339     tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5340                 enable ? 1 : 0);
5341     tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5342                 enable ? 1 : 0);
5343     tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5344                 enable ? 1 : 0);
5345     tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5346                 enable ? 1 : 0);
5347 
5348     WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5349 }
5350 
5351 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5352 {
5353     adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5354 
5355     /* csib */
5356     if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
5357         WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5358                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5359         WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5360                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5361         WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5362     } else {
5363         WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5364                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5365         WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5366                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5367         WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5368     }
5369     return 0;
5370 }
5371 
5372 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5373 {
5374     u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5375 
5376     tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5377     WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5378 }
5379 
5380 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5381 {
5382     WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5383     udelay(50);
5384     WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5385     udelay(50);
5386 }
5387 
5388 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5389                          bool enable)
5390 {
5391     uint32_t rlc_pg_cntl;
5392 
5393     rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5394 
5395     if (!enable) {
5396         /* RLC_PG_CNTL[23] = 0 (default)
5397          * RLC will wait for handshake acks with SMU
5398          * GFXOFF will be enabled
5399          * RLC_PG_CNTL[23] = 1
5400          * RLC will not issue any message to SMU
5401          * hence no handshake between SMU & RLC
5402          * GFXOFF will be disabled
5403          */
5404         rlc_pg_cntl |= 0x800000;
5405     } else
5406         rlc_pg_cntl &= ~0x800000;
5407     WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5408 }
5409 
5410 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5411 {
5412     /* TODO: enable rlc & smu handshake until smu
5413      * and gfxoff feature works as expected */
5414     if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5415         gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5416 
5417     WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5418     udelay(50);
5419 }
5420 
5421 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5422 {
5423     uint32_t tmp;
5424 
5425     /* enable Save Restore Machine */
5426     tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5427     tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5428     tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5429     WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5430 }
5431 
5432 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5433 {
5434     const struct rlc_firmware_header_v2_0 *hdr;
5435     const __le32 *fw_data;
5436     unsigned i, fw_size;
5437 
5438     if (!adev->gfx.rlc_fw)
5439         return -EINVAL;
5440 
5441     hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5442     amdgpu_ucode_print_rlc_hdr(&hdr->header);
5443 
5444     fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5445                le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5446     fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5447 
5448     WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5449              RLCG_UCODE_LOADING_START_ADDRESS);
5450 
5451     for (i = 0; i < fw_size; i++)
5452         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5453                  le32_to_cpup(fw_data++));
5454 
5455     WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5456 
5457     return 0;
5458 }
5459 
5460 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5461 {
5462     int r;
5463 
5464     if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
5465         adev->psp.autoload_supported) {
5466 
5467         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5468         if (r)
5469             return r;
5470 
5471         gfx_v10_0_init_csb(adev);
5472 
5473         if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5474             gfx_v10_0_rlc_enable_srm(adev);
5475     } else {
5476         if (amdgpu_sriov_vf(adev)) {
5477             gfx_v10_0_init_csb(adev);
5478             return 0;
5479         }
5480 
5481         adev->gfx.rlc.funcs->stop(adev);
5482 
5483         /* disable CG */
5484         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5485 
5486         /* disable PG */
5487         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5488 
5489         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5490             /* legacy rlc firmware loading */
5491             r = gfx_v10_0_rlc_load_microcode(adev);
5492             if (r)
5493                 return r;
5494         } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5495             /* rlc backdoor autoload firmware */
5496             r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5497             if (r)
5498                 return r;
5499         }
5500 
5501         gfx_v10_0_init_csb(adev);
5502 
5503         adev->gfx.rlc.funcs->start(adev);
5504 
5505         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5506             r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5507             if (r)
5508                 return r;
5509         }
5510     }
5511     return 0;
5512 }
5513 
5514 static struct {
5515     FIRMWARE_ID id;
5516     unsigned int    offset;
5517     unsigned int    size;
5518 } rlc_autoload_info[FIRMWARE_ID_MAX];
5519 
5520 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5521 {
5522     int ret;
5523     RLC_TABLE_OF_CONTENT *rlc_toc;
5524 
5525     ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE,
5526                     AMDGPU_GEM_DOMAIN_GTT,
5527                     &adev->gfx.rlc.rlc_toc_bo,
5528                     &adev->gfx.rlc.rlc_toc_gpu_addr,
5529                     (void **)&adev->gfx.rlc.rlc_toc_buf);
5530     if (ret) {
5531         dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5532         return ret;
5533     }
5534 
5535     /* Copy toc from psp sos fw to rlc toc buffer */
5536     memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);
5537 
5538     rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5539     while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5540         (rlc_toc->id < FIRMWARE_ID_MAX)) {
5541         if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5542             (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5543             /* Offset needs 4KB alignment */
5544             rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5545         }
5546 
5547         rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5548         rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5549         rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5550 
5551         rlc_toc++;
5552     }
5553 
5554     return 0;
5555 }
5556 
5557 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5558 {
5559     uint32_t total_size = 0;
5560     FIRMWARE_ID id;
5561     int ret;
5562 
5563     ret = gfx_v10_0_parse_rlc_toc(adev);
5564     if (ret) {
5565         dev_err(adev->dev, "failed to parse rlc toc\n");
5566         return 0;
5567     }
5568 
5569     for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5570         total_size += rlc_autoload_info[id].size;
5571 
5572     /* In case the offset in rlc toc ucode is aligned */
5573     if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5574         total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5575                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5576 
5577     return total_size;
5578 }
5579 
5580 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5581 {
5582     int r;
5583     uint32_t total_size;
5584 
5585     total_size = gfx_v10_0_calc_toc_total_size(adev);
5586 
5587     r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5588                       AMDGPU_GEM_DOMAIN_GTT,
5589                       &adev->gfx.rlc.rlc_autoload_bo,
5590                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5591                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5592     if (r) {
5593         dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5594         return r;
5595     }
5596 
5597     return 0;
5598 }
5599 
5600 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5601 {
5602     amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5603                   &adev->gfx.rlc.rlc_toc_gpu_addr,
5604                   (void **)&adev->gfx.rlc.rlc_toc_buf);
5605     amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5606                   &adev->gfx.rlc.rlc_autoload_gpu_addr,
5607                   (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5608 }
5609 
5610 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5611                                FIRMWARE_ID id,
5612                                const void *fw_data,
5613                                uint32_t fw_size)
5614 {
5615     uint32_t toc_offset;
5616     uint32_t toc_fw_size;
5617     char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5618 
5619     if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5620         return;
5621 
5622     toc_offset = rlc_autoload_info[id].offset;
5623     toc_fw_size = rlc_autoload_info[id].size;
5624 
5625     if (fw_size == 0)
5626         fw_size = toc_fw_size;
5627 
5628     if (fw_size > toc_fw_size)
5629         fw_size = toc_fw_size;
5630 
5631     memcpy(ptr + toc_offset, fw_data, fw_size);
5632 
5633     if (fw_size < toc_fw_size)
5634         memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5635 }
5636 
5637 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5638 {
5639     void *data;
5640     uint32_t size;
5641 
5642     data = adev->gfx.rlc.rlc_toc_buf;
5643     size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5644 
5645     gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5646                            FIRMWARE_ID_RLC_TOC,
5647                            data, size);
5648 }
5649 
5650 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5651 {
5652     const __le32 *fw_data;
5653     uint32_t fw_size;
5654     const struct gfx_firmware_header_v1_0 *cp_hdr;
5655     const struct rlc_firmware_header_v2_0 *rlc_hdr;
5656 
5657     /* pfp ucode */
5658     cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5659         adev->gfx.pfp_fw->data;
5660     fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5661         le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5662     fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5663     gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5664                            FIRMWARE_ID_CP_PFP,
5665                            fw_data, fw_size);
5666 
5667     /* ce ucode */
5668     cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5669         adev->gfx.ce_fw->data;
5670     fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5671         le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5672     fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5673     gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5674                            FIRMWARE_ID_CP_CE,
5675                            fw_data, fw_size);
5676 
5677     /* me ucode */
5678     cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5679         adev->gfx.me_fw->data;
5680     fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5681         le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5682     fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5683     gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5684                            FIRMWARE_ID_CP_ME,
5685                            fw_data, fw_size);
5686 
5687     /* rlc ucode */
5688     rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5689         adev->gfx.rlc_fw->data;
5690     fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5691         le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5692     fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5693     gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5694                            FIRMWARE_ID_RLC_G_UCODE,
5695                            fw_data, fw_size);
5696 
5697     /* mec1 ucode */
5698     cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5699         adev->gfx.mec_fw->data;
5700     fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5701         le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5702     fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5703         cp_hdr->jt_size * 4;
5704     gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5705                            FIRMWARE_ID_CP_MEC,
5706                            fw_data, fw_size);
5707     /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5708 }
5709 
5710 /* Temporarily put sdma part here */
5711 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5712 {
5713     const __le32 *fw_data;
5714     uint32_t fw_size;
5715     const struct sdma_firmware_header_v1_0 *sdma_hdr;
5716     int i;
5717 
5718     for (i = 0; i < adev->sdma.num_instances; i++) {
5719         sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5720             adev->sdma.instance[i].fw->data;
5721         fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5722             le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5723         fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5724 
5725         if (i == 0) {
5726             gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5727                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5728             gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5729                 FIRMWARE_ID_SDMA0_JT,
5730                 (uint32_t *)fw_data +
5731                 sdma_hdr->jt_offset,
5732                 sdma_hdr->jt_size * 4);
5733         } else if (i == 1) {
5734             gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5735                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5736             gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5737                 FIRMWARE_ID_SDMA1_JT,
5738                 (uint32_t *)fw_data +
5739                 sdma_hdr->jt_offset,
5740                 sdma_hdr->jt_size * 4);
5741         }
5742     }
5743 }
5744 
5745 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5746 {
5747     uint32_t rlc_g_offset, rlc_g_size, tmp;
5748     uint64_t gpu_addr;
5749 
5750     gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5751     gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5752     gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5753 
5754     rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5755     rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5756     gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5757 
5758     WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5759     WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5760     WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5761 
5762     tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5763     if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5764            RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5765         DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5766         return -EINVAL;
5767     }
5768 
5769     tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5770     if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5771         DRM_ERROR("RLC ROM should halt itself\n");
5772         return -EINVAL;
5773     }
5774 
5775     return 0;
5776 }
5777 
5778 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5779 {
5780     uint32_t usec_timeout = 50000;  /* wait for 50ms */
5781     uint32_t tmp;
5782     int i;
5783     uint64_t addr;
5784 
5785     /* Trigger an invalidation of the L1 instruction caches */
5786     tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5787     tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5788     WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5789 
5790     /* Wait for invalidation complete */
5791     for (i = 0; i < usec_timeout; i++) {
5792         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5793         if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5794             INVALIDATE_CACHE_COMPLETE))
5795             break;
5796         udelay(1);
5797     }
5798 
5799     if (i >= usec_timeout) {
5800         dev_err(adev->dev, "failed to invalidate instruction cache\n");
5801         return -EINVAL;
5802     }
5803 
5804     /* Program me ucode address into intruction cache address register */
5805     addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5806         rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5807     WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5808             lower_32_bits(addr) & 0xFFFFF000);
5809     WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5810             upper_32_bits(addr));
5811 
5812     return 0;
5813 }
5814 
5815 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5816 {
5817     uint32_t usec_timeout = 50000;  /* wait for 50ms */
5818     uint32_t tmp;
5819     int i;
5820     uint64_t addr;
5821 
5822     /* Trigger an invalidation of the L1 instruction caches */
5823     tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5824     tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5825     WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5826 
5827     /* Wait for invalidation complete */
5828     for (i = 0; i < usec_timeout; i++) {
5829         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5830         if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5831             INVALIDATE_CACHE_COMPLETE))
5832             break;
5833         udelay(1);
5834     }
5835 
5836     if (i >= usec_timeout) {
5837         dev_err(adev->dev, "failed to invalidate instruction cache\n");
5838         return -EINVAL;
5839     }
5840 
5841     /* Program ce ucode address into intruction cache address register */
5842     addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5843         rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5844     WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5845             lower_32_bits(addr) & 0xFFFFF000);
5846     WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5847             upper_32_bits(addr));
5848 
5849     return 0;
5850 }
5851 
5852 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5853 {
5854     uint32_t usec_timeout = 50000;  /* wait for 50ms */
5855     uint32_t tmp;
5856     int i;
5857     uint64_t addr;
5858 
5859     /* Trigger an invalidation of the L1 instruction caches */
5860     tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5861     tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5862     WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5863 
5864     /* Wait for invalidation complete */
5865     for (i = 0; i < usec_timeout; i++) {
5866         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5867         if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5868             INVALIDATE_CACHE_COMPLETE))
5869             break;
5870         udelay(1);
5871     }
5872 
5873     if (i >= usec_timeout) {
5874         dev_err(adev->dev, "failed to invalidate instruction cache\n");
5875         return -EINVAL;
5876     }
5877 
5878     /* Program pfp ucode address into intruction cache address register */
5879     addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5880         rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5881     WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5882             lower_32_bits(addr) & 0xFFFFF000);
5883     WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5884             upper_32_bits(addr));
5885 
5886     return 0;
5887 }
5888 
5889 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5890 {
5891     uint32_t usec_timeout = 50000;  /* wait for 50ms */
5892     uint32_t tmp;
5893     int i;
5894     uint64_t addr;
5895 
5896     /* Trigger an invalidation of the L1 instruction caches */
5897     tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5898     tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5899     WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5900 
5901     /* Wait for invalidation complete */
5902     for (i = 0; i < usec_timeout; i++) {
5903         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5904         if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5905             INVALIDATE_CACHE_COMPLETE))
5906             break;
5907         udelay(1);
5908     }
5909 
5910     if (i >= usec_timeout) {
5911         dev_err(adev->dev, "failed to invalidate instruction cache\n");
5912         return -EINVAL;
5913     }
5914 
5915     /* Program mec1 ucode address into intruction cache address register */
5916     addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5917         rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5918     WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5919             lower_32_bits(addr) & 0xFFFFF000);
5920     WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5921             upper_32_bits(addr));
5922 
5923     return 0;
5924 }
5925 
5926 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5927 {
5928     uint32_t cp_status;
5929     uint32_t bootload_status;
5930     int i, r;
5931 
5932     for (i = 0; i < adev->usec_timeout; i++) {
5933         cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5934         bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5935         if ((cp_status == 0) &&
5936             (REG_GET_FIELD(bootload_status,
5937             RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5938             break;
5939         }
5940         udelay(1);
5941     }
5942 
5943     if (i >= adev->usec_timeout) {
5944         dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5945         return -ETIMEDOUT;
5946     }
5947 
5948     if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5949         r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5950         if (r)
5951             return r;
5952 
5953         r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5954         if (r)
5955             return r;
5956 
5957         r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5958         if (r)
5959             return r;
5960 
5961         r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5962         if (r)
5963             return r;
5964     }
5965 
5966     return 0;
5967 }
5968 
5969 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5970 {
5971     int i;
5972     u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5973 
5974     tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5975     tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5976     tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5977 
5978     if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
5979         WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5980     } else {
5981         WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5982     }
5983 
5984     for (i = 0; i < adev->usec_timeout; i++) {
5985         if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5986             break;
5987         udelay(1);
5988     }
5989 
5990     if (i >= adev->usec_timeout)
5991         DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5992 
5993     return 0;
5994 }
5995 
5996 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5997 {
5998     int r;
5999     const struct gfx_firmware_header_v1_0 *pfp_hdr;
6000     const __le32 *fw_data;
6001     unsigned i, fw_size;
6002     uint32_t tmp;
6003     uint32_t usec_timeout = 50000;  /* wait for 50ms */
6004 
6005     pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
6006         adev->gfx.pfp_fw->data;
6007 
6008     amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
6009 
6010     fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
6011         le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
6012     fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
6013 
6014     r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
6015                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6016                       &adev->gfx.pfp.pfp_fw_obj,
6017                       &adev->gfx.pfp.pfp_fw_gpu_addr,
6018                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
6019     if (r) {
6020         dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
6021         gfx_v10_0_pfp_fini(adev);
6022         return r;
6023     }
6024 
6025     memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
6026 
6027     amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
6028     amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
6029 
6030     /* Trigger an invalidation of the L1 instruction caches */
6031     tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
6032     tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6033     WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
6034 
6035     /* Wait for invalidation complete */
6036     for (i = 0; i < usec_timeout; i++) {
6037         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
6038         if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
6039             INVALIDATE_CACHE_COMPLETE))
6040             break;
6041         udelay(1);
6042     }
6043 
6044     if (i >= usec_timeout) {
6045         dev_err(adev->dev, "failed to invalidate instruction cache\n");
6046         return -EINVAL;
6047     }
6048 
6049     if (amdgpu_emu_mode == 1)
6050         adev->hdp.funcs->flush_hdp(adev, NULL);
6051 
6052     tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
6053     tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
6054     tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
6055     tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
6056     tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6057     WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
6058     WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
6059         adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
6060     WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
6061         upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
6062 
6063     WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
6064 
6065     for (i = 0; i < pfp_hdr->jt_size; i++)
6066         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
6067                  le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
6068 
6069     WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
6070 
6071     return 0;
6072 }
6073 
6074 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
6075 {
6076     int r;
6077     const struct gfx_firmware_header_v1_0 *ce_hdr;
6078     const __le32 *fw_data;
6079     unsigned i, fw_size;
6080     uint32_t tmp;
6081     uint32_t usec_timeout = 50000;  /* wait for 50ms */
6082 
6083     ce_hdr = (const struct gfx_firmware_header_v1_0 *)
6084         adev->gfx.ce_fw->data;
6085 
6086     amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
6087 
6088     fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
6089         le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
6090     fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
6091 
6092     r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
6093                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6094                       &adev->gfx.ce.ce_fw_obj,
6095                       &adev->gfx.ce.ce_fw_gpu_addr,
6096                       (void **)&adev->gfx.ce.ce_fw_ptr);
6097     if (r) {
6098         dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
6099         gfx_v10_0_ce_fini(adev);
6100         return r;
6101     }
6102 
6103     memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
6104 
6105     amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
6106     amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
6107 
6108     /* Trigger an invalidation of the L1 instruction caches */
6109     tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6110     tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6111     WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
6112 
6113     /* Wait for invalidation complete */
6114     for (i = 0; i < usec_timeout; i++) {
6115         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
6116         if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
6117             INVALIDATE_CACHE_COMPLETE))
6118             break;
6119         udelay(1);
6120     }
6121 
6122     if (i >= usec_timeout) {
6123         dev_err(adev->dev, "failed to invalidate instruction cache\n");
6124         return -EINVAL;
6125     }
6126 
6127     if (amdgpu_emu_mode == 1)
6128         adev->hdp.funcs->flush_hdp(adev, NULL);
6129 
6130     tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
6131     tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
6132     tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
6133     tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
6134     tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6135     WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
6136         adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
6137     WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
6138         upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
6139 
6140     WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
6141 
6142     for (i = 0; i < ce_hdr->jt_size; i++)
6143         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
6144                  le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
6145 
6146     WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
6147 
6148     return 0;
6149 }
6150 
6151 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
6152 {
6153     int r;
6154     const struct gfx_firmware_header_v1_0 *me_hdr;
6155     const __le32 *fw_data;
6156     unsigned i, fw_size;
6157     uint32_t tmp;
6158     uint32_t usec_timeout = 50000;  /* wait for 50ms */
6159 
6160     me_hdr = (const struct gfx_firmware_header_v1_0 *)
6161         adev->gfx.me_fw->data;
6162 
6163     amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
6164 
6165     fw_data = (const __le32 *)(adev->gfx.me_fw->data +
6166         le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
6167     fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
6168 
6169     r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
6170                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
6171                       &adev->gfx.me.me_fw_obj,
6172                       &adev->gfx.me.me_fw_gpu_addr,
6173                       (void **)&adev->gfx.me.me_fw_ptr);
6174     if (r) {
6175         dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
6176         gfx_v10_0_me_fini(adev);
6177         return r;
6178     }
6179 
6180     memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
6181 
6182     amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
6183     amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
6184 
6185     /* Trigger an invalidation of the L1 instruction caches */
6186     tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6187     tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6188     WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
6189 
6190     /* Wait for invalidation complete */
6191     for (i = 0; i < usec_timeout; i++) {
6192         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
6193         if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
6194             INVALIDATE_CACHE_COMPLETE))
6195             break;
6196         udelay(1);
6197     }
6198 
6199     if (i >= usec_timeout) {
6200         dev_err(adev->dev, "failed to invalidate instruction cache\n");
6201         return -EINVAL;
6202     }
6203 
6204     if (amdgpu_emu_mode == 1)
6205         adev->hdp.funcs->flush_hdp(adev, NULL);
6206 
6207     tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
6208     tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
6209     tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
6210     tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
6211     tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6212     WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
6213         adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
6214     WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
6215         upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
6216 
6217     WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
6218 
6219     for (i = 0; i < me_hdr->jt_size; i++)
6220         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
6221                  le32_to_cpup(fw_data + me_hdr->jt_offset + i));
6222 
6223     WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
6224 
6225     return 0;
6226 }
6227 
6228 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
6229 {
6230     int r;
6231 
6232     if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
6233         return -EINVAL;
6234 
6235     gfx_v10_0_cp_gfx_enable(adev, false);
6236 
6237     r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
6238     if (r) {
6239         dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
6240         return r;
6241     }
6242 
6243     r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
6244     if (r) {
6245         dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
6246         return r;
6247     }
6248 
6249     r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6250     if (r) {
6251         dev_err(adev->dev, "(%d) failed to load me fw\n", r);
6252         return r;
6253     }
6254 
6255     return 0;
6256 }
6257 
6258 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6259 {
6260     struct amdgpu_ring *ring;
6261     const struct cs_section_def *sect = NULL;
6262     const struct cs_extent_def *ext = NULL;
6263     int r, i;
6264     int ctx_reg_offset;
6265 
6266     /* init the CP */
6267     WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
6268              adev->gfx.config.max_hw_contexts - 1);
6269     WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
6270 
6271     gfx_v10_0_cp_gfx_enable(adev, true);
6272 
6273     ring = &adev->gfx.gfx_ring[0];
6274     r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6275     if (r) {
6276         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6277         return r;
6278     }
6279 
6280     amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6281     amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6282 
6283     amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6284     amdgpu_ring_write(ring, 0x80000000);
6285     amdgpu_ring_write(ring, 0x80000000);
6286 
6287     for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
6288         for (ext = sect->section; ext->extent != NULL; ++ext) {
6289             if (sect->id == SECT_CONTEXT) {
6290                 amdgpu_ring_write(ring,
6291                           PACKET3(PACKET3_SET_CONTEXT_REG,
6292                               ext->reg_count));
6293                 amdgpu_ring_write(ring, ext->reg_index -
6294                           PACKET3_SET_CONTEXT_REG_START);
6295                 for (i = 0; i < ext->reg_count; i++)
6296                     amdgpu_ring_write(ring, ext->extent[i]);
6297             }
6298         }
6299     }
6300 
6301     ctx_reg_offset =
6302         SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6303     amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6304     amdgpu_ring_write(ring, ctx_reg_offset);
6305     amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6306 
6307     amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6308     amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6309 
6310     amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6311     amdgpu_ring_write(ring, 0);
6312 
6313     amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6314     amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6315     amdgpu_ring_write(ring, 0x8000);
6316     amdgpu_ring_write(ring, 0x8000);
6317 
6318     amdgpu_ring_commit(ring);
6319 
6320     /* submit cs packet to copy state 0 to next available state */
6321     if (adev->gfx.num_gfx_rings > 1) {
6322         /* maximum supported gfx ring is 2 */
6323         ring = &adev->gfx.gfx_ring[1];
6324         r = amdgpu_ring_alloc(ring, 2);
6325         if (r) {
6326             DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6327             return r;
6328         }
6329 
6330         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6331         amdgpu_ring_write(ring, 0);
6332 
6333         amdgpu_ring_commit(ring);
6334     }
6335     return 0;
6336 }
6337 
6338 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6339                      CP_PIPE_ID pipe)
6340 {
6341     u32 tmp;
6342 
6343     tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6344     tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6345 
6346     WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6347 }
6348 
6349 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6350                       struct amdgpu_ring *ring)
6351 {
6352     u32 tmp;
6353 
6354     if (!amdgpu_async_gfx_ring) {
6355         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6356         if (ring->use_doorbell) {
6357             tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6358                         DOORBELL_OFFSET, ring->doorbell_index);
6359             tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6360                         DOORBELL_EN, 1);
6361         } else {
6362             tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6363                         DOORBELL_EN, 0);
6364         }
6365         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6366     }
6367     switch (adev->ip_versions[GC_HWIP][0]) {
6368     case IP_VERSION(10, 3, 0):
6369     case IP_VERSION(10, 3, 2):
6370     case IP_VERSION(10, 3, 1):
6371     case IP_VERSION(10, 3, 4):
6372     case IP_VERSION(10, 3, 5):
6373     case IP_VERSION(10, 3, 6):
6374     case IP_VERSION(10, 3, 3):
6375     case IP_VERSION(10, 3, 7):
6376         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6377                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6378         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6379 
6380         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6381                  CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6382         break;
6383     default:
6384         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6385                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
6386         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6387 
6388         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6389                  CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6390         break;
6391     }
6392 }
6393 
6394 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6395 {
6396     struct amdgpu_ring *ring;
6397     u32 tmp;
6398     u32 rb_bufsz;
6399     u64 rb_addr, rptr_addr, wptr_gpu_addr;
6400     u32 i;
6401 
6402     /* Set the write pointer delay */
6403     WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6404 
6405     /* set the RB to use vmid 0 */
6406     WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6407 
6408     /* Init gfx ring 0 for pipe 0 */
6409     mutex_lock(&adev->srbm_mutex);
6410     gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6411 
6412     /* Set ring buffer size */
6413     ring = &adev->gfx.gfx_ring[0];
6414     rb_bufsz = order_base_2(ring->ring_size / 8);
6415     tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6416     tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6417 #ifdef __BIG_ENDIAN
6418     tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6419 #endif
6420     WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6421 
6422     /* Initialize the ring buffer's write pointers */
6423     ring->wptr = 0;
6424     WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6425     WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6426 
6427     /* set the wb address wether it's enabled or not */
6428     rptr_addr = ring->rptr_gpu_addr;
6429     WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6430     WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6431              CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6432 
6433     wptr_gpu_addr = ring->wptr_gpu_addr;
6434     WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6435              lower_32_bits(wptr_gpu_addr));
6436     WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6437              upper_32_bits(wptr_gpu_addr));
6438 
6439     mdelay(1);
6440     WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6441 
6442     rb_addr = ring->gpu_addr >> 8;
6443     WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6444     WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6445 
6446     WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6447 
6448     gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6449     mutex_unlock(&adev->srbm_mutex);
6450 
6451     /* Init gfx ring 1 for pipe 1 */
6452     if (adev->gfx.num_gfx_rings > 1) {
6453         mutex_lock(&adev->srbm_mutex);
6454         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6455         /* maximum supported gfx ring is 2 */
6456         ring = &adev->gfx.gfx_ring[1];
6457         rb_bufsz = order_base_2(ring->ring_size / 8);
6458         tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6459         tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6460         WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6461         /* Initialize the ring buffer's write pointers */
6462         ring->wptr = 0;
6463         WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6464         WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6465         /* Set the wb address wether it's enabled or not */
6466         rptr_addr = ring->rptr_gpu_addr;
6467         WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6468         WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6469                  CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6470         wptr_gpu_addr = ring->wptr_gpu_addr;
6471         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6472                  lower_32_bits(wptr_gpu_addr));
6473         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6474                  upper_32_bits(wptr_gpu_addr));
6475 
6476         mdelay(1);
6477         WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6478 
6479         rb_addr = ring->gpu_addr >> 8;
6480         WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6481         WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6482         WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6483 
6484         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6485         mutex_unlock(&adev->srbm_mutex);
6486     }
6487     /* Switch to pipe 0 */
6488     mutex_lock(&adev->srbm_mutex);
6489     gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6490     mutex_unlock(&adev->srbm_mutex);
6491 
6492     /* start the ring */
6493     gfx_v10_0_cp_gfx_start(adev);
6494 
6495     for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6496         ring = &adev->gfx.gfx_ring[i];
6497         ring->sched.ready = true;
6498     }
6499 
6500     return 0;
6501 }
6502 
6503 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6504 {
6505     if (enable) {
6506         switch (adev->ip_versions[GC_HWIP][0]) {
6507         case IP_VERSION(10, 3, 0):
6508         case IP_VERSION(10, 3, 2):
6509         case IP_VERSION(10, 3, 1):
6510         case IP_VERSION(10, 3, 4):
6511         case IP_VERSION(10, 3, 5):
6512         case IP_VERSION(10, 3, 6):
6513         case IP_VERSION(10, 3, 3):
6514         case IP_VERSION(10, 3, 7):
6515             WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6516             break;
6517         default:
6518             WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6519             break;
6520         }
6521     } else {
6522         switch (adev->ip_versions[GC_HWIP][0]) {
6523         case IP_VERSION(10, 3, 0):
6524         case IP_VERSION(10, 3, 2):
6525         case IP_VERSION(10, 3, 1):
6526         case IP_VERSION(10, 3, 4):
6527         case IP_VERSION(10, 3, 5):
6528         case IP_VERSION(10, 3, 6):
6529         case IP_VERSION(10, 3, 3):
6530         case IP_VERSION(10, 3, 7):
6531             WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6532                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6533                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6534             break;
6535         default:
6536             WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6537                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6538                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6539             break;
6540         }
6541         adev->gfx.kiq.ring.sched.ready = false;
6542     }
6543     udelay(50);
6544 }
6545 
6546 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6547 {
6548     const struct gfx_firmware_header_v1_0 *mec_hdr;
6549     const __le32 *fw_data;
6550     unsigned i;
6551     u32 tmp;
6552     u32 usec_timeout = 50000; /* Wait for 50 ms */
6553 
6554     if (!adev->gfx.mec_fw)
6555         return -EINVAL;
6556 
6557     gfx_v10_0_cp_compute_enable(adev, false);
6558 
6559     mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6560     amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6561 
6562     fw_data = (const __le32 *)
6563         (adev->gfx.mec_fw->data +
6564          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6565 
6566     /* Trigger an invalidation of the L1 instruction caches */
6567     tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6568     tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6569     WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6570 
6571     /* Wait for invalidation complete */
6572     for (i = 0; i < usec_timeout; i++) {
6573         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6574         if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6575                        INVALIDATE_CACHE_COMPLETE))
6576             break;
6577         udelay(1);
6578     }
6579 
6580     if (i >= usec_timeout) {
6581         dev_err(adev->dev, "failed to invalidate instruction cache\n");
6582         return -EINVAL;
6583     }
6584 
6585     if (amdgpu_emu_mode == 1)
6586         adev->hdp.funcs->flush_hdp(adev, NULL);
6587 
6588     tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6589     tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6590     tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6591     tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6592     WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6593 
6594     WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6595              0xFFFFF000);
6596     WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6597              upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6598 
6599     /* MEC1 */
6600     WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6601 
6602     for (i = 0; i < mec_hdr->jt_size; i++)
6603         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6604                  le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6605 
6606     WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6607 
6608     /*
6609      * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6610      * different microcode than MEC1.
6611      */
6612 
6613     return 0;
6614 }
6615 
6616 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6617 {
6618     uint32_t tmp;
6619     struct amdgpu_device *adev = ring->adev;
6620 
6621     /* tell RLC which is KIQ queue */
6622     switch (adev->ip_versions[GC_HWIP][0]) {
6623     case IP_VERSION(10, 3, 0):
6624     case IP_VERSION(10, 3, 2):
6625     case IP_VERSION(10, 3, 1):
6626     case IP_VERSION(10, 3, 4):
6627     case IP_VERSION(10, 3, 5):
6628     case IP_VERSION(10, 3, 6):
6629     case IP_VERSION(10, 3, 3):
6630     case IP_VERSION(10, 3, 7):
6631         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6632         tmp &= 0xffffff00;
6633         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6634         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6635         tmp |= 0x80;
6636         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6637         break;
6638     default:
6639         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6640         tmp &= 0xffffff00;
6641         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6642         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6643         tmp |= 0x80;
6644         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6645         break;
6646     }
6647 }
6648 
6649 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev,
6650                        struct v10_gfx_mqd *mqd,
6651                        struct amdgpu_mqd_prop *prop)
6652 {
6653     bool priority = 0;
6654     u32 tmp;
6655 
6656     /* set up default queue priority level
6657      * 0x0 = low priority, 0x1 = high priority
6658      */
6659     if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)
6660         priority = 1;
6661 
6662     tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6663     tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
6664     mqd->cp_gfx_hqd_queue_priority = tmp;
6665 }
6666 
6667 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
6668                   struct amdgpu_mqd_prop *prop)
6669 {
6670     struct v10_gfx_mqd *mqd = m;
6671     uint64_t hqd_gpu_addr, wb_gpu_addr;
6672     uint32_t tmp;
6673     uint32_t rb_bufsz;
6674 
6675     /* set up gfx hqd wptr */
6676     mqd->cp_gfx_hqd_wptr = 0;
6677     mqd->cp_gfx_hqd_wptr_hi = 0;
6678 
6679     /* set the pointer to the MQD */
6680     mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
6681     mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6682 
6683     /* set up mqd control */
6684     tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6685     tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6686     tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6687     tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6688     mqd->cp_gfx_mqd_control = tmp;
6689 
6690     /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6691     tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6692     tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6693     mqd->cp_gfx_hqd_vmid = 0;
6694 
6695     /* set up gfx queue priority */
6696     gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop);
6697 
6698     /* set up time quantum */
6699     tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6700     tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6701     mqd->cp_gfx_hqd_quantum = tmp;
6702 
6703     /* set up gfx hqd base. this is similar as CP_RB_BASE */
6704     hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6705     mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6706     mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6707 
6708     /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6709     wb_gpu_addr = prop->rptr_gpu_addr;
6710     mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6711     mqd->cp_gfx_hqd_rptr_addr_hi =
6712         upper_32_bits(wb_gpu_addr) & 0xffff;
6713 
6714     /* set up rb_wptr_poll addr */
6715     wb_gpu_addr = prop->wptr_gpu_addr;
6716     mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6717     mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6718 
6719     /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6720     rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
6721     tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6722     tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6723     tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6724 #ifdef __BIG_ENDIAN
6725     tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6726 #endif
6727     mqd->cp_gfx_hqd_cntl = tmp;
6728 
6729     /* set up cp_doorbell_control */
6730     tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6731     if (prop->use_doorbell) {
6732         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6733                     DOORBELL_OFFSET, prop->doorbell_index);
6734         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6735                     DOORBELL_EN, 1);
6736     } else
6737         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6738                     DOORBELL_EN, 0);
6739     mqd->cp_rb_doorbell_control = tmp;
6740 
6741     /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6742     mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6743 
6744     /* active the queue */
6745     mqd->cp_gfx_hqd_active = 1;
6746 
6747     return 0;
6748 }
6749 
6750 #ifdef BRING_UP_DEBUG
6751 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6752 {
6753     struct amdgpu_device *adev = ring->adev;
6754     struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6755 
6756     /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6757     WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6758     WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6759 
6760     /* set GFX_MQD_BASE */
6761     WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6762     WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6763 
6764     /* set GFX_MQD_CONTROL */
6765     WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6766 
6767     /* set GFX_HQD_VMID to 0 */
6768     WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6769 
6770     WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6771             mqd->cp_gfx_hqd_queue_priority);
6772     WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6773 
6774     /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6775     WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6776     WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6777 
6778     /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6779     WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6780     WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6781 
6782     /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6783     WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6784 
6785     /* set RB_WPTR_POLL_ADDR */
6786     WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6787     WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6788 
6789     /* set RB_DOORBELL_CONTROL */
6790     WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6791 
6792     /* active the queue */
6793     WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6794 
6795     return 0;
6796 }
6797 #endif
6798 
6799 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6800 {
6801     struct amdgpu_device *adev = ring->adev;
6802     struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6803     int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6804 
6805     if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6806         memset((void *)mqd, 0, sizeof(*mqd));
6807         mutex_lock(&adev->srbm_mutex);
6808         nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6809         amdgpu_ring_init_mqd(ring);
6810 
6811         /*
6812          * if there are 2 gfx rings, set the lower doorbell
6813          * range of the first ring, otherwise the range of
6814          * the second ring will override the first ring
6815          */
6816         if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6817             gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6818 
6819 #ifdef BRING_UP_DEBUG
6820         gfx_v10_0_gfx_queue_init_register(ring);
6821 #endif
6822         nv_grbm_select(adev, 0, 0, 0, 0);
6823         mutex_unlock(&adev->srbm_mutex);
6824         if (adev->gfx.me.mqd_backup[mqd_idx])
6825             memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6826     } else if (amdgpu_in_reset(adev)) {
6827         /* reset mqd with the backup copy */
6828         if (adev->gfx.me.mqd_backup[mqd_idx])
6829             memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6830         /* reset the ring */
6831         ring->wptr = 0;
6832         *ring->wptr_cpu_addr = 0;
6833         amdgpu_ring_clear_ring(ring);
6834 #ifdef BRING_UP_DEBUG
6835         mutex_lock(&adev->srbm_mutex);
6836         nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6837         gfx_v10_0_gfx_queue_init_register(ring);
6838         nv_grbm_select(adev, 0, 0, 0, 0);
6839         mutex_unlock(&adev->srbm_mutex);
6840 #endif
6841     } else {
6842         amdgpu_ring_clear_ring(ring);
6843     }
6844 
6845     return 0;
6846 }
6847 
6848 #ifndef BRING_UP_DEBUG
6849 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6850 {
6851     struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6852     struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6853     int r, i;
6854 
6855     if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6856         return -EINVAL;
6857 
6858     r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6859                     adev->gfx.num_gfx_rings);
6860     if (r) {
6861         DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6862         return r;
6863     }
6864 
6865     for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6866         kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6867 
6868     return amdgpu_ring_test_helper(kiq_ring);
6869 }
6870 #endif
6871 
6872 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6873 {
6874     int r, i;
6875     struct amdgpu_ring *ring;
6876 
6877     for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6878         ring = &adev->gfx.gfx_ring[i];
6879 
6880         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6881         if (unlikely(r != 0))
6882             goto done;
6883 
6884         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6885         if (!r) {
6886             r = gfx_v10_0_gfx_init_queue(ring);
6887             amdgpu_bo_kunmap(ring->mqd_obj);
6888             ring->mqd_ptr = NULL;
6889         }
6890         amdgpu_bo_unreserve(ring->mqd_obj);
6891         if (r)
6892             goto done;
6893     }
6894 #ifndef BRING_UP_DEBUG
6895     r = gfx_v10_0_kiq_enable_kgq(adev);
6896     if (r)
6897         goto done;
6898 #endif
6899     r = gfx_v10_0_cp_gfx_start(adev);
6900     if (r)
6901         goto done;
6902 
6903     for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6904         ring = &adev->gfx.gfx_ring[i];
6905         ring->sched.ready = true;
6906     }
6907 done:
6908     return r;
6909 }
6910 
6911 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
6912                       struct amdgpu_mqd_prop *prop)
6913 {
6914     struct v10_compute_mqd *mqd = m;
6915     uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6916     uint32_t tmp;
6917 
6918     mqd->header = 0xC0310800;
6919     mqd->compute_pipelinestat_enable = 0x00000001;
6920     mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6921     mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6922     mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6923     mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6924     mqd->compute_misc_reserved = 0x00000003;
6925 
6926     eop_base_addr = prop->eop_gpu_addr >> 8;
6927     mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6928     mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6929 
6930     /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6931     tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6932     tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6933             (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6934 
6935     mqd->cp_hqd_eop_control = tmp;
6936 
6937     /* enable doorbell? */
6938     tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6939 
6940     if (prop->use_doorbell) {
6941         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6942                     DOORBELL_OFFSET, prop->doorbell_index);
6943         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6944                     DOORBELL_EN, 1);
6945         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6946                     DOORBELL_SOURCE, 0);
6947         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6948                     DOORBELL_HIT, 0);
6949     } else {
6950         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6951                     DOORBELL_EN, 0);
6952     }
6953 
6954     mqd->cp_hqd_pq_doorbell_control = tmp;
6955 
6956     /* disable the queue if it's active */
6957     mqd->cp_hqd_dequeue_request = 0;
6958     mqd->cp_hqd_pq_rptr = 0;
6959     mqd->cp_hqd_pq_wptr_lo = 0;
6960     mqd->cp_hqd_pq_wptr_hi = 0;
6961 
6962     /* set the pointer to the MQD */
6963     mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
6964     mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6965 
6966     /* set MQD vmid to 0 */
6967     tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6968     tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6969     mqd->cp_mqd_control = tmp;
6970 
6971     /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6972     hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6973     mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6974     mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6975 
6976     /* set up the HQD, this is similar to CP_RB0_CNTL */
6977     tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6978     tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6979                 (order_base_2(prop->queue_size / 4) - 1));
6980     tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6981                 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
6982 #ifdef __BIG_ENDIAN
6983     tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6984 #endif
6985     tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6986     tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6987     tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6988     tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6989     mqd->cp_hqd_pq_control = tmp;
6990 
6991     /* set the wb address whether it's enabled or not */
6992     wb_gpu_addr = prop->rptr_gpu_addr;
6993     mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6994     mqd->cp_hqd_pq_rptr_report_addr_hi =
6995         upper_32_bits(wb_gpu_addr) & 0xffff;
6996 
6997     /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6998     wb_gpu_addr = prop->wptr_gpu_addr;
6999     mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
7000     mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
7001 
7002     /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
7003     mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
7004 
7005     /* set the vmid for the queue */
7006     mqd->cp_hqd_vmid = 0;
7007 
7008     tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
7009     tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
7010     mqd->cp_hqd_persistent_state = tmp;
7011 
7012     /* set MIN_IB_AVAIL_SIZE */
7013     tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
7014     tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
7015     mqd->cp_hqd_ib_control = tmp;
7016 
7017     /* set static priority for a compute queue/ring */
7018     mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
7019     mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
7020 
7021     mqd->cp_hqd_active = prop->hqd_active;
7022 
7023     return 0;
7024 }
7025 
7026 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
7027 {
7028     struct amdgpu_device *adev = ring->adev;
7029     struct v10_compute_mqd *mqd = ring->mqd_ptr;
7030     int j;
7031 
7032     /* inactivate the queue */
7033     if (amdgpu_sriov_vf(adev))
7034         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
7035 
7036     /* disable wptr polling */
7037     WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
7038 
7039     /* disable the queue if it's active */
7040     if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
7041         WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
7042         for (j = 0; j < adev->usec_timeout; j++) {
7043             if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
7044                 break;
7045             udelay(1);
7046         }
7047         WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
7048                mqd->cp_hqd_dequeue_request);
7049         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
7050                mqd->cp_hqd_pq_rptr);
7051         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
7052                mqd->cp_hqd_pq_wptr_lo);
7053         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
7054                mqd->cp_hqd_pq_wptr_hi);
7055     }
7056 
7057     /* disable doorbells */
7058     WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
7059 
7060     /* write the EOP addr */
7061     WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
7062            mqd->cp_hqd_eop_base_addr_lo);
7063     WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
7064            mqd->cp_hqd_eop_base_addr_hi);
7065 
7066     /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
7067     WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
7068            mqd->cp_hqd_eop_control);
7069 
7070     /* set the pointer to the MQD */
7071     WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
7072            mqd->cp_mqd_base_addr_lo);
7073     WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
7074            mqd->cp_mqd_base_addr_hi);
7075 
7076     /* set MQD vmid to 0 */
7077     WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
7078            mqd->cp_mqd_control);
7079 
7080     /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
7081     WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
7082            mqd->cp_hqd_pq_base_lo);
7083     WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
7084            mqd->cp_hqd_pq_base_hi);
7085 
7086     /* set up the HQD, this is similar to CP_RB0_CNTL */
7087     WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
7088            mqd->cp_hqd_pq_control);
7089 
7090     /* set the wb address whether it's enabled or not */
7091     WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
7092         mqd->cp_hqd_pq_rptr_report_addr_lo);
7093     WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
7094         mqd->cp_hqd_pq_rptr_report_addr_hi);
7095 
7096     /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
7097     WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
7098            mqd->cp_hqd_pq_wptr_poll_addr_lo);
7099     WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
7100            mqd->cp_hqd_pq_wptr_poll_addr_hi);
7101 
7102     /* enable the doorbell if requested */
7103     if (ring->use_doorbell) {
7104         WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
7105             (adev->doorbell_index.kiq * 2) << 2);
7106         WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
7107             (adev->doorbell_index.userqueue_end * 2) << 2);
7108     }
7109 
7110     WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
7111            mqd->cp_hqd_pq_doorbell_control);
7112 
7113     /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
7114     WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
7115            mqd->cp_hqd_pq_wptr_lo);
7116     WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
7117            mqd->cp_hqd_pq_wptr_hi);
7118 
7119     /* set the vmid for the queue */
7120     WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
7121 
7122     WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
7123            mqd->cp_hqd_persistent_state);
7124 
7125     /* activate the queue */
7126     WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
7127            mqd->cp_hqd_active);
7128 
7129     if (ring->use_doorbell)
7130         WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
7131 
7132     return 0;
7133 }
7134 
7135 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
7136 {
7137     struct amdgpu_device *adev = ring->adev;
7138     struct v10_compute_mqd *mqd = ring->mqd_ptr;
7139     int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
7140 
7141     gfx_v10_0_kiq_setting(ring);
7142 
7143     if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7144         /* reset MQD to a clean status */
7145         if (adev->gfx.mec.mqd_backup[mqd_idx])
7146             memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7147 
7148         /* reset ring buffer */
7149         ring->wptr = 0;
7150         amdgpu_ring_clear_ring(ring);
7151 
7152         mutex_lock(&adev->srbm_mutex);
7153         nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7154         gfx_v10_0_kiq_init_register(ring);
7155         nv_grbm_select(adev, 0, 0, 0, 0);
7156         mutex_unlock(&adev->srbm_mutex);
7157     } else {
7158         memset((void *)mqd, 0, sizeof(*mqd));
7159         mutex_lock(&adev->srbm_mutex);
7160         nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7161         amdgpu_ring_init_mqd(ring);
7162         gfx_v10_0_kiq_init_register(ring);
7163         nv_grbm_select(adev, 0, 0, 0, 0);
7164         mutex_unlock(&adev->srbm_mutex);
7165 
7166         if (adev->gfx.mec.mqd_backup[mqd_idx])
7167             memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7168     }
7169 
7170     return 0;
7171 }
7172 
7173 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
7174 {
7175     struct amdgpu_device *adev = ring->adev;
7176     struct v10_compute_mqd *mqd = ring->mqd_ptr;
7177     int mqd_idx = ring - &adev->gfx.compute_ring[0];
7178 
7179     if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
7180         memset((void *)mqd, 0, sizeof(*mqd));
7181         mutex_lock(&adev->srbm_mutex);
7182         nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
7183         amdgpu_ring_init_mqd(ring);
7184         nv_grbm_select(adev, 0, 0, 0, 0);
7185         mutex_unlock(&adev->srbm_mutex);
7186 
7187         if (adev->gfx.mec.mqd_backup[mqd_idx])
7188             memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
7189     } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
7190         /* reset MQD to a clean status */
7191         if (adev->gfx.mec.mqd_backup[mqd_idx])
7192             memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
7193 
7194         /* reset ring buffer */
7195         ring->wptr = 0;
7196         atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
7197         amdgpu_ring_clear_ring(ring);
7198     } else {
7199         amdgpu_ring_clear_ring(ring);
7200     }
7201 
7202     return 0;
7203 }
7204 
7205 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
7206 {
7207     struct amdgpu_ring *ring;
7208     int r;
7209 
7210     ring = &adev->gfx.kiq.ring;
7211 
7212     r = amdgpu_bo_reserve(ring->mqd_obj, false);
7213     if (unlikely(r != 0))
7214         return r;
7215 
7216     r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7217     if (unlikely(r != 0))
7218         return r;
7219 
7220     gfx_v10_0_kiq_init_queue(ring);
7221     amdgpu_bo_kunmap(ring->mqd_obj);
7222     ring->mqd_ptr = NULL;
7223     amdgpu_bo_unreserve(ring->mqd_obj);
7224     ring->sched.ready = true;
7225     return 0;
7226 }
7227 
7228 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
7229 {
7230     struct amdgpu_ring *ring = NULL;
7231     int r = 0, i;
7232 
7233     gfx_v10_0_cp_compute_enable(adev, true);
7234 
7235     for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7236         ring = &adev->gfx.compute_ring[i];
7237 
7238         r = amdgpu_bo_reserve(ring->mqd_obj, false);
7239         if (unlikely(r != 0))
7240             goto done;
7241         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
7242         if (!r) {
7243             r = gfx_v10_0_kcq_init_queue(ring);
7244             amdgpu_bo_kunmap(ring->mqd_obj);
7245             ring->mqd_ptr = NULL;
7246         }
7247         amdgpu_bo_unreserve(ring->mqd_obj);
7248         if (r)
7249             goto done;
7250     }
7251 
7252     r = amdgpu_gfx_enable_kcq(adev);
7253 done:
7254     return r;
7255 }
7256 
7257 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
7258 {
7259     int r, i;
7260     struct amdgpu_ring *ring;
7261 
7262     if (!(adev->flags & AMD_IS_APU))
7263         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7264 
7265     if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7266         /* legacy firmware loading */
7267         r = gfx_v10_0_cp_gfx_load_microcode(adev);
7268         if (r)
7269             return r;
7270 
7271         r = gfx_v10_0_cp_compute_load_microcode(adev);
7272         if (r)
7273             return r;
7274     }
7275 
7276     if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
7277         r = amdgpu_mes_kiq_hw_init(adev);
7278     else
7279         r = gfx_v10_0_kiq_resume(adev);
7280     if (r)
7281         return r;
7282 
7283     r = gfx_v10_0_kcq_resume(adev);
7284     if (r)
7285         return r;
7286 
7287     if (!amdgpu_async_gfx_ring) {
7288         r = gfx_v10_0_cp_gfx_resume(adev);
7289         if (r)
7290             return r;
7291     } else {
7292         r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7293         if (r)
7294             return r;
7295     }
7296 
7297     for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7298         ring = &adev->gfx.gfx_ring[i];
7299         r = amdgpu_ring_test_helper(ring);
7300         if (r)
7301             return r;
7302     }
7303 
7304     for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7305         ring = &adev->gfx.compute_ring[i];
7306         r = amdgpu_ring_test_helper(ring);
7307         if (r)
7308             return r;
7309     }
7310 
7311     return 0;
7312 }
7313 
7314 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
7315 {
7316     gfx_v10_0_cp_gfx_enable(adev, enable);
7317     gfx_v10_0_cp_compute_enable(adev, enable);
7318 }
7319 
7320 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7321 {
7322     uint32_t data, pattern = 0xDEADBEEF;
7323 
7324     /* check if mmVGT_ESGS_RING_SIZE_UMD
7325      * has been remapped to mmVGT_ESGS_RING_SIZE */
7326     switch (adev->ip_versions[GC_HWIP][0]) {
7327     case IP_VERSION(10, 3, 0):
7328     case IP_VERSION(10, 3, 2):
7329     case IP_VERSION(10, 3, 4):
7330     case IP_VERSION(10, 3, 5):
7331         data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
7332         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
7333         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7334 
7335         if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7336             WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
7337             return true;
7338         } else {
7339             WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7340             return false;
7341         }
7342         break;
7343     case IP_VERSION(10, 3, 1):
7344     case IP_VERSION(10, 3, 3):
7345     case IP_VERSION(10, 3, 6):
7346     case IP_VERSION(10, 3, 7):
7347         return true;
7348     default:
7349         data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7350         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7351         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7352 
7353         if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7354             WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7355             return true;
7356         } else {
7357             WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7358             return false;
7359         }
7360         break;
7361     }
7362 }
7363 
7364 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7365 {
7366     uint32_t data;
7367 
7368     if (amdgpu_sriov_vf(adev))
7369         return;
7370 
7371     /* initialize cam_index to 0
7372      * index will auto-inc after each data writting */
7373     WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7374 
7375     switch (adev->ip_versions[GC_HWIP][0]) {
7376     case IP_VERSION(10, 3, 0):
7377     case IP_VERSION(10, 3, 2):
7378     case IP_VERSION(10, 3, 1):
7379     case IP_VERSION(10, 3, 4):
7380     case IP_VERSION(10, 3, 5):
7381     case IP_VERSION(10, 3, 6):
7382     case IP_VERSION(10, 3, 3):
7383     case IP_VERSION(10, 3, 7):
7384         /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7385         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7386             GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7387                (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7388             GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7389         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7390         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7391 
7392         /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7393         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7394             GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7395                (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7396             GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7397         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7398         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7399 
7400         /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7401         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7402             GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7403                (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7404             GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7405         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7406         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7407 
7408         /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7409         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7410             GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7411                (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7412             GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7413         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7414         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7415 
7416         /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7417         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7418             GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7419                (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7420             GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7421         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7422         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7423 
7424         /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7425         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7426             GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7427                (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7428             GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7429         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7430         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7431 
7432         /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7433         data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7434             GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7435                (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7436             GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7437         break;
7438     default:
7439         /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7440         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7441             GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7442                (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7443             GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7444         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7445         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7446 
7447         /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7448         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7449             GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7450                (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7451             GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7452         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7453         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7454 
7455         /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7456         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7457             GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7458                (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7459             GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7460         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7461         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7462 
7463         /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7464         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7465             GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7466                (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7467             GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7468         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7469         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7470 
7471         /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7472         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7473             GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7474                (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7475             GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7476         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7477         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7478 
7479         /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7480         data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7481             GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7482                (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7483             GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7484         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7485         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7486 
7487         /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7488         data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7489             GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7490                (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7491             GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7492         break;
7493     }
7494 
7495     WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7496     WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7497 }
7498 
7499 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7500 {
7501     uint32_t data;
7502     data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7503     data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7504     WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7505 
7506     data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7507     data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7508     WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7509 }
7510 
7511 static int gfx_v10_0_hw_init(void *handle)
7512 {
7513     int r;
7514     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7515 
7516     if (!amdgpu_emu_mode)
7517         gfx_v10_0_init_golden_registers(adev);
7518 
7519     if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7520         /**
7521          * For gfx 10, rlc firmware loading relies on smu firmware is
7522          * loaded firstly, so in direct type, it has to load smc ucode
7523          * here before rlc.
7524          */
7525         if (!(adev->flags & AMD_IS_APU)) {
7526             r = amdgpu_pm_load_smu_firmware(adev, NULL);
7527             if (r)
7528                 return r;
7529         }
7530         gfx_v10_0_disable_gpa_mode(adev);
7531     }
7532 
7533     /* if GRBM CAM not remapped, set up the remapping */
7534     if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7535         gfx_v10_0_setup_grbm_cam_remapping(adev);
7536 
7537     gfx_v10_0_constants_init(adev);
7538 
7539     r = gfx_v10_0_rlc_resume(adev);
7540     if (r)
7541         return r;
7542 
7543     /*
7544      * init golden registers and rlc resume may override some registers,
7545      * reconfig them here
7546      */
7547     if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10) ||
7548         adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) ||
7549         adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2))
7550         gfx_v10_0_tcp_harvest(adev);
7551 
7552     r = gfx_v10_0_cp_resume(adev);
7553     if (r)
7554         return r;
7555 
7556     if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
7557         gfx_v10_3_program_pbb_mode(adev);
7558 
7559     if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
7560         gfx_v10_3_set_power_brake_sequence(adev);
7561 
7562     return r;
7563 }
7564 
7565 #ifndef BRING_UP_DEBUG
7566 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7567 {
7568     struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7569     struct amdgpu_ring *kiq_ring = &kiq->ring;
7570     int i;
7571 
7572     if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7573         return -EINVAL;
7574 
7575     if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7576                     adev->gfx.num_gfx_rings))
7577         return -ENOMEM;
7578 
7579     for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7580         kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7581                        PREEMPT_QUEUES, 0, 0);
7582 
7583     return amdgpu_ring_test_helper(kiq_ring);
7584 }
7585 #endif
7586 
7587 static int gfx_v10_0_hw_fini(void *handle)
7588 {
7589     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7590     int r;
7591     uint32_t tmp;
7592 
7593     amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7594     amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7595 
7596     if (!adev->no_hw_access) {
7597 #ifndef BRING_UP_DEBUG
7598         if (amdgpu_async_gfx_ring) {
7599             r = gfx_v10_0_kiq_disable_kgq(adev);
7600             if (r)
7601                 DRM_ERROR("KGQ disable failed\n");
7602         }
7603 #endif
7604         if (amdgpu_gfx_disable_kcq(adev))
7605             DRM_ERROR("KCQ disable failed\n");
7606     }
7607 
7608     if (amdgpu_sriov_vf(adev)) {
7609         gfx_v10_0_cp_gfx_enable(adev, false);
7610         /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7611         if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
7612             tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
7613             tmp &= 0xffffff00;
7614             WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
7615         } else {
7616             tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7617             tmp &= 0xffffff00;
7618             WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7619         }
7620 
7621         return 0;
7622     }
7623     gfx_v10_0_cp_enable(adev, false);
7624     gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7625 
7626     return 0;
7627 }
7628 
7629 static int gfx_v10_0_suspend(void *handle)
7630 {
7631     return gfx_v10_0_hw_fini(handle);
7632 }
7633 
7634 static int gfx_v10_0_resume(void *handle)
7635 {
7636     return gfx_v10_0_hw_init(handle);
7637 }
7638 
7639 static bool gfx_v10_0_is_idle(void *handle)
7640 {
7641     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7642 
7643     if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7644                 GRBM_STATUS, GUI_ACTIVE))
7645         return false;
7646     else
7647         return true;
7648 }
7649 
7650 static int gfx_v10_0_wait_for_idle(void *handle)
7651 {
7652     unsigned i;
7653     u32 tmp;
7654     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7655 
7656     for (i = 0; i < adev->usec_timeout; i++) {
7657         /* read MC_STATUS */
7658         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7659             GRBM_STATUS__GUI_ACTIVE_MASK;
7660 
7661         if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7662             return 0;
7663         udelay(1);
7664     }
7665     return -ETIMEDOUT;
7666 }
7667 
7668 static int gfx_v10_0_soft_reset(void *handle)
7669 {
7670     u32 grbm_soft_reset = 0;
7671     u32 tmp;
7672     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7673 
7674     /* GRBM_STATUS */
7675     tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7676     if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7677            GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7678            GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7679            GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7680            GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7681         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7682                         GRBM_SOFT_RESET, SOFT_RESET_CP,
7683                         1);
7684         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7685                         GRBM_SOFT_RESET, SOFT_RESET_GFX,
7686                         1);
7687     }
7688 
7689     if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7690         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7691                         GRBM_SOFT_RESET, SOFT_RESET_CP,
7692                         1);
7693     }
7694 
7695     /* GRBM_STATUS2 */
7696     tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7697     switch (adev->ip_versions[GC_HWIP][0]) {
7698     case IP_VERSION(10, 3, 0):
7699     case IP_VERSION(10, 3, 2):
7700     case IP_VERSION(10, 3, 1):
7701     case IP_VERSION(10, 3, 4):
7702     case IP_VERSION(10, 3, 5):
7703     case IP_VERSION(10, 3, 6):
7704     case IP_VERSION(10, 3, 3):
7705         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7706             grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7707                             GRBM_SOFT_RESET,
7708                             SOFT_RESET_RLC,
7709                             1);
7710         break;
7711     default:
7712         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7713             grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7714                             GRBM_SOFT_RESET,
7715                             SOFT_RESET_RLC,
7716                             1);
7717         break;
7718     }
7719 
7720     if (grbm_soft_reset) {
7721         /* stop the rlc */
7722         gfx_v10_0_rlc_stop(adev);
7723 
7724         /* Disable GFX parsing/prefetching */
7725         gfx_v10_0_cp_gfx_enable(adev, false);
7726 
7727         /* Disable MEC parsing/prefetching */
7728         gfx_v10_0_cp_compute_enable(adev, false);
7729 
7730         if (grbm_soft_reset) {
7731             tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7732             tmp |= grbm_soft_reset;
7733             dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7734             WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7735             tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7736 
7737             udelay(50);
7738 
7739             tmp &= ~grbm_soft_reset;
7740             WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7741             tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7742         }
7743 
7744         /* Wait a little for things to settle down */
7745         udelay(50);
7746     }
7747     return 0;
7748 }
7749 
7750 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7751 {
7752     uint64_t clock, clock_lo, clock_hi, hi_check;
7753 
7754     switch (adev->ip_versions[GC_HWIP][0]) {
7755     case IP_VERSION(10, 3, 1):
7756     case IP_VERSION(10, 3, 3):
7757     case IP_VERSION(10, 3, 7):
7758         preempt_disable();
7759         clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7760         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7761         hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7762         /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7763          * roughly every 42 seconds.
7764          */
7765         if (hi_check != clock_hi) {
7766             clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7767             clock_hi = hi_check;
7768         }
7769         preempt_enable();
7770         clock = clock_lo | (clock_hi << 32ULL);
7771         break;
7772     case IP_VERSION(10, 3, 6):
7773         preempt_disable();
7774         clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7775         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7776         hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7777         /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7778          * roughly every 42 seconds.
7779          */
7780         if (hi_check != clock_hi) {
7781             clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7782             clock_hi = hi_check;
7783         }
7784         preempt_enable();
7785         clock = clock_lo | (clock_hi << 32ULL);
7786         break;
7787     default:
7788         preempt_disable();
7789         clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7790         clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7791         hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7792         /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7793          * roughly every 42 seconds.
7794          */
7795         if (hi_check != clock_hi) {
7796             clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7797             clock_hi = hi_check;
7798         }
7799         preempt_enable();
7800         clock = clock_lo | (clock_hi << 32ULL);
7801         break;
7802     }
7803     return clock;
7804 }
7805 
7806 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7807                        uint32_t vmid,
7808                        uint32_t gds_base, uint32_t gds_size,
7809                        uint32_t gws_base, uint32_t gws_size,
7810                        uint32_t oa_base, uint32_t oa_size)
7811 {
7812     struct amdgpu_device *adev = ring->adev;
7813 
7814     /* GDS Base */
7815     gfx_v10_0_write_data_to_reg(ring, 0, false,
7816                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7817                     gds_base);
7818 
7819     /* GDS Size */
7820     gfx_v10_0_write_data_to_reg(ring, 0, false,
7821                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7822                     gds_size);
7823 
7824     /* GWS */
7825     gfx_v10_0_write_data_to_reg(ring, 0, false,
7826                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7827                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7828 
7829     /* OA */
7830     gfx_v10_0_write_data_to_reg(ring, 0, false,
7831                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7832                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7833 }
7834 
7835 static int gfx_v10_0_early_init(void *handle)
7836 {
7837     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7838 
7839     switch (adev->ip_versions[GC_HWIP][0]) {
7840     case IP_VERSION(10, 1, 10):
7841     case IP_VERSION(10, 1, 1):
7842     case IP_VERSION(10, 1, 2):
7843     case IP_VERSION(10, 1, 3):
7844     case IP_VERSION(10, 1, 4):
7845         adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7846         break;
7847     case IP_VERSION(10, 3, 0):
7848     case IP_VERSION(10, 3, 2):
7849     case IP_VERSION(10, 3, 1):
7850     case IP_VERSION(10, 3, 4):
7851     case IP_VERSION(10, 3, 5):
7852     case IP_VERSION(10, 3, 6):
7853     case IP_VERSION(10, 3, 3):
7854     case IP_VERSION(10, 3, 7):
7855         adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7856         break;
7857     default:
7858         break;
7859     }
7860 
7861     adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7862                       AMDGPU_MAX_COMPUTE_RINGS);
7863 
7864     gfx_v10_0_set_kiq_pm4_funcs(adev);
7865     gfx_v10_0_set_ring_funcs(adev);
7866     gfx_v10_0_set_irq_funcs(adev);
7867     gfx_v10_0_set_gds_init(adev);
7868     gfx_v10_0_set_rlc_funcs(adev);
7869     gfx_v10_0_set_mqd_funcs(adev);
7870 
7871     /* init rlcg reg access ctrl */
7872     gfx_v10_0_init_rlcg_reg_access_ctrl(adev);
7873 
7874     return 0;
7875 }
7876 
7877 static int gfx_v10_0_late_init(void *handle)
7878 {
7879     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7880     int r;
7881 
7882     r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7883     if (r)
7884         return r;
7885 
7886     r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7887     if (r)
7888         return r;
7889 
7890     return 0;
7891 }
7892 
7893 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7894 {
7895     uint32_t rlc_cntl;
7896 
7897     /* if RLC is not enabled, do nothing */
7898     rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7899     return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7900 }
7901 
7902 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7903 {
7904     uint32_t data;
7905     unsigned i;
7906 
7907     data = RLC_SAFE_MODE__CMD_MASK;
7908     data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7909 
7910     switch (adev->ip_versions[GC_HWIP][0]) {
7911     case IP_VERSION(10, 3, 0):
7912     case IP_VERSION(10, 3, 2):
7913     case IP_VERSION(10, 3, 1):
7914     case IP_VERSION(10, 3, 4):
7915     case IP_VERSION(10, 3, 5):
7916     case IP_VERSION(10, 3, 6):
7917     case IP_VERSION(10, 3, 3):
7918     case IP_VERSION(10, 3, 7):
7919         WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7920 
7921         /* wait for RLC_SAFE_MODE */
7922         for (i = 0; i < adev->usec_timeout; i++) {
7923             if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7924                        RLC_SAFE_MODE, CMD))
7925                 break;
7926             udelay(1);
7927         }
7928         break;
7929     default:
7930         WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7931 
7932         /* wait for RLC_SAFE_MODE */
7933         for (i = 0; i < adev->usec_timeout; i++) {
7934             if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7935                        RLC_SAFE_MODE, CMD))
7936                 break;
7937             udelay(1);
7938         }
7939         break;
7940     }
7941 }
7942 
7943 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7944 {
7945     uint32_t data;
7946 
7947     data = RLC_SAFE_MODE__CMD_MASK;
7948     switch (adev->ip_versions[GC_HWIP][0]) {
7949     case IP_VERSION(10, 3, 0):
7950     case IP_VERSION(10, 3, 2):
7951     case IP_VERSION(10, 3, 1):
7952     case IP_VERSION(10, 3, 4):
7953     case IP_VERSION(10, 3, 5):
7954     case IP_VERSION(10, 3, 6):
7955     case IP_VERSION(10, 3, 3):
7956     case IP_VERSION(10, 3, 7):
7957         WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7958         break;
7959     default:
7960         WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7961         break;
7962     }
7963 }
7964 
7965 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7966                               bool enable)
7967 {
7968     uint32_t data, def;
7969 
7970     if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
7971         return;
7972 
7973     /* It is disabled by HW by default */
7974     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7975         /* 0 - Disable some blocks' MGCG */
7976         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7977         WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7978         WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7979         WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7980 
7981         /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7982         def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7983         data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7984               RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7985               RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7986               RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7987               RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7988               RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7989 
7990         if (def != data)
7991             WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7992 
7993         /* MGLS is a global flag to control all MGLS in GFX */
7994         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7995             /* 2 - RLC memory Light sleep */
7996             if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7997                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7998                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7999                 if (def != data)
8000                     WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
8001             }
8002             /* 3 - CP memory Light sleep */
8003             if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
8004                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
8005                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
8006                 if (def != data)
8007                     WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
8008             }
8009         }
8010     } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
8011         /* 1 - MGCG_OVERRIDE */
8012         def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8013         data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
8014              RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
8015              RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
8016              RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
8017              RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
8018              RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
8019         if (def != data)
8020             WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8021 
8022         /* 2 - disable MGLS in CP */
8023         data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
8024         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
8025             data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
8026             WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
8027         }
8028 
8029         /* 3 - disable MGLS in RLC */
8030         data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
8031         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
8032             data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
8033             WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
8034         }
8035 
8036     }
8037 }
8038 
8039 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
8040                        bool enable)
8041 {
8042     uint32_t data, def;
8043 
8044     if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
8045         return;
8046 
8047     /* Enable 3D CGCG/CGLS */
8048     if (enable) {
8049         /* write cmd to clear cgcg/cgls ov */
8050         def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8051 
8052         /* unset CGCG override */
8053         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8054             data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
8055 
8056         /* update CGCG and CGLS override bits */
8057         if (def != data)
8058             WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8059 
8060         /* enable 3Dcgcg FSM(0x0000363f) */
8061         def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
8062         data = 0;
8063 
8064         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8065             data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
8066                 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
8067 
8068         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
8069             data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
8070                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
8071 
8072         if (def != data)
8073             WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
8074 
8075         /* set IDLE_POLL_COUNT(0x00900100) */
8076         def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
8077         data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
8078             (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
8079         if (def != data)
8080             WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8081     } else {
8082         /* Disable CGCG/CGLS */
8083         def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
8084 
8085         /* disable cgcg, cgls should be disabled */
8086         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
8087             data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
8088 
8089         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
8090             data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
8091 
8092         /* disable cgcg and cgls in FSM */
8093         if (def != data)
8094             WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
8095     }
8096 }
8097 
8098 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
8099                               bool enable)
8100 {
8101     uint32_t def, data;
8102 
8103     if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
8104         return;
8105 
8106     if (enable) {
8107         def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8108 
8109         /* unset CGCG override */
8110         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8111             data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
8112 
8113         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8114             data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
8115 
8116         /* update CGCG and CGLS override bits */
8117         if (def != data)
8118             WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8119 
8120         /* enable cgcg FSM(0x0000363F) */
8121         def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8122         data = 0;
8123 
8124         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8125             data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
8126                 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8127 
8128         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8129             data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
8130                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8131 
8132         if (def != data)
8133             WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8134 
8135         /* set IDLE_POLL_COUNT(0x00900100) */
8136         def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
8137         data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
8138             (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
8139         if (def != data)
8140             WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
8141     } else {
8142         def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
8143 
8144         /* reset CGCG/CGLS bits */
8145         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
8146             data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
8147 
8148         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
8149             data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
8150 
8151         /* disable cgcg and cgls in FSM */
8152         if (def != data)
8153             WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
8154     }
8155 }
8156 
8157 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
8158                               bool enable)
8159 {
8160     uint32_t def, data;
8161 
8162     if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
8163         return;
8164 
8165     if (enable) {
8166         def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8167         /* unset FGCG override */
8168         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8169         /* update FGCG override bits */
8170         if (def != data)
8171             WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8172 
8173         def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8174         /* unset RLC SRAM CLK GATER override */
8175         data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8176         /* update RLC SRAM CLK GATER override bits */
8177         if (def != data)
8178             WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8179     } else {
8180         def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
8181         /* reset FGCG bits */
8182         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
8183         /* disable FGCG*/
8184         if (def != data)
8185             WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
8186 
8187         def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
8188         /* reset RLC SRAM CLK GATER bits */
8189         data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
8190         /* disable RLC SRAM CLK*/
8191         if (def != data)
8192             WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
8193     }
8194 }
8195 
8196 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
8197 {
8198     uint32_t reg_data = 0;
8199     uint32_t reg_idx = 0;
8200     uint32_t i;
8201 
8202     const uint32_t tcp_ctrl_regs[] = {
8203         mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8204         mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8205         mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8206         mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8207         mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8208         mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8209         mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8210         mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8211         mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8212         mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8213         mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,
8214         mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,
8215         mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8216         mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8217         mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8218         mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8219         mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8220         mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8221         mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8222         mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8223         mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8224         mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8225         mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,
8226         mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG
8227     };
8228 
8229     const uint32_t tcp_ctrl_regs_nv12[] = {
8230         mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
8231         mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
8232         mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
8233         mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
8234         mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
8235         mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
8236         mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
8237         mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
8238         mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
8239         mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
8240         mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
8241         mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
8242         mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8243         mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8244         mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8245         mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8246         mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8247         mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8248         mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8249         mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8250     };
8251 
8252     const uint32_t sm_ctlr_regs[] = {
8253         mmCGTS_SA0_QUAD0_SM_CTRL_REG,
8254         mmCGTS_SA0_QUAD1_SM_CTRL_REG,
8255         mmCGTS_SA1_QUAD0_SM_CTRL_REG,
8256         mmCGTS_SA1_QUAD1_SM_CTRL_REG
8257     };
8258 
8259     if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
8260         for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
8261             reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8262                   tcp_ctrl_regs_nv12[i];
8263             reg_data = RREG32(reg_idx);
8264             reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8265             WREG32(reg_idx, reg_data);
8266         }
8267     } else {
8268         for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {
8269             reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8270                   tcp_ctrl_regs[i];
8271             reg_data = RREG32(reg_idx);
8272             reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8273             WREG32(reg_idx, reg_data);
8274         }
8275     }
8276 
8277     for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {
8278         reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +
8279               sm_ctlr_regs[i];
8280         reg_data = RREG32(reg_idx);
8281         reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;
8282         reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;
8283         WREG32(reg_idx, reg_data);
8284     }
8285 }
8286 
8287 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
8288                         bool enable)
8289 {
8290     amdgpu_gfx_rlc_enter_safe_mode(adev);
8291 
8292     if (enable) {
8293         /* enable FGCG firstly*/
8294         gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8295         /* CGCG/CGLS should be enabled after MGCG/MGLS
8296          * ===  MGCG + MGLS ===
8297          */
8298         gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8299         /* ===  CGCG /CGLS for GFX 3D Only === */
8300         gfx_v10_0_update_3d_clock_gating(adev, enable);
8301         /* ===  CGCG + CGLS === */
8302         gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8303 
8304         if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10)) ||
8305             (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1)) ||
8306             (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)))
8307             gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
8308     } else {
8309         /* CGCG/CGLS should be disabled before MGCG/MGLS
8310          * ===  CGCG + CGLS ===
8311          */
8312         gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8313         /* ===  CGCG /CGLS for GFX 3D Only === */
8314         gfx_v10_0_update_3d_clock_gating(adev, enable);
8315         /* ===  MGCG + MGLS === */
8316         gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8317         /* disable fgcg at last*/
8318         gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8319     }
8320 
8321     if (adev->cg_flags &
8322         (AMD_CG_SUPPORT_GFX_MGCG |
8323          AMD_CG_SUPPORT_GFX_CGLS |
8324          AMD_CG_SUPPORT_GFX_CGCG |
8325          AMD_CG_SUPPORT_GFX_3D_CGCG |
8326          AMD_CG_SUPPORT_GFX_3D_CGLS))
8327         gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
8328 
8329     amdgpu_gfx_rlc_exit_safe_mode(adev);
8330 
8331     return 0;
8332 }
8333 
8334 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
8335 {
8336     u32 reg, data;
8337 
8338     amdgpu_gfx_off_ctrl(adev, false);
8339 
8340     /* not for *_SOC15 */
8341     reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
8342     if (amdgpu_sriov_is_pp_one_vf(adev))
8343         data = RREG32_NO_KIQ(reg);
8344     else
8345         data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
8346 
8347     data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
8348     data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
8349 
8350     if (amdgpu_sriov_is_pp_one_vf(adev))
8351         WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
8352     else
8353         WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
8354 
8355     amdgpu_gfx_off_ctrl(adev, true);
8356 }
8357 
8358 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
8359                     uint32_t offset,
8360                     struct soc15_reg_rlcg *entries, int arr_size)
8361 {
8362     int i;
8363     uint32_t reg;
8364 
8365     if (!entries)
8366         return false;
8367 
8368     for (i = 0; i < arr_size; i++) {
8369         const struct soc15_reg_rlcg *entry;
8370 
8371         entry = &entries[i];
8372         reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
8373         if (offset == reg)
8374             return true;
8375     }
8376 
8377     return false;
8378 }
8379 
8380 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
8381 {
8382     return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
8383 }
8384 
8385 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
8386 {
8387     u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
8388 
8389     if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
8390         data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8391     else
8392         data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8393 
8394     WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
8395 
8396     /*
8397      * CGPG enablement required and the register to program the hysteresis value
8398      * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
8399      * in refclk count. Note that RLC FW is modified to take 16 bits from
8400      * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
8401      *
8402      * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
8403      * of CGPG enablement starting point.
8404      * Power/performance team will optimize it and might give a new value later.
8405      */
8406     if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
8407         switch (adev->ip_versions[GC_HWIP][0]) {
8408         case IP_VERSION(10, 3, 1):
8409         case IP_VERSION(10, 3, 3):
8410         case IP_VERSION(10, 3, 6):
8411         case IP_VERSION(10, 3, 7):
8412             data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8413             WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8414             break;
8415         default:
8416             break;
8417         }
8418     }
8419 }
8420 
8421 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
8422 {
8423     amdgpu_gfx_rlc_enter_safe_mode(adev);
8424 
8425     gfx_v10_cntl_power_gating(adev, enable);
8426 
8427     amdgpu_gfx_rlc_exit_safe_mode(adev);
8428 }
8429 
8430 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8431     .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8432     .set_safe_mode = gfx_v10_0_set_safe_mode,
8433     .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8434     .init = gfx_v10_0_rlc_init,
8435     .get_csb_size = gfx_v10_0_get_csb_size,
8436     .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8437     .resume = gfx_v10_0_rlc_resume,
8438     .stop = gfx_v10_0_rlc_stop,
8439     .reset = gfx_v10_0_rlc_reset,
8440     .start = gfx_v10_0_rlc_start,
8441     .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8442 };
8443 
8444 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8445     .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8446     .set_safe_mode = gfx_v10_0_set_safe_mode,
8447     .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8448     .init = gfx_v10_0_rlc_init,
8449     .get_csb_size = gfx_v10_0_get_csb_size,
8450     .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8451     .resume = gfx_v10_0_rlc_resume,
8452     .stop = gfx_v10_0_rlc_stop,
8453     .reset = gfx_v10_0_rlc_reset,
8454     .start = gfx_v10_0_rlc_start,
8455     .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8456     .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8457 };
8458 
8459 static int gfx_v10_0_set_powergating_state(void *handle,
8460                       enum amd_powergating_state state)
8461 {
8462     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8463     bool enable = (state == AMD_PG_STATE_GATE);
8464 
8465     if (amdgpu_sriov_vf(adev))
8466         return 0;
8467 
8468     switch (adev->ip_versions[GC_HWIP][0]) {
8469     case IP_VERSION(10, 1, 10):
8470     case IP_VERSION(10, 1, 1):
8471     case IP_VERSION(10, 1, 2):
8472     case IP_VERSION(10, 3, 0):
8473     case IP_VERSION(10, 3, 2):
8474     case IP_VERSION(10, 3, 4):
8475     case IP_VERSION(10, 3, 5):
8476         amdgpu_gfx_off_ctrl(adev, enable);
8477         break;
8478     case IP_VERSION(10, 3, 1):
8479     case IP_VERSION(10, 3, 3):
8480     case IP_VERSION(10, 3, 6):
8481     case IP_VERSION(10, 3, 7):
8482         gfx_v10_cntl_pg(adev, enable);
8483         amdgpu_gfx_off_ctrl(adev, enable);
8484         break;
8485     default:
8486         break;
8487     }
8488     return 0;
8489 }
8490 
8491 static int gfx_v10_0_set_clockgating_state(void *handle,
8492                       enum amd_clockgating_state state)
8493 {
8494     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8495 
8496     if (amdgpu_sriov_vf(adev))
8497         return 0;
8498 
8499     switch (adev->ip_versions[GC_HWIP][0]) {
8500     case IP_VERSION(10, 1, 10):
8501     case IP_VERSION(10, 1, 1):
8502     case IP_VERSION(10, 1, 2):
8503     case IP_VERSION(10, 3, 0):
8504     case IP_VERSION(10, 3, 2):
8505     case IP_VERSION(10, 3, 1):
8506     case IP_VERSION(10, 3, 4):
8507     case IP_VERSION(10, 3, 5):
8508     case IP_VERSION(10, 3, 6):
8509     case IP_VERSION(10, 3, 3):
8510     case IP_VERSION(10, 3, 7):
8511         gfx_v10_0_update_gfx_clock_gating(adev,
8512                          state == AMD_CG_STATE_GATE);
8513         break;
8514     default:
8515         break;
8516     }
8517     return 0;
8518 }
8519 
8520 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags)
8521 {
8522     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8523     int data;
8524 
8525     /* AMD_CG_SUPPORT_GFX_FGCG */
8526     data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8527     if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8528         *flags |= AMD_CG_SUPPORT_GFX_FGCG;
8529 
8530     /* AMD_CG_SUPPORT_GFX_MGCG */
8531     data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8532     if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8533         *flags |= AMD_CG_SUPPORT_GFX_MGCG;
8534 
8535     /* AMD_CG_SUPPORT_GFX_CGCG */
8536     data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8537     if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8538         *flags |= AMD_CG_SUPPORT_GFX_CGCG;
8539 
8540     /* AMD_CG_SUPPORT_GFX_CGLS */
8541     if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8542         *flags |= AMD_CG_SUPPORT_GFX_CGLS;
8543 
8544     /* AMD_CG_SUPPORT_GFX_RLC_LS */
8545     data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8546     if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8547         *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8548 
8549     /* AMD_CG_SUPPORT_GFX_CP_LS */
8550     data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8551     if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8552         *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8553 
8554     /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8555     data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8556     if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8557         *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8558 
8559     /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8560     if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8561         *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8562 }
8563 
8564 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8565 {
8566     /* gfx10 is 32bit rptr*/
8567     return *(uint32_t *)ring->rptr_cpu_addr;
8568 }
8569 
8570 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8571 {
8572     struct amdgpu_device *adev = ring->adev;
8573     u64 wptr;
8574 
8575     /* XXX check if swapping is necessary on BE */
8576     if (ring->use_doorbell) {
8577         wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8578     } else {
8579         wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8580         wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8581     }
8582 
8583     return wptr;
8584 }
8585 
8586 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8587 {
8588     struct amdgpu_device *adev = ring->adev;
8589     uint32_t *wptr_saved;
8590     uint32_t *is_queue_unmap;
8591     uint64_t aggregated_db_index;
8592     uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size;
8593     uint64_t wptr_tmp;
8594 
8595     if (ring->is_mes_queue) {
8596         wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
8597         is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
8598                           sizeof(uint32_t));
8599         aggregated_db_index =
8600             amdgpu_mes_get_aggregated_doorbell_index(adev,
8601             AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
8602 
8603         wptr_tmp = ring->wptr & ring->buf_mask;
8604         atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
8605         *wptr_saved = wptr_tmp;
8606         /* assume doorbell always being used by mes mapped queue */
8607         if (*is_queue_unmap) {
8608             WDOORBELL64(aggregated_db_index, wptr_tmp);
8609             WDOORBELL64(ring->doorbell_index, wptr_tmp);
8610         } else {
8611             WDOORBELL64(ring->doorbell_index, wptr_tmp);
8612 
8613             if (*is_queue_unmap)
8614                 WDOORBELL64(aggregated_db_index, wptr_tmp);
8615         }
8616     } else {
8617         if (ring->use_doorbell) {
8618             /* XXX check if swapping is necessary on BE */
8619             atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8620                      ring->wptr);
8621             WDOORBELL64(ring->doorbell_index, ring->wptr);
8622         } else {
8623             WREG32_SOC15(GC, 0, mmCP_RB0_WPTR,
8624                      lower_32_bits(ring->wptr));
8625             WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI,
8626                      upper_32_bits(ring->wptr));
8627         }
8628     }
8629 }
8630 
8631 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8632 {
8633     /* gfx10 hardware is 32bit rptr */
8634     return *(uint32_t *)ring->rptr_cpu_addr;
8635 }
8636 
8637 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8638 {
8639     u64 wptr;
8640 
8641     /* XXX check if swapping is necessary on BE */
8642     if (ring->use_doorbell)
8643         wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8644     else
8645         BUG();
8646     return wptr;
8647 }
8648 
8649 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8650 {
8651     struct amdgpu_device *adev = ring->adev;
8652     uint32_t *wptr_saved;
8653     uint32_t *is_queue_unmap;
8654     uint64_t aggregated_db_index;
8655     uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size;
8656     uint64_t wptr_tmp;
8657 
8658     if (ring->is_mes_queue) {
8659         wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
8660         is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
8661                           sizeof(uint32_t));
8662         aggregated_db_index =
8663             amdgpu_mes_get_aggregated_doorbell_index(adev,
8664             AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
8665 
8666         wptr_tmp = ring->wptr & ring->buf_mask;
8667         atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
8668         *wptr_saved = wptr_tmp;
8669         /* assume doorbell always used by mes mapped queue */
8670         if (*is_queue_unmap) {
8671             WDOORBELL64(aggregated_db_index, wptr_tmp);
8672             WDOORBELL64(ring->doorbell_index, wptr_tmp);
8673         } else {
8674             WDOORBELL64(ring->doorbell_index, wptr_tmp);
8675 
8676             if (*is_queue_unmap)
8677                 WDOORBELL64(aggregated_db_index, wptr_tmp);
8678         }
8679     } else {
8680         /* XXX check if swapping is necessary on BE */
8681         if (ring->use_doorbell) {
8682             atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8683                      ring->wptr);
8684             WDOORBELL64(ring->doorbell_index, ring->wptr);
8685         } else {
8686             BUG(); /* only DOORBELL method supported on gfx10 now */
8687         }
8688     }
8689 }
8690 
8691 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8692 {
8693     struct amdgpu_device *adev = ring->adev;
8694     u32 ref_and_mask, reg_mem_engine;
8695     const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8696 
8697     if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8698         switch (ring->me) {
8699         case 1:
8700             ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8701             break;
8702         case 2:
8703             ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8704             break;
8705         default:
8706             return;
8707         }
8708         reg_mem_engine = 0;
8709     } else {
8710         ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8711         reg_mem_engine = 1; /* pfp */
8712     }
8713 
8714     gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8715                    adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8716                    adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8717                    ref_and_mask, ref_and_mask, 0x20);
8718 }
8719 
8720 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8721                        struct amdgpu_job *job,
8722                        struct amdgpu_ib *ib,
8723                        uint32_t flags)
8724 {
8725     unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8726     u32 header, control = 0;
8727 
8728     if (ib->flags & AMDGPU_IB_FLAG_CE)
8729         header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8730     else
8731         header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8732 
8733     control |= ib->length_dw | (vmid << 24);
8734 
8735     if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8736         control |= INDIRECT_BUFFER_PRE_ENB(1);
8737 
8738         if (flags & AMDGPU_IB_PREEMPTED)
8739             control |= INDIRECT_BUFFER_PRE_RESUME(1);
8740 
8741         if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8742             gfx_v10_0_ring_emit_de_meta(ring,
8743                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8744     }
8745 
8746     if (ring->is_mes_queue)
8747         /* inherit vmid from mqd */
8748         control |= 0x400000;
8749 
8750     amdgpu_ring_write(ring, header);
8751     BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8752     amdgpu_ring_write(ring,
8753 #ifdef __BIG_ENDIAN
8754         (2 << 0) |
8755 #endif
8756         lower_32_bits(ib->gpu_addr));
8757     amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8758     amdgpu_ring_write(ring, control);
8759 }
8760 
8761 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8762                        struct amdgpu_job *job,
8763                        struct amdgpu_ib *ib,
8764                        uint32_t flags)
8765 {
8766     unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8767     u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8768 
8769     if (ring->is_mes_queue)
8770         /* inherit vmid from mqd */
8771         control |= 0x40000000;
8772 
8773     /* Currently, there is a high possibility to get wave ID mismatch
8774      * between ME and GDS, leading to a hw deadlock, because ME generates
8775      * different wave IDs than the GDS expects. This situation happens
8776      * randomly when at least 5 compute pipes use GDS ordered append.
8777      * The wave IDs generated by ME are also wrong after suspend/resume.
8778      * Those are probably bugs somewhere else in the kernel driver.
8779      *
8780      * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8781      * GDS to 0 for this ring (me/pipe).
8782      */
8783     if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8784         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8785         amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8786         amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8787     }
8788 
8789     amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8790     BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8791     amdgpu_ring_write(ring,
8792 #ifdef __BIG_ENDIAN
8793                 (2 << 0) |
8794 #endif
8795                 lower_32_bits(ib->gpu_addr));
8796     amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8797     amdgpu_ring_write(ring, control);
8798 }
8799 
8800 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8801                      u64 seq, unsigned flags)
8802 {
8803     bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8804     bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8805 
8806     /* RELEASE_MEM - flush caches, send int */
8807     amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8808     amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8809                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
8810                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8811                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
8812                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8813                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8814                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8815     amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8816                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8817 
8818     /*
8819      * the address should be Qword aligned if 64bit write, Dword
8820      * aligned if only send 32bit data low (discard data high)
8821      */
8822     if (write64bit)
8823         BUG_ON(addr & 0x7);
8824     else
8825         BUG_ON(addr & 0x3);
8826     amdgpu_ring_write(ring, lower_32_bits(addr));
8827     amdgpu_ring_write(ring, upper_32_bits(addr));
8828     amdgpu_ring_write(ring, lower_32_bits(seq));
8829     amdgpu_ring_write(ring, upper_32_bits(seq));
8830     amdgpu_ring_write(ring, ring->is_mes_queue ?
8831              (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);
8832 }
8833 
8834 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8835 {
8836     int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8837     uint32_t seq = ring->fence_drv.sync_seq;
8838     uint64_t addr = ring->fence_drv.gpu_addr;
8839 
8840     gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8841                    upper_32_bits(addr), seq, 0xffffffff, 4);
8842 }
8843 
8844 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
8845                    uint16_t pasid, uint32_t flush_type,
8846                    bool all_hub, uint8_t dst_sel)
8847 {
8848     amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
8849     amdgpu_ring_write(ring,
8850               PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
8851               PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
8852               PACKET3_INVALIDATE_TLBS_PASID(pasid) |
8853               PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
8854 }
8855 
8856 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8857                      unsigned vmid, uint64_t pd_addr)
8858 {
8859     if (ring->is_mes_queue)
8860         gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);
8861     else
8862         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8863 
8864     /* compute doesn't have PFP */
8865     if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8866         /* sync PFP to ME, otherwise we might get invalid PFP reads */
8867         amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8868         amdgpu_ring_write(ring, 0x0);
8869     }
8870 }
8871 
8872 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8873                       u64 seq, unsigned int flags)
8874 {
8875     struct amdgpu_device *adev = ring->adev;
8876 
8877     /* we only allocate 32bit for each seq wb address */
8878     BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8879 
8880     /* write fence seq to the "addr" */
8881     amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8882     amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8883                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8884     amdgpu_ring_write(ring, lower_32_bits(addr));
8885     amdgpu_ring_write(ring, upper_32_bits(addr));
8886     amdgpu_ring_write(ring, lower_32_bits(seq));
8887 
8888     if (flags & AMDGPU_FENCE_FLAG_INT) {
8889         /* set register to trigger INT */
8890         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8891         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8892                      WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8893         amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8894         amdgpu_ring_write(ring, 0);
8895         amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8896     }
8897 }
8898 
8899 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8900 {
8901     amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8902     amdgpu_ring_write(ring, 0);
8903 }
8904 
8905 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8906                      uint32_t flags)
8907 {
8908     uint32_t dw2 = 0;
8909 
8910     if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
8911         gfx_v10_0_ring_emit_ce_meta(ring,
8912                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8913 
8914     dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8915     if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8916         /* set load_global_config & load_global_uconfig */
8917         dw2 |= 0x8001;
8918         /* set load_cs_sh_regs */
8919         dw2 |= 0x01000000;
8920         /* set load_per_context_state & load_gfx_sh_regs for GFX */
8921         dw2 |= 0x10002;
8922 
8923         /* set load_ce_ram if preamble presented */
8924         if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8925             dw2 |= 0x10000000;
8926     } else {
8927         /* still load_ce_ram if this is the first time preamble presented
8928          * although there is no context switch happens.
8929          */
8930         if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8931             dw2 |= 0x10000000;
8932     }
8933 
8934     amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8935     amdgpu_ring_write(ring, dw2);
8936     amdgpu_ring_write(ring, 0);
8937 }
8938 
8939 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8940 {
8941     unsigned ret;
8942 
8943     amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8944     amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8945     amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8946     amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8947     ret = ring->wptr & ring->buf_mask;
8948     amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8949 
8950     return ret;
8951 }
8952 
8953 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8954 {
8955     unsigned cur;
8956     BUG_ON(offset > ring->buf_mask);
8957     BUG_ON(ring->ring[offset] != 0x55aa55aa);
8958 
8959     cur = (ring->wptr - 1) & ring->buf_mask;
8960     if (likely(cur > offset))
8961         ring->ring[offset] = cur - offset;
8962     else
8963         ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8964 }
8965 
8966 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8967 {
8968     int i, r = 0;
8969     struct amdgpu_device *adev = ring->adev;
8970     struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8971     struct amdgpu_ring *kiq_ring = &kiq->ring;
8972     unsigned long flags;
8973 
8974     if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8975         return -EINVAL;
8976 
8977     spin_lock_irqsave(&kiq->ring_lock, flags);
8978 
8979     if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8980         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8981         return -ENOMEM;
8982     }
8983 
8984     /* assert preemption condition */
8985     amdgpu_ring_set_preempt_cond_exec(ring, false);
8986 
8987     /* assert IB preemption, emit the trailing fence */
8988     kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8989                    ring->trail_fence_gpu_addr,
8990                    ++ring->trail_seq);
8991     amdgpu_ring_commit(kiq_ring);
8992 
8993     spin_unlock_irqrestore(&kiq->ring_lock, flags);
8994 
8995     /* poll the trailing fence */
8996     for (i = 0; i < adev->usec_timeout; i++) {
8997         if (ring->trail_seq ==
8998             le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8999             break;
9000         udelay(1);
9001     }
9002 
9003     if (i >= adev->usec_timeout) {
9004         r = -EINVAL;
9005         DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
9006     }
9007 
9008     /* deassert preemption condition */
9009     amdgpu_ring_set_preempt_cond_exec(ring, true);
9010     return r;
9011 }
9012 
9013 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
9014 {
9015     struct amdgpu_device *adev = ring->adev;
9016     struct v10_ce_ib_state ce_payload = {0};
9017     uint64_t offset, ce_payload_gpu_addr;
9018     void *ce_payload_cpu_addr;
9019     int cnt;
9020 
9021     cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
9022 
9023     if (ring->is_mes_queue) {
9024         offset = offsetof(struct amdgpu_mes_ctx_meta_data,
9025                   gfx[0].gfx_meta_data) +
9026             offsetof(struct v10_gfx_meta_data, ce_payload);
9027         ce_payload_gpu_addr =
9028             amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
9029         ce_payload_cpu_addr =
9030             amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
9031     } else {
9032         offset = offsetof(struct v10_gfx_meta_data, ce_payload);
9033         ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
9034         ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
9035     }
9036 
9037     amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
9038     amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
9039                  WRITE_DATA_DST_SEL(8) |
9040                  WR_CONFIRM) |
9041                  WRITE_DATA_CACHE_POLICY(0));
9042     amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
9043     amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));
9044 
9045     if (resume)
9046         amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,
9047                        sizeof(ce_payload) >> 2);
9048     else
9049         amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
9050                        sizeof(ce_payload) >> 2);
9051 }
9052 
9053 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
9054 {
9055     struct amdgpu_device *adev = ring->adev;
9056     struct v10_de_ib_state de_payload = {0};
9057     uint64_t offset, gds_addr, de_payload_gpu_addr;
9058     void *de_payload_cpu_addr;
9059     int cnt;
9060 
9061     if (ring->is_mes_queue) {
9062         offset = offsetof(struct amdgpu_mes_ctx_meta_data,
9063                   gfx[0].gfx_meta_data) +
9064             offsetof(struct v10_gfx_meta_data, de_payload);
9065         de_payload_gpu_addr =
9066             amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
9067         de_payload_cpu_addr =
9068             amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
9069 
9070         offset = offsetof(struct amdgpu_mes_ctx_meta_data,
9071                   gfx[0].gds_backup) +
9072             offsetof(struct v10_gfx_meta_data, de_payload);
9073         gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
9074     } else {
9075         offset = offsetof(struct v10_gfx_meta_data, de_payload);
9076         de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
9077         de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
9078 
9079         gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
9080                  AMDGPU_CSA_SIZE - adev->gds.gds_size,
9081                  PAGE_SIZE);
9082     }
9083 
9084     de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
9085     de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
9086 
9087     cnt = (sizeof(de_payload) >> 2) + 4 - 2;
9088     amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
9089     amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
9090                  WRITE_DATA_DST_SEL(8) |
9091                  WR_CONFIRM) |
9092                  WRITE_DATA_CACHE_POLICY(0));
9093     amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
9094     amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
9095 
9096     if (resume)
9097         amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
9098                        sizeof(de_payload) >> 2);
9099     else
9100         amdgpu_ring_write_multiple(ring, (void *)&de_payload,
9101                        sizeof(de_payload) >> 2);
9102 }
9103 
9104 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
9105                     bool secure)
9106 {
9107     uint32_t v = secure ? FRAME_TMZ : 0;
9108 
9109     amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
9110     amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
9111 }
9112 
9113 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
9114                      uint32_t reg_val_offs)
9115 {
9116     struct amdgpu_device *adev = ring->adev;
9117 
9118     amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
9119     amdgpu_ring_write(ring, 0 | /* src: register*/
9120                 (5 << 8) |  /* dst: memory */
9121                 (1 << 20)); /* write confirm */
9122     amdgpu_ring_write(ring, reg);
9123     amdgpu_ring_write(ring, 0);
9124     amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
9125                 reg_val_offs * 4));
9126     amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
9127                 reg_val_offs * 4));
9128 }
9129 
9130 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
9131                    uint32_t val)
9132 {
9133     uint32_t cmd = 0;
9134 
9135     switch (ring->funcs->type) {
9136     case AMDGPU_RING_TYPE_GFX:
9137         cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
9138         break;
9139     case AMDGPU_RING_TYPE_KIQ:
9140         cmd = (1 << 16); /* no inc addr */
9141         break;
9142     default:
9143         cmd = WR_CONFIRM;
9144         break;
9145     }
9146     amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
9147     amdgpu_ring_write(ring, cmd);
9148     amdgpu_ring_write(ring, reg);
9149     amdgpu_ring_write(ring, 0);
9150     amdgpu_ring_write(ring, val);
9151 }
9152 
9153 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
9154                     uint32_t val, uint32_t mask)
9155 {
9156     gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
9157 }
9158 
9159 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
9160                            uint32_t reg0, uint32_t reg1,
9161                            uint32_t ref, uint32_t mask)
9162 {
9163     int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
9164     struct amdgpu_device *adev = ring->adev;
9165     bool fw_version_ok = false;
9166 
9167     fw_version_ok = adev->gfx.cp_fw_write_wait;
9168 
9169     if (fw_version_ok)
9170         gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
9171                        ref, mask, 0x20);
9172     else
9173         amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
9174                                ref, mask);
9175 }
9176 
9177 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
9178                      unsigned vmid)
9179 {
9180     struct amdgpu_device *adev = ring->adev;
9181     uint32_t value = 0;
9182 
9183     value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
9184     value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
9185     value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
9186     value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
9187     WREG32_SOC15(GC, 0, mmSQ_CMD, value);
9188 }
9189 
9190 static void
9191 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
9192                       uint32_t me, uint32_t pipe,
9193                       enum amdgpu_interrupt_state state)
9194 {
9195     uint32_t cp_int_cntl, cp_int_cntl_reg;
9196 
9197     if (!me) {
9198         switch (pipe) {
9199         case 0:
9200             cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
9201             break;
9202         case 1:
9203             cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
9204             break;
9205         default:
9206             DRM_DEBUG("invalid pipe %d\n", pipe);
9207             return;
9208         }
9209     } else {
9210         DRM_DEBUG("invalid me %d\n", me);
9211         return;
9212     }
9213 
9214     switch (state) {
9215     case AMDGPU_IRQ_STATE_DISABLE:
9216         cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9217         cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9218                         TIME_STAMP_INT_ENABLE, 0);
9219         WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9220         break;
9221     case AMDGPU_IRQ_STATE_ENABLE:
9222         cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
9223         cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
9224                         TIME_STAMP_INT_ENABLE, 1);
9225         WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
9226         break;
9227     default:
9228         break;
9229     }
9230 }
9231 
9232 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
9233                              int me, int pipe,
9234                              enum amdgpu_interrupt_state state)
9235 {
9236     u32 mec_int_cntl, mec_int_cntl_reg;
9237 
9238     /*
9239      * amdgpu controls only the first MEC. That's why this function only
9240      * handles the setting of interrupts for this specific MEC. All other
9241      * pipes' interrupts are set by amdkfd.
9242      */
9243 
9244     if (me == 1) {
9245         switch (pipe) {
9246         case 0:
9247             mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9248             break;
9249         case 1:
9250             mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
9251             break;
9252         case 2:
9253             mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
9254             break;
9255         case 3:
9256             mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
9257             break;
9258         default:
9259             DRM_DEBUG("invalid pipe %d\n", pipe);
9260             return;
9261         }
9262     } else {
9263         DRM_DEBUG("invalid me %d\n", me);
9264         return;
9265     }
9266 
9267     switch (state) {
9268     case AMDGPU_IRQ_STATE_DISABLE:
9269         mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9270         mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9271                          TIME_STAMP_INT_ENABLE, 0);
9272         WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9273         break;
9274     case AMDGPU_IRQ_STATE_ENABLE:
9275         mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9276         mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9277                          TIME_STAMP_INT_ENABLE, 1);
9278         WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9279         break;
9280     default:
9281         break;
9282     }
9283 }
9284 
9285 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
9286                         struct amdgpu_irq_src *src,
9287                         unsigned type,
9288                         enum amdgpu_interrupt_state state)
9289 {
9290     switch (type) {
9291     case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
9292         gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
9293         break;
9294     case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
9295         gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
9296         break;
9297     case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
9298         gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
9299         break;
9300     case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
9301         gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
9302         break;
9303     case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
9304         gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
9305         break;
9306     case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
9307         gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
9308         break;
9309     case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
9310         gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
9311         break;
9312     case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
9313         gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
9314         break;
9315     case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
9316         gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
9317         break;
9318     case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
9319         gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
9320         break;
9321     default:
9322         break;
9323     }
9324     return 0;
9325 }
9326 
9327 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
9328                  struct amdgpu_irq_src *source,
9329                  struct amdgpu_iv_entry *entry)
9330 {
9331     int i;
9332     u8 me_id, pipe_id, queue_id;
9333     struct amdgpu_ring *ring;
9334     uint32_t mes_queue_id = entry->src_data[0];
9335 
9336     DRM_DEBUG("IH: CP EOP\n");
9337 
9338     if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
9339         struct amdgpu_mes_queue *queue;
9340 
9341         mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
9342 
9343         spin_lock(&adev->mes.queue_id_lock);
9344         queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
9345         if (queue) {
9346             DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);
9347             amdgpu_fence_process(queue->ring);
9348         }
9349         spin_unlock(&adev->mes.queue_id_lock);
9350     } else {
9351         me_id = (entry->ring_id & 0x0c) >> 2;
9352         pipe_id = (entry->ring_id & 0x03) >> 0;
9353         queue_id = (entry->ring_id & 0x70) >> 4;
9354 
9355         switch (me_id) {
9356         case 0:
9357             if (pipe_id == 0)
9358                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
9359             else
9360                 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
9361             break;
9362         case 1:
9363         case 2:
9364             for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9365                 ring = &adev->gfx.compute_ring[i];
9366                 /* Per-queue interrupt is supported for MEC starting from VI.
9367                  * The interrupt can only be enabled/disabled per pipe instead
9368                  * of per queue.
9369                  */
9370                 if ((ring->me == me_id) &&
9371                     (ring->pipe == pipe_id) &&
9372                     (ring->queue == queue_id))
9373                     amdgpu_fence_process(ring);
9374             }
9375             break;
9376         }
9377     }
9378 
9379     return 0;
9380 }
9381 
9382 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
9383                           struct amdgpu_irq_src *source,
9384                           unsigned type,
9385                           enum amdgpu_interrupt_state state)
9386 {
9387     switch (state) {
9388     case AMDGPU_IRQ_STATE_DISABLE:
9389     case AMDGPU_IRQ_STATE_ENABLE:
9390         WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9391                    PRIV_REG_INT_ENABLE,
9392                    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9393         break;
9394     default:
9395         break;
9396     }
9397 
9398     return 0;
9399 }
9400 
9401 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
9402                            struct amdgpu_irq_src *source,
9403                            unsigned type,
9404                            enum amdgpu_interrupt_state state)
9405 {
9406     switch (state) {
9407     case AMDGPU_IRQ_STATE_DISABLE:
9408     case AMDGPU_IRQ_STATE_ENABLE:
9409         WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9410                    PRIV_INSTR_INT_ENABLE,
9411                    state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9412         break;
9413     default:
9414         break;
9415     }
9416 
9417     return 0;
9418 }
9419 
9420 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
9421                     struct amdgpu_iv_entry *entry)
9422 {
9423     u8 me_id, pipe_id, queue_id;
9424     struct amdgpu_ring *ring;
9425     int i;
9426 
9427     me_id = (entry->ring_id & 0x0c) >> 2;
9428     pipe_id = (entry->ring_id & 0x03) >> 0;
9429     queue_id = (entry->ring_id & 0x70) >> 4;
9430 
9431     switch (me_id) {
9432     case 0:
9433         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9434             ring = &adev->gfx.gfx_ring[i];
9435             /* we only enabled 1 gfx queue per pipe for now */
9436             if (ring->me == me_id && ring->pipe == pipe_id)
9437                 drm_sched_fault(&ring->sched);
9438         }
9439         break;
9440     case 1:
9441     case 2:
9442         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9443             ring = &adev->gfx.compute_ring[i];
9444             if (ring->me == me_id && ring->pipe == pipe_id &&
9445                 ring->queue == queue_id)
9446                 drm_sched_fault(&ring->sched);
9447         }
9448         break;
9449     default:
9450         BUG();
9451     }
9452 }
9453 
9454 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
9455                   struct amdgpu_irq_src *source,
9456                   struct amdgpu_iv_entry *entry)
9457 {
9458     DRM_ERROR("Illegal register access in command stream\n");
9459     gfx_v10_0_handle_priv_fault(adev, entry);
9460     return 0;
9461 }
9462 
9463 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
9464                    struct amdgpu_irq_src *source,
9465                    struct amdgpu_iv_entry *entry)
9466 {
9467     DRM_ERROR("Illegal instruction in command stream\n");
9468     gfx_v10_0_handle_priv_fault(adev, entry);
9469     return 0;
9470 }
9471 
9472 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
9473                          struct amdgpu_irq_src *src,
9474                          unsigned int type,
9475                          enum amdgpu_interrupt_state state)
9476 {
9477     uint32_t tmp, target;
9478     struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
9479 
9480     if (ring->me == 1)
9481         target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9482     else
9483         target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
9484     target += ring->pipe;
9485 
9486     switch (type) {
9487     case AMDGPU_CP_KIQ_IRQ_DRIVER0:
9488         if (state == AMDGPU_IRQ_STATE_DISABLE) {
9489             tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9490             tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9491                         GENERIC2_INT_ENABLE, 0);
9492             WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9493 
9494             tmp = RREG32_SOC15_IP(GC, target);
9495             tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9496                         GENERIC2_INT_ENABLE, 0);
9497             WREG32_SOC15_IP(GC, target, tmp);
9498         } else {
9499             tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9500             tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9501                         GENERIC2_INT_ENABLE, 1);
9502             WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9503 
9504             tmp = RREG32_SOC15_IP(GC, target);
9505             tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9506                         GENERIC2_INT_ENABLE, 1);
9507             WREG32_SOC15_IP(GC, target, tmp);
9508         }
9509         break;
9510     default:
9511         BUG(); /* kiq only support GENERIC2_INT now */
9512         break;
9513     }
9514     return 0;
9515 }
9516 
9517 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
9518                  struct amdgpu_irq_src *source,
9519                  struct amdgpu_iv_entry *entry)
9520 {
9521     u8 me_id, pipe_id, queue_id;
9522     struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
9523 
9524     me_id = (entry->ring_id & 0x0c) >> 2;
9525     pipe_id = (entry->ring_id & 0x03) >> 0;
9526     queue_id = (entry->ring_id & 0x70) >> 4;
9527     DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
9528            me_id, pipe_id, queue_id);
9529 
9530     amdgpu_fence_process(ring);
9531     return 0;
9532 }
9533 
9534 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
9535 {
9536     const unsigned int gcr_cntl =
9537             PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
9538             PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
9539             PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
9540             PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
9541             PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
9542             PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
9543             PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
9544             PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
9545 
9546     /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
9547     amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
9548     amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
9549     amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
9550     amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
9551     amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9552     amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
9553     amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9554     amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9555 }
9556 
9557 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9558     .name = "gfx_v10_0",
9559     .early_init = gfx_v10_0_early_init,
9560     .late_init = gfx_v10_0_late_init,
9561     .sw_init = gfx_v10_0_sw_init,
9562     .sw_fini = gfx_v10_0_sw_fini,
9563     .hw_init = gfx_v10_0_hw_init,
9564     .hw_fini = gfx_v10_0_hw_fini,
9565     .suspend = gfx_v10_0_suspend,
9566     .resume = gfx_v10_0_resume,
9567     .is_idle = gfx_v10_0_is_idle,
9568     .wait_for_idle = gfx_v10_0_wait_for_idle,
9569     .soft_reset = gfx_v10_0_soft_reset,
9570     .set_clockgating_state = gfx_v10_0_set_clockgating_state,
9571     .set_powergating_state = gfx_v10_0_set_powergating_state,
9572     .get_clockgating_state = gfx_v10_0_get_clockgating_state,
9573 };
9574 
9575 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9576     .type = AMDGPU_RING_TYPE_GFX,
9577     .align_mask = 0xff,
9578     .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9579     .support_64bit_ptrs = true,
9580     .secure_submission_supported = true,
9581     .vmhub = AMDGPU_GFXHUB_0,
9582     .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9583     .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9584     .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9585     .emit_frame_size = /* totally 242 maximum if 16 IBs */
9586         5 + /* COND_EXEC */
9587         7 + /* PIPELINE_SYNC */
9588         SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9589         SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9590         2 + /* VM_FLUSH */
9591         8 + /* FENCE for VM_FLUSH */
9592         20 + /* GDS switch */
9593         4 + /* double SWITCH_BUFFER,
9594              * the first COND_EXEC jump to the place
9595              * just prior to this double SWITCH_BUFFER
9596              */
9597         5 + /* COND_EXEC */
9598         7 + /* HDP_flush */
9599         4 + /* VGT_flush */
9600         14 + /* CE_META */
9601         31 + /* DE_META */
9602         3 + /* CNTX_CTRL */
9603         5 + /* HDP_INVL */
9604         8 + 8 + /* FENCE x2 */
9605         2 + /* SWITCH_BUFFER */
9606         8, /* gfx_v10_0_emit_mem_sync */
9607     .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
9608     .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9609     .emit_fence = gfx_v10_0_ring_emit_fence,
9610     .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9611     .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9612     .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9613     .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9614     .test_ring = gfx_v10_0_ring_test_ring,
9615     .test_ib = gfx_v10_0_ring_test_ib,
9616     .insert_nop = amdgpu_ring_insert_nop,
9617     .pad_ib = amdgpu_ring_generic_pad_ib,
9618     .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9619     .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9620     .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9621     .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
9622     .preempt_ib = gfx_v10_0_ring_preempt_ib,
9623     .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9624     .emit_wreg = gfx_v10_0_ring_emit_wreg,
9625     .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9626     .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9627     .soft_recovery = gfx_v10_0_ring_soft_recovery,
9628     .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9629 };
9630 
9631 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9632     .type = AMDGPU_RING_TYPE_COMPUTE,
9633     .align_mask = 0xff,
9634     .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9635     .support_64bit_ptrs = true,
9636     .vmhub = AMDGPU_GFXHUB_0,
9637     .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9638     .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9639     .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9640     .emit_frame_size =
9641         20 + /* gfx_v10_0_ring_emit_gds_switch */
9642         7 + /* gfx_v10_0_ring_emit_hdp_flush */
9643         5 + /* hdp invalidate */
9644         7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9645         SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9646         SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9647         2 + /* gfx_v10_0_ring_emit_vm_flush */
9648         8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9649         8, /* gfx_v10_0_emit_mem_sync */
9650     .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9651     .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9652     .emit_fence = gfx_v10_0_ring_emit_fence,
9653     .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9654     .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9655     .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9656     .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9657     .test_ring = gfx_v10_0_ring_test_ring,
9658     .test_ib = gfx_v10_0_ring_test_ib,
9659     .insert_nop = amdgpu_ring_insert_nop,
9660     .pad_ib = amdgpu_ring_generic_pad_ib,
9661     .emit_wreg = gfx_v10_0_ring_emit_wreg,
9662     .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9663     .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9664     .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9665 };
9666 
9667 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9668     .type = AMDGPU_RING_TYPE_KIQ,
9669     .align_mask = 0xff,
9670     .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9671     .support_64bit_ptrs = true,
9672     .vmhub = AMDGPU_GFXHUB_0,
9673     .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9674     .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9675     .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9676     .emit_frame_size =
9677         20 + /* gfx_v10_0_ring_emit_gds_switch */
9678         7 + /* gfx_v10_0_ring_emit_hdp_flush */
9679         5 + /*hdp invalidate */
9680         7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9681         SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9682         SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9683         2 + /* gfx_v10_0_ring_emit_vm_flush */
9684         8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9685     .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9686     .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9687     .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9688     .test_ring = gfx_v10_0_ring_test_ring,
9689     .test_ib = gfx_v10_0_ring_test_ib,
9690     .insert_nop = amdgpu_ring_insert_nop,
9691     .pad_ib = amdgpu_ring_generic_pad_ib,
9692     .emit_rreg = gfx_v10_0_ring_emit_rreg,
9693     .emit_wreg = gfx_v10_0_ring_emit_wreg,
9694     .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9695     .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9696 };
9697 
9698 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9699 {
9700     int i;
9701 
9702     adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9703 
9704     for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9705         adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9706 
9707     for (i = 0; i < adev->gfx.num_compute_rings; i++)
9708         adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9709 }
9710 
9711 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9712     .set = gfx_v10_0_set_eop_interrupt_state,
9713     .process = gfx_v10_0_eop_irq,
9714 };
9715 
9716 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9717     .set = gfx_v10_0_set_priv_reg_fault_state,
9718     .process = gfx_v10_0_priv_reg_irq,
9719 };
9720 
9721 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9722     .set = gfx_v10_0_set_priv_inst_fault_state,
9723     .process = gfx_v10_0_priv_inst_irq,
9724 };
9725 
9726 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9727     .set = gfx_v10_0_kiq_set_interrupt_state,
9728     .process = gfx_v10_0_kiq_irq,
9729 };
9730 
9731 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9732 {
9733     adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9734     adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9735 
9736     adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9737     adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9738 
9739     adev->gfx.priv_reg_irq.num_types = 1;
9740     adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9741 
9742     adev->gfx.priv_inst_irq.num_types = 1;
9743     adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9744 }
9745 
9746 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9747 {
9748     switch (adev->ip_versions[GC_HWIP][0]) {
9749     case IP_VERSION(10, 1, 10):
9750     case IP_VERSION(10, 1, 1):
9751     case IP_VERSION(10, 1, 3):
9752     case IP_VERSION(10, 1, 4):
9753     case IP_VERSION(10, 3, 2):
9754     case IP_VERSION(10, 3, 1):
9755     case IP_VERSION(10, 3, 4):
9756     case IP_VERSION(10, 3, 5):
9757     case IP_VERSION(10, 3, 6):
9758     case IP_VERSION(10, 3, 3):
9759     case IP_VERSION(10, 3, 7):
9760         adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9761         break;
9762     case IP_VERSION(10, 1, 2):
9763     case IP_VERSION(10, 3, 0):
9764         adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9765         break;
9766     default:
9767         break;
9768     }
9769 }
9770 
9771 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9772 {
9773     unsigned total_cu = adev->gfx.config.max_cu_per_sh *
9774                 adev->gfx.config.max_sh_per_se *
9775                 adev->gfx.config.max_shader_engines;
9776 
9777     adev->gds.gds_size = 0x10000;
9778     adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9779     adev->gds.gws_size = 64;
9780     adev->gds.oa_size = 16;
9781 }
9782 
9783 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev)
9784 {
9785     /* set gfx eng mqd */
9786     adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
9787         sizeof(struct v10_gfx_mqd);
9788     adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
9789         gfx_v10_0_gfx_mqd_init;
9790     /* set compute eng mqd */
9791     adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
9792         sizeof(struct v10_compute_mqd);
9793     adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
9794         gfx_v10_0_compute_mqd_init;
9795 }
9796 
9797 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9798                               u32 bitmap)
9799 {
9800     u32 data;
9801 
9802     if (!bitmap)
9803         return;
9804 
9805     data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9806     data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9807 
9808     WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9809 }
9810 
9811 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9812 {
9813     u32 disabled_mask =
9814         ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9815     u32 efuse_setting = 0;
9816     u32 vbios_setting = 0;
9817 
9818     efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9819     efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9820     efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9821 
9822     vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9823     vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9824     vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9825 
9826     disabled_mask |= efuse_setting | vbios_setting;
9827 
9828     return (~disabled_mask);
9829 }
9830 
9831 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9832 {
9833     u32 wgp_idx, wgp_active_bitmap;
9834     u32 cu_bitmap_per_wgp, cu_active_bitmap;
9835 
9836     wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9837     cu_active_bitmap = 0;
9838 
9839     for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9840         /* if there is one WGP enabled, it means 2 CUs will be enabled */
9841         cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9842         if (wgp_active_bitmap & (1 << wgp_idx))
9843             cu_active_bitmap |= cu_bitmap_per_wgp;
9844     }
9845 
9846     return cu_active_bitmap;
9847 }
9848 
9849 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9850                  struct amdgpu_cu_info *cu_info)
9851 {
9852     int i, j, k, counter, active_cu_number = 0;
9853     u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9854     unsigned disable_masks[4 * 2];
9855 
9856     if (!adev || !cu_info)
9857         return -EINVAL;
9858 
9859     amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9860 
9861     mutex_lock(&adev->grbm_idx_mutex);
9862     for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9863         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9864             bitmap = i * adev->gfx.config.max_sh_per_se + j;
9865             if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
9866                  (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
9867                  (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6)) ||
9868                  (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 7))) &&
9869                 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9870                 continue;
9871             mask = 1;
9872             ao_bitmap = 0;
9873             counter = 0;
9874             gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
9875             if (i < 4 && j < 2)
9876                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9877                     adev, disable_masks[i * 2 + j]);
9878             bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9879             cu_info->bitmap[i][j] = bitmap;
9880 
9881             for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9882                 if (bitmap & mask) {
9883                     if (counter < adev->gfx.config.max_cu_per_sh)
9884                         ao_bitmap |= mask;
9885                     counter++;
9886                 }
9887                 mask <<= 1;
9888             }
9889             active_cu_number += counter;
9890             if (i < 2 && j < 2)
9891                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9892             cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9893         }
9894     }
9895     gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
9896     mutex_unlock(&adev->grbm_idx_mutex);
9897 
9898     cu_info->number = active_cu_number;
9899     cu_info->ao_cu_mask = ao_cu_mask;
9900     cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9901 
9902     return 0;
9903 }
9904 
9905 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9906 {
9907     uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9908 
9909     efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9910     efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9911     efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9912 
9913     vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9914     vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9915     vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9916 
9917     max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9918                         adev->gfx.config.max_shader_engines);
9919     disabled_sa = efuse_setting | vbios_setting;
9920     disabled_sa &= max_sa_mask;
9921 
9922     return disabled_sa;
9923 }
9924 
9925 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9926 {
9927     uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9928     uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9929 
9930     disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9931 
9932     max_sa_per_se = adev->gfx.config.max_sh_per_se;
9933     max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9934     max_shader_engines = adev->gfx.config.max_shader_engines;
9935 
9936     for (se_index = 0; max_shader_engines > se_index; se_index++) {
9937         disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9938         disabled_sa_per_se &= max_sa_per_se_mask;
9939         if (disabled_sa_per_se == max_sa_per_se_mask) {
9940             WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9941             break;
9942         }
9943     }
9944 }
9945 
9946 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9947 {
9948     WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9949              (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9950              (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9951              (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9952 
9953     WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9954     WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9955              (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9956              (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9957              (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9958              (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9959 
9960     WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9961              (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9962              (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9963              (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9964 
9965     WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9966 
9967     WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9968              (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9969 }
9970 
9971 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9972 {
9973     .type = AMD_IP_BLOCK_TYPE_GFX,
9974     .major = 10,
9975     .minor = 0,
9976     .rev = 0,
9977     .funcs = &gfx_v10_0_ip_funcs,
9978 };
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