amd/amdgpu/df_v1_7.c

0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include "amdgpu.h"
0024 #include "df_v1_7.h"
0025
0026 #include "df/df_1_7_default.h"
0027 #include "df/df_1_7_offset.h"
0028 #include "df/df_1_7_sh_mask.h"
0029
0030 static u32 df_v1_7_channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
0031
0032 static void df_v1_7_sw_init(struct amdgpu_device *adev)
0033 {
0034     adev->df.hash_status.hash_64k = false;
0035     adev->df.hash_status.hash_2m = false;
0036     adev->df.hash_status.hash_1g = false;
0037 }
0038
0039 static void df_v1_7_sw_fini(struct amdgpu_device *adev)
0040 {
0041 }
0042
0043 static void df_v1_7_enable_broadcast_mode(struct amdgpu_device *adev,
0044                       bool enable)
0045 {
0046     u32 tmp;
0047
0048     if (enable) {
0049         tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
0050         tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
0051         WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
0052     } else
0053         WREG32_SOC15(DF, 0, mmFabricConfigAccessControl,
0054                  mmFabricConfigAccessControl_DEFAULT);
0055 }
0056
0057 static u32 df_v1_7_get_fb_channel_number(struct amdgpu_device *adev)
0058 {
0059     u32 tmp;
0060
0061     tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
0062     tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
0063     tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
0064
0065     return tmp;
0066 }
0067
0068 static u32 df_v1_7_get_hbm_channel_number(struct amdgpu_device *adev)
0069 {
0070     int fb_channel_number;
0071
0072     fb_channel_number = adev->df.funcs->get_fb_channel_number(adev);
0073
0074     return df_v1_7_channel_number[fb_channel_number];
0075 }
0076
0077 static void df_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
0078                              bool enable)
0079 {
0080     u32 tmp;
0081
0082     /* Put DF on broadcast mode */
0083     adev->df.funcs->enable_broadcast_mode(adev, true);
0084
0085     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
0086         tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
0087         tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
0088         tmp |= DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY;
0089         WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
0090     } else {
0091         tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
0092         tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
0093         tmp |= DF_V1_7_MGCG_DISABLE;
0094         WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
0095     }
0096
0097     /* Exit boradcast mode */
0098     adev->df.funcs->enable_broadcast_mode(adev, false);
0099 }
0100
0101 static void df_v1_7_get_clockgating_state(struct amdgpu_device *adev,
0102                       u64 *flags)
0103 {
0104     u32 tmp;
0105
0106     /* AMD_CG_SUPPORT_DF_MGCG */
0107     tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
0108     if (tmp & DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY)
0109         *flags |= AMD_CG_SUPPORT_DF_MGCG;
0110 }
0111
0112 static void df_v1_7_enable_ecc_force_par_wr_rmw(struct amdgpu_device *adev,
0113                         bool enable)
0114 {
0115     WREG32_FIELD15(DF, 0, DF_CS_AON0_CoherentSlaveModeCtrlA0,
0116                ForceParWrRMW, enable);
0117 }
0118
0119 const struct amdgpu_df_funcs df_v1_7_funcs = {
0120     .sw_init = df_v1_7_sw_init,
0121     .sw_fini = df_v1_7_sw_fini,
0122     .enable_broadcast_mode = df_v1_7_enable_broadcast_mode,
0123     .get_fb_channel_number = df_v1_7_get_fb_channel_number,
0124     .get_hbm_channel_number = df_v1_7_get_hbm_channel_number,
0125     .update_medium_grain_clock_gating = df_v1_7_update_medium_grain_clock_gating,
0126     .get_clockgating_state = df_v1_7_get_clockgating_state,
0127     .enable_ecc_force_par_wr_rmw = df_v1_7_enable_ecc_force_par_wr_rmw,
0128 };