Back to home page

OSCL-LXR
 
 

     

0001 /*
0002  * Copyright 2013 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: Alex Deucher
0023  */
0024 
0025 #include <linux/firmware.h>
0026 #include <linux/module.h>
0027 
0028 #include "amdgpu.h"
0029 #include "amdgpu_ucode.h"
0030 #include "amdgpu_trace.h"
0031 #include "cikd.h"
0032 #include "cik.h"
0033 
0034 #include "bif/bif_4_1_d.h"
0035 #include "bif/bif_4_1_sh_mask.h"
0036 
0037 #include "gca/gfx_7_2_d.h"
0038 #include "gca/gfx_7_2_enum.h"
0039 #include "gca/gfx_7_2_sh_mask.h"
0040 
0041 #include "gmc/gmc_7_1_d.h"
0042 #include "gmc/gmc_7_1_sh_mask.h"
0043 
0044 #include "oss/oss_2_0_d.h"
0045 #include "oss/oss_2_0_sh_mask.h"
0046 
0047 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
0048 {
0049     SDMA0_REGISTER_OFFSET,
0050     SDMA1_REGISTER_OFFSET
0051 };
0052 
0053 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev);
0054 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev);
0055 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev);
0056 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev);
0057 static int cik_sdma_soft_reset(void *handle);
0058 
0059 MODULE_FIRMWARE("amdgpu/bonaire_sdma.bin");
0060 MODULE_FIRMWARE("amdgpu/bonaire_sdma1.bin");
0061 MODULE_FIRMWARE("amdgpu/hawaii_sdma.bin");
0062 MODULE_FIRMWARE("amdgpu/hawaii_sdma1.bin");
0063 MODULE_FIRMWARE("amdgpu/kaveri_sdma.bin");
0064 MODULE_FIRMWARE("amdgpu/kaveri_sdma1.bin");
0065 MODULE_FIRMWARE("amdgpu/kabini_sdma.bin");
0066 MODULE_FIRMWARE("amdgpu/kabini_sdma1.bin");
0067 MODULE_FIRMWARE("amdgpu/mullins_sdma.bin");
0068 MODULE_FIRMWARE("amdgpu/mullins_sdma1.bin");
0069 
0070 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev);
0071 
0072 
0073 static void cik_sdma_free_microcode(struct amdgpu_device *adev)
0074 {
0075     int i;
0076     for (i = 0; i < adev->sdma.num_instances; i++) {
0077             release_firmware(adev->sdma.instance[i].fw);
0078             adev->sdma.instance[i].fw = NULL;
0079     }
0080 }
0081 
0082 /*
0083  * sDMA - System DMA
0084  * Starting with CIK, the GPU has new asynchronous
0085  * DMA engines.  These engines are used for compute
0086  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
0087  * and each one supports 1 ring buffer used for gfx
0088  * and 2 queues used for compute.
0089  *
0090  * The programming model is very similar to the CP
0091  * (ring buffer, IBs, etc.), but sDMA has it's own
0092  * packet format that is different from the PM4 format
0093  * used by the CP. sDMA supports copying data, writing
0094  * embedded data, solid fills, and a number of other
0095  * things.  It also has support for tiling/detiling of
0096  * buffers.
0097  */
0098 
0099 /**
0100  * cik_sdma_init_microcode - load ucode images from disk
0101  *
0102  * @adev: amdgpu_device pointer
0103  *
0104  * Use the firmware interface to load the ucode images into
0105  * the driver (not loaded into hw).
0106  * Returns 0 on success, error on failure.
0107  */
0108 static int cik_sdma_init_microcode(struct amdgpu_device *adev)
0109 {
0110     const char *chip_name;
0111     char fw_name[30];
0112     int err = 0, i;
0113 
0114     DRM_DEBUG("\n");
0115 
0116     switch (adev->asic_type) {
0117     case CHIP_BONAIRE:
0118         chip_name = "bonaire";
0119         break;
0120     case CHIP_HAWAII:
0121         chip_name = "hawaii";
0122         break;
0123     case CHIP_KAVERI:
0124         chip_name = "kaveri";
0125         break;
0126     case CHIP_KABINI:
0127         chip_name = "kabini";
0128         break;
0129     case CHIP_MULLINS:
0130         chip_name = "mullins";
0131         break;
0132     default: BUG();
0133     }
0134 
0135     for (i = 0; i < adev->sdma.num_instances; i++) {
0136         if (i == 0)
0137             snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
0138         else
0139             snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
0140         err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
0141         if (err)
0142             goto out;
0143         err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
0144     }
0145 out:
0146     if (err) {
0147         pr_err("cik_sdma: Failed to load firmware \"%s\"\n", fw_name);
0148         for (i = 0; i < adev->sdma.num_instances; i++) {
0149             release_firmware(adev->sdma.instance[i].fw);
0150             adev->sdma.instance[i].fw = NULL;
0151         }
0152     }
0153     return err;
0154 }
0155 
0156 /**
0157  * cik_sdma_ring_get_rptr - get the current read pointer
0158  *
0159  * @ring: amdgpu ring pointer
0160  *
0161  * Get the current rptr from the hardware (CIK+).
0162  */
0163 static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
0164 {
0165     u32 rptr;
0166 
0167     rptr = *ring->rptr_cpu_addr;
0168 
0169     return (rptr & 0x3fffc) >> 2;
0170 }
0171 
0172 /**
0173  * cik_sdma_ring_get_wptr - get the current write pointer
0174  *
0175  * @ring: amdgpu ring pointer
0176  *
0177  * Get the current wptr from the hardware (CIK+).
0178  */
0179 static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
0180 {
0181     struct amdgpu_device *adev = ring->adev;
0182 
0183     return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;
0184 }
0185 
0186 /**
0187  * cik_sdma_ring_set_wptr - commit the write pointer
0188  *
0189  * @ring: amdgpu ring pointer
0190  *
0191  * Write the wptr back to the hardware (CIK+).
0192  */
0193 static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
0194 {
0195     struct amdgpu_device *adev = ring->adev;
0196 
0197     WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],
0198            (ring->wptr << 2) & 0x3fffc);
0199 }
0200 
0201 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
0202 {
0203     struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
0204     int i;
0205 
0206     for (i = 0; i < count; i++)
0207         if (sdma && sdma->burst_nop && (i == 0))
0208             amdgpu_ring_write(ring, ring->funcs->nop |
0209                       SDMA_NOP_COUNT(count - 1));
0210         else
0211             amdgpu_ring_write(ring, ring->funcs->nop);
0212 }
0213 
0214 /**
0215  * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine
0216  *
0217  * @ring: amdgpu ring pointer
0218  * @job: job to retrive vmid from
0219  * @ib: IB object to schedule
0220  * @flags: unused
0221  *
0222  * Schedule an IB in the DMA ring (CIK).
0223  */
0224 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
0225                   struct amdgpu_job *job,
0226                   struct amdgpu_ib *ib,
0227                   uint32_t flags)
0228 {
0229     unsigned vmid = AMDGPU_JOB_GET_VMID(job);
0230     u32 extra_bits = vmid & 0xf;
0231 
0232     /* IB packet must end on a 8 DW boundary */
0233     cik_sdma_ring_insert_nop(ring, (4 - lower_32_bits(ring->wptr)) & 7);
0234 
0235     amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
0236     amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
0237     amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
0238     amdgpu_ring_write(ring, ib->length_dw);
0239 
0240 }
0241 
0242 /**
0243  * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
0244  *
0245  * @ring: amdgpu ring pointer
0246  *
0247  * Emit an hdp flush packet on the requested DMA ring.
0248  */
0249 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
0250 {
0251     u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
0252               SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
0253     u32 ref_and_mask;
0254 
0255     if (ring->me == 0)
0256         ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
0257     else
0258         ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
0259 
0260     amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
0261     amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
0262     amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
0263     amdgpu_ring_write(ring, ref_and_mask); /* reference */
0264     amdgpu_ring_write(ring, ref_and_mask); /* mask */
0265     amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
0266 }
0267 
0268 /**
0269  * cik_sdma_ring_emit_fence - emit a fence on the DMA ring
0270  *
0271  * @ring: amdgpu ring pointer
0272  * @addr: address
0273  * @seq: sequence number
0274  * @flags: fence related flags
0275  *
0276  * Add a DMA fence packet to the ring to write
0277  * the fence seq number and DMA trap packet to generate
0278  * an interrupt if needed (CIK).
0279  */
0280 static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
0281                      unsigned flags)
0282 {
0283     bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
0284     /* write the fence */
0285     amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
0286     amdgpu_ring_write(ring, lower_32_bits(addr));
0287     amdgpu_ring_write(ring, upper_32_bits(addr));
0288     amdgpu_ring_write(ring, lower_32_bits(seq));
0289 
0290     /* optionally write high bits as well */
0291     if (write64bit) {
0292         addr += 4;
0293         amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
0294         amdgpu_ring_write(ring, lower_32_bits(addr));
0295         amdgpu_ring_write(ring, upper_32_bits(addr));
0296         amdgpu_ring_write(ring, upper_32_bits(seq));
0297     }
0298 
0299     /* generate an interrupt */
0300     amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
0301 }
0302 
0303 /**
0304  * cik_sdma_gfx_stop - stop the gfx async dma engines
0305  *
0306  * @adev: amdgpu_device pointer
0307  *
0308  * Stop the gfx async dma ring buffers (CIK).
0309  */
0310 static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
0311 {
0312     struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
0313     struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
0314     u32 rb_cntl;
0315     int i;
0316 
0317     if ((adev->mman.buffer_funcs_ring == sdma0) ||
0318         (adev->mman.buffer_funcs_ring == sdma1))
0319             amdgpu_ttm_set_buffer_funcs_status(adev, false);
0320 
0321     for (i = 0; i < adev->sdma.num_instances; i++) {
0322         rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
0323         rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
0324         WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
0325         WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);
0326     }
0327 }
0328 
0329 /**
0330  * cik_sdma_rlc_stop - stop the compute async dma engines
0331  *
0332  * @adev: amdgpu_device pointer
0333  *
0334  * Stop the compute async dma queues (CIK).
0335  */
0336 static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
0337 {
0338     /* XXX todo */
0339 }
0340 
0341 /**
0342  * cik_ctx_switch_enable - stop the async dma engines context switch
0343  *
0344  * @adev: amdgpu_device pointer
0345  * @enable: enable/disable the DMA MEs context switch.
0346  *
0347  * Halt or unhalt the async dma engines context switch (VI).
0348  */
0349 static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
0350 {
0351     u32 f32_cntl, phase_quantum = 0;
0352     int i;
0353 
0354     if (amdgpu_sdma_phase_quantum) {
0355         unsigned value = amdgpu_sdma_phase_quantum;
0356         unsigned unit = 0;
0357 
0358         while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
0359                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
0360             value = (value + 1) >> 1;
0361             unit++;
0362         }
0363         if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
0364                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
0365             value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
0366                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
0367             unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
0368                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
0369             WARN_ONCE(1,
0370             "clamping sdma_phase_quantum to %uK clock cycles\n",
0371                   value << unit);
0372         }
0373         phase_quantum =
0374             value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
0375             unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
0376     }
0377 
0378     for (i = 0; i < adev->sdma.num_instances; i++) {
0379         f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
0380         if (enable) {
0381             f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
0382                     AUTO_CTXSW_ENABLE, 1);
0383             if (amdgpu_sdma_phase_quantum) {
0384                 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
0385                        phase_quantum);
0386                 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
0387                        phase_quantum);
0388             }
0389         } else {
0390             f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
0391                     AUTO_CTXSW_ENABLE, 0);
0392         }
0393 
0394         WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
0395     }
0396 }
0397 
0398 /**
0399  * cik_sdma_enable - stop the async dma engines
0400  *
0401  * @adev: amdgpu_device pointer
0402  * @enable: enable/disable the DMA MEs.
0403  *
0404  * Halt or unhalt the async dma engines (CIK).
0405  */
0406 static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
0407 {
0408     u32 me_cntl;
0409     int i;
0410 
0411     if (!enable) {
0412         cik_sdma_gfx_stop(adev);
0413         cik_sdma_rlc_stop(adev);
0414     }
0415 
0416     for (i = 0; i < adev->sdma.num_instances; i++) {
0417         me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
0418         if (enable)
0419             me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
0420         else
0421             me_cntl |= SDMA0_F32_CNTL__HALT_MASK;
0422         WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
0423     }
0424 }
0425 
0426 /**
0427  * cik_sdma_gfx_resume - setup and start the async dma engines
0428  *
0429  * @adev: amdgpu_device pointer
0430  *
0431  * Set up the gfx DMA ring buffers and enable them (CIK).
0432  * Returns 0 for success, error for failure.
0433  */
0434 static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
0435 {
0436     struct amdgpu_ring *ring;
0437     u32 rb_cntl, ib_cntl;
0438     u32 rb_bufsz;
0439     int i, j, r;
0440 
0441     for (i = 0; i < adev->sdma.num_instances; i++) {
0442         ring = &adev->sdma.instance[i].ring;
0443 
0444         mutex_lock(&adev->srbm_mutex);
0445         for (j = 0; j < 16; j++) {
0446             cik_srbm_select(adev, 0, 0, 0, j);
0447             /* SDMA GFX */
0448             WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
0449             WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
0450             /* XXX SDMA RLC - todo */
0451         }
0452         cik_srbm_select(adev, 0, 0, 0, 0);
0453         mutex_unlock(&adev->srbm_mutex);
0454 
0455         WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
0456                adev->gfx.config.gb_addr_config & 0x70);
0457 
0458         WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);
0459         WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
0460 
0461         /* Set ring buffer size in dwords */
0462         rb_bufsz = order_base_2(ring->ring_size / 4);
0463         rb_cntl = rb_bufsz << 1;
0464 #ifdef __BIG_ENDIAN
0465         rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK |
0466             SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK;
0467 #endif
0468         WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
0469 
0470         /* Initialize the ring buffer's read and write pointers */
0471         WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
0472         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
0473         WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
0474         WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
0475 
0476         /* set the wb address whether it's enabled or not */
0477         WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
0478                upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
0479         WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
0480                ((ring->rptr_gpu_addr) & 0xFFFFFFFC));
0481 
0482         rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK;
0483 
0484         WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
0485         WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
0486 
0487         ring->wptr = 0;
0488         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
0489 
0490         /* enable DMA RB */
0491         WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],
0492                rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK);
0493 
0494         ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK;
0495 #ifdef __BIG_ENDIAN
0496         ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK;
0497 #endif
0498         /* enable DMA IBs */
0499         WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
0500 
0501         ring->sched.ready = true;
0502     }
0503 
0504     cik_sdma_enable(adev, true);
0505 
0506     for (i = 0; i < adev->sdma.num_instances; i++) {
0507         ring = &adev->sdma.instance[i].ring;
0508         r = amdgpu_ring_test_helper(ring);
0509         if (r)
0510             return r;
0511 
0512         if (adev->mman.buffer_funcs_ring == ring)
0513             amdgpu_ttm_set_buffer_funcs_status(adev, true);
0514     }
0515 
0516     return 0;
0517 }
0518 
0519 /**
0520  * cik_sdma_rlc_resume - setup and start the async dma engines
0521  *
0522  * @adev: amdgpu_device pointer
0523  *
0524  * Set up the compute DMA queues and enable them (CIK).
0525  * Returns 0 for success, error for failure.
0526  */
0527 static int cik_sdma_rlc_resume(struct amdgpu_device *adev)
0528 {
0529     /* XXX todo */
0530     return 0;
0531 }
0532 
0533 /**
0534  * cik_sdma_load_microcode - load the sDMA ME ucode
0535  *
0536  * @adev: amdgpu_device pointer
0537  *
0538  * Loads the sDMA0/1 ucode.
0539  * Returns 0 for success, -EINVAL if the ucode is not available.
0540  */
0541 static int cik_sdma_load_microcode(struct amdgpu_device *adev)
0542 {
0543     const struct sdma_firmware_header_v1_0 *hdr;
0544     const __le32 *fw_data;
0545     u32 fw_size;
0546     int i, j;
0547 
0548     /* halt the MEs */
0549     cik_sdma_enable(adev, false);
0550 
0551     for (i = 0; i < adev->sdma.num_instances; i++) {
0552         if (!adev->sdma.instance[i].fw)
0553             return -EINVAL;
0554         hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
0555         amdgpu_ucode_print_sdma_hdr(&hdr->header);
0556         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
0557         adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
0558         adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
0559         if (adev->sdma.instance[i].feature_version >= 20)
0560             adev->sdma.instance[i].burst_nop = true;
0561         fw_data = (const __le32 *)
0562             (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
0563         WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
0564         for (j = 0; j < fw_size; j++)
0565             WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
0566         WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
0567     }
0568 
0569     return 0;
0570 }
0571 
0572 /**
0573  * cik_sdma_start - setup and start the async dma engines
0574  *
0575  * @adev: amdgpu_device pointer
0576  *
0577  * Set up the DMA engines and enable them (CIK).
0578  * Returns 0 for success, error for failure.
0579  */
0580 static int cik_sdma_start(struct amdgpu_device *adev)
0581 {
0582     int r;
0583 
0584     r = cik_sdma_load_microcode(adev);
0585     if (r)
0586         return r;
0587 
0588     /* halt the engine before programing */
0589     cik_sdma_enable(adev, false);
0590     /* enable sdma ring preemption */
0591     cik_ctx_switch_enable(adev, true);
0592 
0593     /* start the gfx rings and rlc compute queues */
0594     r = cik_sdma_gfx_resume(adev);
0595     if (r)
0596         return r;
0597     r = cik_sdma_rlc_resume(adev);
0598     if (r)
0599         return r;
0600 
0601     return 0;
0602 }
0603 
0604 /**
0605  * cik_sdma_ring_test_ring - simple async dma engine test
0606  *
0607  * @ring: amdgpu_ring structure holding ring information
0608  *
0609  * Test the DMA engine by writing using it to write an
0610  * value to memory. (CIK).
0611  * Returns 0 for success, error for failure.
0612  */
0613 static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring)
0614 {
0615     struct amdgpu_device *adev = ring->adev;
0616     unsigned i;
0617     unsigned index;
0618     int r;
0619     u32 tmp;
0620     u64 gpu_addr;
0621 
0622     r = amdgpu_device_wb_get(adev, &index);
0623     if (r)
0624         return r;
0625 
0626     gpu_addr = adev->wb.gpu_addr + (index * 4);
0627     tmp = 0xCAFEDEAD;
0628     adev->wb.wb[index] = cpu_to_le32(tmp);
0629 
0630     r = amdgpu_ring_alloc(ring, 5);
0631     if (r)
0632         goto error_free_wb;
0633 
0634     amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
0635     amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
0636     amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
0637     amdgpu_ring_write(ring, 1); /* number of DWs to follow */
0638     amdgpu_ring_write(ring, 0xDEADBEEF);
0639     amdgpu_ring_commit(ring);
0640 
0641     for (i = 0; i < adev->usec_timeout; i++) {
0642         tmp = le32_to_cpu(adev->wb.wb[index]);
0643         if (tmp == 0xDEADBEEF)
0644             break;
0645         udelay(1);
0646     }
0647 
0648     if (i >= adev->usec_timeout)
0649         r = -ETIMEDOUT;
0650 
0651 error_free_wb:
0652     amdgpu_device_wb_free(adev, index);
0653     return r;
0654 }
0655 
0656 /**
0657  * cik_sdma_ring_test_ib - test an IB on the DMA engine
0658  *
0659  * @ring: amdgpu_ring structure holding ring information
0660  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
0661  *
0662  * Test a simple IB in the DMA ring (CIK).
0663  * Returns 0 on success, error on failure.
0664  */
0665 static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout)
0666 {
0667     struct amdgpu_device *adev = ring->adev;
0668     struct amdgpu_ib ib;
0669     struct dma_fence *f = NULL;
0670     unsigned index;
0671     u32 tmp = 0;
0672     u64 gpu_addr;
0673     long r;
0674 
0675     r = amdgpu_device_wb_get(adev, &index);
0676     if (r)
0677         return r;
0678 
0679     gpu_addr = adev->wb.gpu_addr + (index * 4);
0680     tmp = 0xCAFEDEAD;
0681     adev->wb.wb[index] = cpu_to_le32(tmp);
0682     memset(&ib, 0, sizeof(ib));
0683     r = amdgpu_ib_get(adev, NULL, 256,
0684                     AMDGPU_IB_POOL_DIRECT, &ib);
0685     if (r)
0686         goto err0;
0687 
0688     ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE,
0689                 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
0690     ib.ptr[1] = lower_32_bits(gpu_addr);
0691     ib.ptr[2] = upper_32_bits(gpu_addr);
0692     ib.ptr[3] = 1;
0693     ib.ptr[4] = 0xDEADBEEF;
0694     ib.length_dw = 5;
0695     r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
0696     if (r)
0697         goto err1;
0698 
0699     r = dma_fence_wait_timeout(f, false, timeout);
0700     if (r == 0) {
0701         r = -ETIMEDOUT;
0702         goto err1;
0703     } else if (r < 0) {
0704         goto err1;
0705     }
0706     tmp = le32_to_cpu(adev->wb.wb[index]);
0707     if (tmp == 0xDEADBEEF)
0708         r = 0;
0709     else
0710         r = -EINVAL;
0711 
0712 err1:
0713     amdgpu_ib_free(adev, &ib, NULL);
0714     dma_fence_put(f);
0715 err0:
0716     amdgpu_device_wb_free(adev, index);
0717     return r;
0718 }
0719 
0720 /**
0721  * cik_sdma_vm_copy_pte - update PTEs by copying them from the GART
0722  *
0723  * @ib: indirect buffer to fill with commands
0724  * @pe: addr of the page entry
0725  * @src: src addr to copy from
0726  * @count: number of page entries to update
0727  *
0728  * Update PTEs by copying them from the GART using sDMA (CIK).
0729  */
0730 static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib,
0731                  uint64_t pe, uint64_t src,
0732                  unsigned count)
0733 {
0734     unsigned bytes = count * 8;
0735 
0736     ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
0737         SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
0738     ib->ptr[ib->length_dw++] = bytes;
0739     ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
0740     ib->ptr[ib->length_dw++] = lower_32_bits(src);
0741     ib->ptr[ib->length_dw++] = upper_32_bits(src);
0742     ib->ptr[ib->length_dw++] = lower_32_bits(pe);
0743     ib->ptr[ib->length_dw++] = upper_32_bits(pe);
0744 }
0745 
0746 /**
0747  * cik_sdma_vm_write_pte - update PTEs by writing them manually
0748  *
0749  * @ib: indirect buffer to fill with commands
0750  * @pe: addr of the page entry
0751  * @value: dst addr to write into pe
0752  * @count: number of page entries to update
0753  * @incr: increase next addr by incr bytes
0754  *
0755  * Update PTEs by writing them manually using sDMA (CIK).
0756  */
0757 static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
0758                   uint64_t value, unsigned count,
0759                   uint32_t incr)
0760 {
0761     unsigned ndw = count * 2;
0762 
0763     ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
0764         SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
0765     ib->ptr[ib->length_dw++] = lower_32_bits(pe);
0766     ib->ptr[ib->length_dw++] = upper_32_bits(pe);
0767     ib->ptr[ib->length_dw++] = ndw;
0768     for (; ndw > 0; ndw -= 2) {
0769         ib->ptr[ib->length_dw++] = lower_32_bits(value);
0770         ib->ptr[ib->length_dw++] = upper_32_bits(value);
0771         value += incr;
0772     }
0773 }
0774 
0775 /**
0776  * cik_sdma_vm_set_pte_pde - update the page tables using sDMA
0777  *
0778  * @ib: indirect buffer to fill with commands
0779  * @pe: addr of the page entry
0780  * @addr: dst addr to write into pe
0781  * @count: number of page entries to update
0782  * @incr: increase next addr by incr bytes
0783  * @flags: access flags
0784  *
0785  * Update the page tables using sDMA (CIK).
0786  */
0787 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
0788                     uint64_t addr, unsigned count,
0789                     uint32_t incr, uint64_t flags)
0790 {
0791     /* for physically contiguous pages (vram) */
0792     ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
0793     ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
0794     ib->ptr[ib->length_dw++] = upper_32_bits(pe);
0795     ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
0796     ib->ptr[ib->length_dw++] = upper_32_bits(flags);
0797     ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
0798     ib->ptr[ib->length_dw++] = upper_32_bits(addr);
0799     ib->ptr[ib->length_dw++] = incr; /* increment size */
0800     ib->ptr[ib->length_dw++] = 0;
0801     ib->ptr[ib->length_dw++] = count; /* number of entries */
0802 }
0803 
0804 /**
0805  * cik_sdma_ring_pad_ib - pad the IB to the required number of dw
0806  *
0807  * @ring: amdgpu_ring structure holding ring information
0808  * @ib: indirect buffer to fill with padding
0809  *
0810  */
0811 static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
0812 {
0813     struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
0814     u32 pad_count;
0815     int i;
0816 
0817     pad_count = (-ib->length_dw) & 7;
0818     for (i = 0; i < pad_count; i++)
0819         if (sdma && sdma->burst_nop && (i == 0))
0820             ib->ptr[ib->length_dw++] =
0821                     SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) |
0822                     SDMA_NOP_COUNT(pad_count - 1);
0823         else
0824             ib->ptr[ib->length_dw++] =
0825                     SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
0826 }
0827 
0828 /**
0829  * cik_sdma_ring_emit_pipeline_sync - sync the pipeline
0830  *
0831  * @ring: amdgpu_ring pointer
0832  *
0833  * Make sure all previous operations are completed (CIK).
0834  */
0835 static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
0836 {
0837     uint32_t seq = ring->fence_drv.sync_seq;
0838     uint64_t addr = ring->fence_drv.gpu_addr;
0839 
0840     /* wait for idle */
0841     amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0,
0842                         SDMA_POLL_REG_MEM_EXTRA_OP(0) |
0843                         SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */
0844                         SDMA_POLL_REG_MEM_EXTRA_M));
0845     amdgpu_ring_write(ring, addr & 0xfffffffc);
0846     amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
0847     amdgpu_ring_write(ring, seq); /* reference */
0848     amdgpu_ring_write(ring, 0xffffffff); /* mask */
0849     amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
0850 }
0851 
0852 /**
0853  * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA
0854  *
0855  * @ring: amdgpu_ring pointer
0856  * @vmid: vmid number to use
0857  * @pd_addr: address
0858  *
0859  * Update the page table base and flush the VM TLB
0860  * using sDMA (CIK).
0861  */
0862 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
0863                     unsigned vmid, uint64_t pd_addr)
0864 {
0865     u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
0866               SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
0867 
0868     amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
0869 
0870     amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
0871     amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
0872     amdgpu_ring_write(ring, 0);
0873     amdgpu_ring_write(ring, 0); /* reference */
0874     amdgpu_ring_write(ring, 0); /* mask */
0875     amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
0876 }
0877 
0878 static void cik_sdma_ring_emit_wreg(struct amdgpu_ring *ring,
0879                     uint32_t reg, uint32_t val)
0880 {
0881     amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
0882     amdgpu_ring_write(ring, reg);
0883     amdgpu_ring_write(ring, val);
0884 }
0885 
0886 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev,
0887                  bool enable)
0888 {
0889     u32 orig, data;
0890 
0891     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
0892         WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
0893         WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
0894     } else {
0895         orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
0896         data |= 0xff000000;
0897         if (data != orig)
0898             WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
0899 
0900         orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
0901         data |= 0xff000000;
0902         if (data != orig)
0903             WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
0904     }
0905 }
0906 
0907 static void cik_enable_sdma_mgls(struct amdgpu_device *adev,
0908                  bool enable)
0909 {
0910     u32 orig, data;
0911 
0912     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
0913         orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
0914         data |= 0x100;
0915         if (orig != data)
0916             WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
0917 
0918         orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
0919         data |= 0x100;
0920         if (orig != data)
0921             WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
0922     } else {
0923         orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
0924         data &= ~0x100;
0925         if (orig != data)
0926             WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
0927 
0928         orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
0929         data &= ~0x100;
0930         if (orig != data)
0931             WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
0932     }
0933 }
0934 
0935 static int cik_sdma_early_init(void *handle)
0936 {
0937     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0938 
0939     adev->sdma.num_instances = SDMA_MAX_INSTANCE;
0940 
0941     cik_sdma_set_ring_funcs(adev);
0942     cik_sdma_set_irq_funcs(adev);
0943     cik_sdma_set_buffer_funcs(adev);
0944     cik_sdma_set_vm_pte_funcs(adev);
0945 
0946     return 0;
0947 }
0948 
0949 static int cik_sdma_sw_init(void *handle)
0950 {
0951     struct amdgpu_ring *ring;
0952     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0953     int r, i;
0954 
0955     r = cik_sdma_init_microcode(adev);
0956     if (r) {
0957         DRM_ERROR("Failed to load sdma firmware!\n");
0958         return r;
0959     }
0960 
0961     /* SDMA trap event */
0962     r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 224,
0963                   &adev->sdma.trap_irq);
0964     if (r)
0965         return r;
0966 
0967     /* SDMA Privileged inst */
0968     r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
0969                   &adev->sdma.illegal_inst_irq);
0970     if (r)
0971         return r;
0972 
0973     /* SDMA Privileged inst */
0974     r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 247,
0975                   &adev->sdma.illegal_inst_irq);
0976     if (r)
0977         return r;
0978 
0979     for (i = 0; i < adev->sdma.num_instances; i++) {
0980         ring = &adev->sdma.instance[i].ring;
0981         ring->ring_obj = NULL;
0982         sprintf(ring->name, "sdma%d", i);
0983         r = amdgpu_ring_init(adev, ring, 1024,
0984                      &adev->sdma.trap_irq,
0985                      (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
0986                      AMDGPU_SDMA_IRQ_INSTANCE1,
0987                      AMDGPU_RING_PRIO_DEFAULT, NULL);
0988         if (r)
0989             return r;
0990     }
0991 
0992     return r;
0993 }
0994 
0995 static int cik_sdma_sw_fini(void *handle)
0996 {
0997     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
0998     int i;
0999 
1000     for (i = 0; i < adev->sdma.num_instances; i++)
1001         amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1002 
1003     cik_sdma_free_microcode(adev);
1004     return 0;
1005 }
1006 
1007 static int cik_sdma_hw_init(void *handle)
1008 {
1009     int r;
1010     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1011 
1012     r = cik_sdma_start(adev);
1013     if (r)
1014         return r;
1015 
1016     return r;
1017 }
1018 
1019 static int cik_sdma_hw_fini(void *handle)
1020 {
1021     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1022 
1023     cik_ctx_switch_enable(adev, false);
1024     cik_sdma_enable(adev, false);
1025 
1026     return 0;
1027 }
1028 
1029 static int cik_sdma_suspend(void *handle)
1030 {
1031     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1032 
1033     return cik_sdma_hw_fini(adev);
1034 }
1035 
1036 static int cik_sdma_resume(void *handle)
1037 {
1038     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1039 
1040     cik_sdma_soft_reset(handle);
1041 
1042     return cik_sdma_hw_init(adev);
1043 }
1044 
1045 static bool cik_sdma_is_idle(void *handle)
1046 {
1047     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1048     u32 tmp = RREG32(mmSRBM_STATUS2);
1049 
1050     if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1051                 SRBM_STATUS2__SDMA1_BUSY_MASK))
1052         return false;
1053 
1054     return true;
1055 }
1056 
1057 static int cik_sdma_wait_for_idle(void *handle)
1058 {
1059     unsigned i;
1060     u32 tmp;
1061     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1062 
1063     for (i = 0; i < adev->usec_timeout; i++) {
1064         tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1065                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1066 
1067         if (!tmp)
1068             return 0;
1069         udelay(1);
1070     }
1071     return -ETIMEDOUT;
1072 }
1073 
1074 static int cik_sdma_soft_reset(void *handle)
1075 {
1076     u32 srbm_soft_reset = 0;
1077     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1078     u32 tmp;
1079 
1080     /* sdma0 */
1081     tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1082     tmp |= SDMA0_F32_CNTL__HALT_MASK;
1083     WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1084     srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1085 
1086     /* sdma1 */
1087     tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1088     tmp |= SDMA0_F32_CNTL__HALT_MASK;
1089     WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1090     srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1091 
1092     if (srbm_soft_reset) {
1093         tmp = RREG32(mmSRBM_SOFT_RESET);
1094         tmp |= srbm_soft_reset;
1095         dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1096         WREG32(mmSRBM_SOFT_RESET, tmp);
1097         tmp = RREG32(mmSRBM_SOFT_RESET);
1098 
1099         udelay(50);
1100 
1101         tmp &= ~srbm_soft_reset;
1102         WREG32(mmSRBM_SOFT_RESET, tmp);
1103         tmp = RREG32(mmSRBM_SOFT_RESET);
1104 
1105         /* Wait a little for things to settle down */
1106         udelay(50);
1107     }
1108 
1109     return 0;
1110 }
1111 
1112 static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev,
1113                        struct amdgpu_irq_src *src,
1114                        unsigned type,
1115                        enum amdgpu_interrupt_state state)
1116 {
1117     u32 sdma_cntl;
1118 
1119     switch (type) {
1120     case AMDGPU_SDMA_IRQ_INSTANCE0:
1121         switch (state) {
1122         case AMDGPU_IRQ_STATE_DISABLE:
1123             sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1124             sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1125             WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1126             break;
1127         case AMDGPU_IRQ_STATE_ENABLE:
1128             sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1129             sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1130             WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1131             break;
1132         default:
1133             break;
1134         }
1135         break;
1136     case AMDGPU_SDMA_IRQ_INSTANCE1:
1137         switch (state) {
1138         case AMDGPU_IRQ_STATE_DISABLE:
1139             sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1140             sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK;
1141             WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1142             break;
1143         case AMDGPU_IRQ_STATE_ENABLE:
1144             sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1145             sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK;
1146             WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1147             break;
1148         default:
1149             break;
1150         }
1151         break;
1152     default:
1153         break;
1154     }
1155     return 0;
1156 }
1157 
1158 static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
1159                      struct amdgpu_irq_src *source,
1160                      struct amdgpu_iv_entry *entry)
1161 {
1162     u8 instance_id, queue_id;
1163 
1164     instance_id = (entry->ring_id & 0x3) >> 0;
1165     queue_id = (entry->ring_id & 0xc) >> 2;
1166     DRM_DEBUG("IH: SDMA trap\n");
1167     switch (instance_id) {
1168     case 0:
1169         switch (queue_id) {
1170         case 0:
1171             amdgpu_fence_process(&adev->sdma.instance[0].ring);
1172             break;
1173         case 1:
1174             /* XXX compute */
1175             break;
1176         case 2:
1177             /* XXX compute */
1178             break;
1179         }
1180         break;
1181     case 1:
1182         switch (queue_id) {
1183         case 0:
1184             amdgpu_fence_process(&adev->sdma.instance[1].ring);
1185             break;
1186         case 1:
1187             /* XXX compute */
1188             break;
1189         case 2:
1190             /* XXX compute */
1191             break;
1192         }
1193         break;
1194     }
1195 
1196     return 0;
1197 }
1198 
1199 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev,
1200                          struct amdgpu_irq_src *source,
1201                          struct amdgpu_iv_entry *entry)
1202 {
1203     u8 instance_id;
1204 
1205     DRM_ERROR("Illegal instruction in SDMA command stream\n");
1206     instance_id = (entry->ring_id & 0x3) >> 0;
1207     drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1208     return 0;
1209 }
1210 
1211 static int cik_sdma_set_clockgating_state(void *handle,
1212                       enum amd_clockgating_state state)
1213 {
1214     bool gate = false;
1215     struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1216 
1217     if (state == AMD_CG_STATE_GATE)
1218         gate = true;
1219 
1220     cik_enable_sdma_mgcg(adev, gate);
1221     cik_enable_sdma_mgls(adev, gate);
1222 
1223     return 0;
1224 }
1225 
1226 static int cik_sdma_set_powergating_state(void *handle,
1227                       enum amd_powergating_state state)
1228 {
1229     return 0;
1230 }
1231 
1232 static const struct amd_ip_funcs cik_sdma_ip_funcs = {
1233     .name = "cik_sdma",
1234     .early_init = cik_sdma_early_init,
1235     .late_init = NULL,
1236     .sw_init = cik_sdma_sw_init,
1237     .sw_fini = cik_sdma_sw_fini,
1238     .hw_init = cik_sdma_hw_init,
1239     .hw_fini = cik_sdma_hw_fini,
1240     .suspend = cik_sdma_suspend,
1241     .resume = cik_sdma_resume,
1242     .is_idle = cik_sdma_is_idle,
1243     .wait_for_idle = cik_sdma_wait_for_idle,
1244     .soft_reset = cik_sdma_soft_reset,
1245     .set_clockgating_state = cik_sdma_set_clockgating_state,
1246     .set_powergating_state = cik_sdma_set_powergating_state,
1247 };
1248 
1249 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
1250     .type = AMDGPU_RING_TYPE_SDMA,
1251     .align_mask = 0xf,
1252     .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0),
1253     .support_64bit_ptrs = false,
1254     .get_rptr = cik_sdma_ring_get_rptr,
1255     .get_wptr = cik_sdma_ring_get_wptr,
1256     .set_wptr = cik_sdma_ring_set_wptr,
1257     .emit_frame_size =
1258         6 + /* cik_sdma_ring_emit_hdp_flush */
1259         3 + /* hdp invalidate */
1260         6 + /* cik_sdma_ring_emit_pipeline_sync */
1261         CIK_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* cik_sdma_ring_emit_vm_flush */
1262         9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */
1263     .emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */
1264     .emit_ib = cik_sdma_ring_emit_ib,
1265     .emit_fence = cik_sdma_ring_emit_fence,
1266     .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync,
1267     .emit_vm_flush = cik_sdma_ring_emit_vm_flush,
1268     .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
1269     .test_ring = cik_sdma_ring_test_ring,
1270     .test_ib = cik_sdma_ring_test_ib,
1271     .insert_nop = cik_sdma_ring_insert_nop,
1272     .pad_ib = cik_sdma_ring_pad_ib,
1273     .emit_wreg = cik_sdma_ring_emit_wreg,
1274 };
1275 
1276 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
1277 {
1278     int i;
1279 
1280     for (i = 0; i < adev->sdma.num_instances; i++) {
1281         adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
1282         adev->sdma.instance[i].ring.me = i;
1283     }
1284 }
1285 
1286 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
1287     .set = cik_sdma_set_trap_irq_state,
1288     .process = cik_sdma_process_trap_irq,
1289 };
1290 
1291 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
1292     .process = cik_sdma_process_illegal_inst_irq,
1293 };
1294 
1295 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
1296 {
1297     adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1298     adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
1299     adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
1300 }
1301 
1302 /**
1303  * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine
1304  *
1305  * @ib: indirect buffer to copy to
1306  * @src_offset: src GPU address
1307  * @dst_offset: dst GPU address
1308  * @byte_count: number of bytes to xfer
1309  * @tmz: is this a secure operation
1310  *
1311  * Copy GPU buffers using the DMA engine (CIK).
1312  * Used by the amdgpu ttm implementation to move pages if
1313  * registered as the asic copy callback.
1314  */
1315 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib,
1316                       uint64_t src_offset,
1317                       uint64_t dst_offset,
1318                       uint32_t byte_count,
1319                       bool tmz)
1320 {
1321     ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0);
1322     ib->ptr[ib->length_dw++] = byte_count;
1323     ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1324     ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1325     ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1326     ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1327     ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1328 }
1329 
1330 /**
1331  * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine
1332  *
1333  * @ib: indirect buffer to fill
1334  * @src_data: value to write to buffer
1335  * @dst_offset: dst GPU address
1336  * @byte_count: number of bytes to xfer
1337  *
1338  * Fill GPU buffers using the DMA engine (CIK).
1339  */
1340 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib,
1341                       uint32_t src_data,
1342                       uint64_t dst_offset,
1343                       uint32_t byte_count)
1344 {
1345     ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0);
1346     ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1347     ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1348     ib->ptr[ib->length_dw++] = src_data;
1349     ib->ptr[ib->length_dw++] = byte_count;
1350 }
1351 
1352 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
1353     .copy_max_bytes = 0x1fffff,
1354     .copy_num_dw = 7,
1355     .emit_copy_buffer = cik_sdma_emit_copy_buffer,
1356 
1357     .fill_max_bytes = 0x1fffff,
1358     .fill_num_dw = 5,
1359     .emit_fill_buffer = cik_sdma_emit_fill_buffer,
1360 };
1361 
1362 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1363 {
1364     adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
1365     adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1366 }
1367 
1368 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1369     .copy_pte_num_dw = 7,
1370     .copy_pte = cik_sdma_vm_copy_pte,
1371 
1372     .write_pte = cik_sdma_vm_write_pte,
1373     .set_pte_pde = cik_sdma_vm_set_pte_pde,
1374 };
1375 
1376 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
1377 {
1378     unsigned i;
1379 
1380     adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
1381     for (i = 0; i < adev->sdma.num_instances; i++) {
1382         adev->vm_manager.vm_pte_scheds[i] =
1383             &adev->sdma.instance[i].ring.sched;
1384     }
1385     adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1386 }
1387 
1388 const struct amdgpu_ip_block_version cik_sdma_ip_block =
1389 {
1390     .type = AMD_IP_BLOCK_TYPE_SDMA,
1391     .major = 2,
1392     .minor = 0,
1393     .rev = 0,
1394     .funcs = &cik_sdma_ip_funcs,
1395 };
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!