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0001 /*
0002  * Copyright 2008 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Author: Stanislaw Skowronek
0023  */
0024 
0025 #include <linux/module.h>
0026 #include <linux/sched.h>
0027 #include <linux/slab.h>
0028 #include <linux/string_helpers.h>
0029 
0030 #include <asm/unaligned.h>
0031 
0032 #include <drm/drm_util.h>
0033 
0034 #define ATOM_DEBUG
0035 
0036 #include "atomfirmware.h"
0037 #include "atom.h"
0038 #include "atom-names.h"
0039 #include "atom-bits.h"
0040 #include "amdgpu.h"
0041 
0042 #define ATOM_COND_ABOVE     0
0043 #define ATOM_COND_ABOVEOREQUAL  1
0044 #define ATOM_COND_ALWAYS    2
0045 #define ATOM_COND_BELOW     3
0046 #define ATOM_COND_BELOWOREQUAL  4
0047 #define ATOM_COND_EQUAL     5
0048 #define ATOM_COND_NOTEQUAL  6
0049 
0050 #define ATOM_PORT_ATI   0
0051 #define ATOM_PORT_PCI   1
0052 #define ATOM_PORT_SYSIO 2
0053 
0054 #define ATOM_UNIT_MICROSEC  0
0055 #define ATOM_UNIT_MILLISEC  1
0056 
0057 #define PLL_INDEX   2
0058 #define PLL_DATA    3
0059 
0060 #define ATOM_CMD_TIMEOUT_SEC    20
0061 
0062 typedef struct {
0063     struct atom_context *ctx;
0064     uint32_t *ps, *ws;
0065     int ps_shift;
0066     uint16_t start;
0067     unsigned last_jump;
0068     unsigned long last_jump_jiffies;
0069     bool abort;
0070 } atom_exec_context;
0071 
0072 int amdgpu_atom_debug;
0073 static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params);
0074 int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params);
0075 
0076 static uint32_t atom_arg_mask[8] =
0077     { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000,
0078       0xFF000000 };
0079 static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 };
0080 
0081 static int atom_dst_to_src[8][4] = {
0082     /* translate destination alignment field to the source alignment encoding */
0083     {0, 0, 0, 0},
0084     {1, 2, 3, 0},
0085     {1, 2, 3, 0},
0086     {1, 2, 3, 0},
0087     {4, 5, 6, 7},
0088     {4, 5, 6, 7},
0089     {4, 5, 6, 7},
0090     {4, 5, 6, 7},
0091 };
0092 static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 };
0093 
0094 static int debug_depth;
0095 #ifdef ATOM_DEBUG
0096 static void debug_print_spaces(int n)
0097 {
0098     while (n--)
0099         printk("   ");
0100 }
0101 
0102 #define DEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG __VA_ARGS__); } while (0)
0103 #define SDEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG); debug_print_spaces(debug_depth); printk(__VA_ARGS__); } while (0)
0104 #else
0105 #define DEBUG(...) do { } while (0)
0106 #define SDEBUG(...) do { } while (0)
0107 #endif
0108 
0109 static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
0110                  uint32_t index, uint32_t data)
0111 {
0112     uint32_t temp = 0xCDCDCDCD;
0113 
0114     while (1)
0115         switch (CU8(base)) {
0116         case ATOM_IIO_NOP:
0117             base++;
0118             break;
0119         case ATOM_IIO_READ:
0120             temp = ctx->card->reg_read(ctx->card, CU16(base + 1));
0121             base += 3;
0122             break;
0123         case ATOM_IIO_WRITE:
0124             ctx->card->reg_write(ctx->card, CU16(base + 1), temp);
0125             base += 3;
0126             break;
0127         case ATOM_IIO_CLEAR:
0128             temp &=
0129                 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
0130                   CU8(base + 2));
0131             base += 3;
0132             break;
0133         case ATOM_IIO_SET:
0134             temp |=
0135                 (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base +
0136                                     2);
0137             base += 3;
0138             break;
0139         case ATOM_IIO_MOVE_INDEX:
0140             temp &=
0141                 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
0142                   CU8(base + 3));
0143             temp |=
0144                 ((index >> CU8(base + 2)) &
0145                  (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
0146                                       3);
0147             base += 4;
0148             break;
0149         case ATOM_IIO_MOVE_DATA:
0150             temp &=
0151                 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
0152                   CU8(base + 3));
0153             temp |=
0154                 ((data >> CU8(base + 2)) &
0155                  (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
0156                                       3);
0157             base += 4;
0158             break;
0159         case ATOM_IIO_MOVE_ATTR:
0160             temp &=
0161                 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
0162                   CU8(base + 3));
0163             temp |=
0164                 ((ctx->
0165                   io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 -
0166                                       CU8
0167                                       (base
0168                                        +
0169                                        1))))
0170                 << CU8(base + 3);
0171             base += 4;
0172             break;
0173         case ATOM_IIO_END:
0174             return temp;
0175         default:
0176             pr_info("Unknown IIO opcode\n");
0177             return 0;
0178         }
0179 }
0180 
0181 static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,
0182                  int *ptr, uint32_t *saved, int print)
0183 {
0184     uint32_t idx, val = 0xCDCDCDCD, align, arg;
0185     struct atom_context *gctx = ctx->ctx;
0186     arg = attr & 7;
0187     align = (attr >> 3) & 7;
0188     switch (arg) {
0189     case ATOM_ARG_REG:
0190         idx = U16(*ptr);
0191         (*ptr) += 2;
0192         if (print)
0193             DEBUG("REG[0x%04X]", idx);
0194         idx += gctx->reg_block;
0195         switch (gctx->io_mode) {
0196         case ATOM_IO_MM:
0197             val = gctx->card->reg_read(gctx->card, idx);
0198             break;
0199         case ATOM_IO_PCI:
0200             pr_info("PCI registers are not implemented\n");
0201             return 0;
0202         case ATOM_IO_SYSIO:
0203             pr_info("SYSIO registers are not implemented\n");
0204             return 0;
0205         default:
0206             if (!(gctx->io_mode & 0x80)) {
0207                 pr_info("Bad IO mode\n");
0208                 return 0;
0209             }
0210             if (!gctx->iio[gctx->io_mode & 0x7F]) {
0211                 pr_info("Undefined indirect IO read method %d\n",
0212                     gctx->io_mode & 0x7F);
0213                 return 0;
0214             }
0215             val =
0216                 atom_iio_execute(gctx,
0217                          gctx->iio[gctx->io_mode & 0x7F],
0218                          idx, 0);
0219         }
0220         break;
0221     case ATOM_ARG_PS:
0222         idx = U8(*ptr);
0223         (*ptr)++;
0224         /* get_unaligned_le32 avoids unaligned accesses from atombios
0225          * tables, noticed on a DEC Alpha. */
0226         val = get_unaligned_le32((u32 *)&ctx->ps[idx]);
0227         if (print)
0228             DEBUG("PS[0x%02X,0x%04X]", idx, val);
0229         break;
0230     case ATOM_ARG_WS:
0231         idx = U8(*ptr);
0232         (*ptr)++;
0233         if (print)
0234             DEBUG("WS[0x%02X]", idx);
0235         switch (idx) {
0236         case ATOM_WS_QUOTIENT:
0237             val = gctx->divmul[0];
0238             break;
0239         case ATOM_WS_REMAINDER:
0240             val = gctx->divmul[1];
0241             break;
0242         case ATOM_WS_DATAPTR:
0243             val = gctx->data_block;
0244             break;
0245         case ATOM_WS_SHIFT:
0246             val = gctx->shift;
0247             break;
0248         case ATOM_WS_OR_MASK:
0249             val = 1 << gctx->shift;
0250             break;
0251         case ATOM_WS_AND_MASK:
0252             val = ~(1 << gctx->shift);
0253             break;
0254         case ATOM_WS_FB_WINDOW:
0255             val = gctx->fb_base;
0256             break;
0257         case ATOM_WS_ATTRIBUTES:
0258             val = gctx->io_attr;
0259             break;
0260         case ATOM_WS_REGPTR:
0261             val = gctx->reg_block;
0262             break;
0263         default:
0264             val = ctx->ws[idx];
0265         }
0266         break;
0267     case ATOM_ARG_ID:
0268         idx = U16(*ptr);
0269         (*ptr) += 2;
0270         if (print) {
0271             if (gctx->data_block)
0272                 DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block);
0273             else
0274                 DEBUG("ID[0x%04X]", idx);
0275         }
0276         val = U32(idx + gctx->data_block);
0277         break;
0278     case ATOM_ARG_FB:
0279         idx = U8(*ptr);
0280         (*ptr)++;
0281         if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) {
0282             DRM_ERROR("ATOM: fb read beyond scratch region: %d vs. %d\n",
0283                   gctx->fb_base + (idx * 4), gctx->scratch_size_bytes);
0284             val = 0;
0285         } else
0286             val = gctx->scratch[(gctx->fb_base / 4) + idx];
0287         if (print)
0288             DEBUG("FB[0x%02X]", idx);
0289         break;
0290     case ATOM_ARG_IMM:
0291         switch (align) {
0292         case ATOM_SRC_DWORD:
0293             val = U32(*ptr);
0294             (*ptr) += 4;
0295             if (print)
0296                 DEBUG("IMM 0x%08X\n", val);
0297             return val;
0298         case ATOM_SRC_WORD0:
0299         case ATOM_SRC_WORD8:
0300         case ATOM_SRC_WORD16:
0301             val = U16(*ptr);
0302             (*ptr) += 2;
0303             if (print)
0304                 DEBUG("IMM 0x%04X\n", val);
0305             return val;
0306         case ATOM_SRC_BYTE0:
0307         case ATOM_SRC_BYTE8:
0308         case ATOM_SRC_BYTE16:
0309         case ATOM_SRC_BYTE24:
0310             val = U8(*ptr);
0311             (*ptr)++;
0312             if (print)
0313                 DEBUG("IMM 0x%02X\n", val);
0314             return val;
0315         }
0316         return 0;
0317     case ATOM_ARG_PLL:
0318         idx = U8(*ptr);
0319         (*ptr)++;
0320         if (print)
0321             DEBUG("PLL[0x%02X]", idx);
0322         val = gctx->card->pll_read(gctx->card, idx);
0323         break;
0324     case ATOM_ARG_MC:
0325         idx = U8(*ptr);
0326         (*ptr)++;
0327         if (print)
0328             DEBUG("MC[0x%02X]", idx);
0329         val = gctx->card->mc_read(gctx->card, idx);
0330         break;
0331     }
0332     if (saved)
0333         *saved = val;
0334     val &= atom_arg_mask[align];
0335     val >>= atom_arg_shift[align];
0336     if (print)
0337         switch (align) {
0338         case ATOM_SRC_DWORD:
0339             DEBUG(".[31:0] -> 0x%08X\n", val);
0340             break;
0341         case ATOM_SRC_WORD0:
0342             DEBUG(".[15:0] -> 0x%04X\n", val);
0343             break;
0344         case ATOM_SRC_WORD8:
0345             DEBUG(".[23:8] -> 0x%04X\n", val);
0346             break;
0347         case ATOM_SRC_WORD16:
0348             DEBUG(".[31:16] -> 0x%04X\n", val);
0349             break;
0350         case ATOM_SRC_BYTE0:
0351             DEBUG(".[7:0] -> 0x%02X\n", val);
0352             break;
0353         case ATOM_SRC_BYTE8:
0354             DEBUG(".[15:8] -> 0x%02X\n", val);
0355             break;
0356         case ATOM_SRC_BYTE16:
0357             DEBUG(".[23:16] -> 0x%02X\n", val);
0358             break;
0359         case ATOM_SRC_BYTE24:
0360             DEBUG(".[31:24] -> 0x%02X\n", val);
0361             break;
0362         }
0363     return val;
0364 }
0365 
0366 static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr)
0367 {
0368     uint32_t align = (attr >> 3) & 7, arg = attr & 7;
0369     switch (arg) {
0370     case ATOM_ARG_REG:
0371     case ATOM_ARG_ID:
0372         (*ptr) += 2;
0373         break;
0374     case ATOM_ARG_PLL:
0375     case ATOM_ARG_MC:
0376     case ATOM_ARG_PS:
0377     case ATOM_ARG_WS:
0378     case ATOM_ARG_FB:
0379         (*ptr)++;
0380         break;
0381     case ATOM_ARG_IMM:
0382         switch (align) {
0383         case ATOM_SRC_DWORD:
0384             (*ptr) += 4;
0385             return;
0386         case ATOM_SRC_WORD0:
0387         case ATOM_SRC_WORD8:
0388         case ATOM_SRC_WORD16:
0389             (*ptr) += 2;
0390             return;
0391         case ATOM_SRC_BYTE0:
0392         case ATOM_SRC_BYTE8:
0393         case ATOM_SRC_BYTE16:
0394         case ATOM_SRC_BYTE24:
0395             (*ptr)++;
0396             return;
0397         }
0398         return;
0399     }
0400 }
0401 
0402 static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr)
0403 {
0404     return atom_get_src_int(ctx, attr, ptr, NULL, 1);
0405 }
0406 
0407 static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr)
0408 {
0409     uint32_t val = 0xCDCDCDCD;
0410 
0411     switch (align) {
0412     case ATOM_SRC_DWORD:
0413         val = U32(*ptr);
0414         (*ptr) += 4;
0415         break;
0416     case ATOM_SRC_WORD0:
0417     case ATOM_SRC_WORD8:
0418     case ATOM_SRC_WORD16:
0419         val = U16(*ptr);
0420         (*ptr) += 2;
0421         break;
0422     case ATOM_SRC_BYTE0:
0423     case ATOM_SRC_BYTE8:
0424     case ATOM_SRC_BYTE16:
0425     case ATOM_SRC_BYTE24:
0426         val = U8(*ptr);
0427         (*ptr)++;
0428         break;
0429     }
0430     return val;
0431 }
0432 
0433 static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr,
0434                  int *ptr, uint32_t *saved, int print)
0435 {
0436     return atom_get_src_int(ctx,
0437                 arg | atom_dst_to_src[(attr >> 3) &
0438                               7][(attr >> 6) & 3] << 3,
0439                 ptr, saved, print);
0440 }
0441 
0442 static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr)
0443 {
0444     atom_skip_src_int(ctx,
0445               arg | atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) &
0446                                  3] << 3, ptr);
0447 }
0448 
0449 static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr,
0450              int *ptr, uint32_t val, uint32_t saved)
0451 {
0452     uint32_t align =
0453         atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val =
0454         val, idx;
0455     struct atom_context *gctx = ctx->ctx;
0456     old_val &= atom_arg_mask[align] >> atom_arg_shift[align];
0457     val <<= atom_arg_shift[align];
0458     val &= atom_arg_mask[align];
0459     saved &= ~atom_arg_mask[align];
0460     val |= saved;
0461     switch (arg) {
0462     case ATOM_ARG_REG:
0463         idx = U16(*ptr);
0464         (*ptr) += 2;
0465         DEBUG("REG[0x%04X]", idx);
0466         idx += gctx->reg_block;
0467         switch (gctx->io_mode) {
0468         case ATOM_IO_MM:
0469             if (idx == 0)
0470                 gctx->card->reg_write(gctx->card, idx,
0471                               val << 2);
0472             else
0473                 gctx->card->reg_write(gctx->card, idx, val);
0474             break;
0475         case ATOM_IO_PCI:
0476             pr_info("PCI registers are not implemented\n");
0477             return;
0478         case ATOM_IO_SYSIO:
0479             pr_info("SYSIO registers are not implemented\n");
0480             return;
0481         default:
0482             if (!(gctx->io_mode & 0x80)) {
0483                 pr_info("Bad IO mode\n");
0484                 return;
0485             }
0486             if (!gctx->iio[gctx->io_mode & 0xFF]) {
0487                 pr_info("Undefined indirect IO write method %d\n",
0488                     gctx->io_mode & 0x7F);
0489                 return;
0490             }
0491             atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF],
0492                      idx, val);
0493         }
0494         break;
0495     case ATOM_ARG_PS:
0496         idx = U8(*ptr);
0497         (*ptr)++;
0498         DEBUG("PS[0x%02X]", idx);
0499         ctx->ps[idx] = cpu_to_le32(val);
0500         break;
0501     case ATOM_ARG_WS:
0502         idx = U8(*ptr);
0503         (*ptr)++;
0504         DEBUG("WS[0x%02X]", idx);
0505         switch (idx) {
0506         case ATOM_WS_QUOTIENT:
0507             gctx->divmul[0] = val;
0508             break;
0509         case ATOM_WS_REMAINDER:
0510             gctx->divmul[1] = val;
0511             break;
0512         case ATOM_WS_DATAPTR:
0513             gctx->data_block = val;
0514             break;
0515         case ATOM_WS_SHIFT:
0516             gctx->shift = val;
0517             break;
0518         case ATOM_WS_OR_MASK:
0519         case ATOM_WS_AND_MASK:
0520             break;
0521         case ATOM_WS_FB_WINDOW:
0522             gctx->fb_base = val;
0523             break;
0524         case ATOM_WS_ATTRIBUTES:
0525             gctx->io_attr = val;
0526             break;
0527         case ATOM_WS_REGPTR:
0528             gctx->reg_block = val;
0529             break;
0530         default:
0531             ctx->ws[idx] = val;
0532         }
0533         break;
0534     case ATOM_ARG_FB:
0535         idx = U8(*ptr);
0536         (*ptr)++;
0537         if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) {
0538             DRM_ERROR("ATOM: fb write beyond scratch region: %d vs. %d\n",
0539                   gctx->fb_base + (idx * 4), gctx->scratch_size_bytes);
0540         } else
0541             gctx->scratch[(gctx->fb_base / 4) + idx] = val;
0542         DEBUG("FB[0x%02X]", idx);
0543         break;
0544     case ATOM_ARG_PLL:
0545         idx = U8(*ptr);
0546         (*ptr)++;
0547         DEBUG("PLL[0x%02X]", idx);
0548         gctx->card->pll_write(gctx->card, idx, val);
0549         break;
0550     case ATOM_ARG_MC:
0551         idx = U8(*ptr);
0552         (*ptr)++;
0553         DEBUG("MC[0x%02X]", idx);
0554         gctx->card->mc_write(gctx->card, idx, val);
0555         return;
0556     }
0557     switch (align) {
0558     case ATOM_SRC_DWORD:
0559         DEBUG(".[31:0] <- 0x%08X\n", old_val);
0560         break;
0561     case ATOM_SRC_WORD0:
0562         DEBUG(".[15:0] <- 0x%04X\n", old_val);
0563         break;
0564     case ATOM_SRC_WORD8:
0565         DEBUG(".[23:8] <- 0x%04X\n", old_val);
0566         break;
0567     case ATOM_SRC_WORD16:
0568         DEBUG(".[31:16] <- 0x%04X\n", old_val);
0569         break;
0570     case ATOM_SRC_BYTE0:
0571         DEBUG(".[7:0] <- 0x%02X\n", old_val);
0572         break;
0573     case ATOM_SRC_BYTE8:
0574         DEBUG(".[15:8] <- 0x%02X\n", old_val);
0575         break;
0576     case ATOM_SRC_BYTE16:
0577         DEBUG(".[23:16] <- 0x%02X\n", old_val);
0578         break;
0579     case ATOM_SRC_BYTE24:
0580         DEBUG(".[31:24] <- 0x%02X\n", old_val);
0581         break;
0582     }
0583 }
0584 
0585 static void atom_op_add(atom_exec_context *ctx, int *ptr, int arg)
0586 {
0587     uint8_t attr = U8((*ptr)++);
0588     uint32_t dst, src, saved;
0589     int dptr = *ptr;
0590     SDEBUG("   dst: ");
0591     dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
0592     SDEBUG("   src: ");
0593     src = atom_get_src(ctx, attr, ptr);
0594     dst += src;
0595     SDEBUG("   dst: ");
0596     atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
0597 }
0598 
0599 static void atom_op_and(atom_exec_context *ctx, int *ptr, int arg)
0600 {
0601     uint8_t attr = U8((*ptr)++);
0602     uint32_t dst, src, saved;
0603     int dptr = *ptr;
0604     SDEBUG("   dst: ");
0605     dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
0606     SDEBUG("   src: ");
0607     src = atom_get_src(ctx, attr, ptr);
0608     dst &= src;
0609     SDEBUG("   dst: ");
0610     atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
0611 }
0612 
0613 static void atom_op_beep(atom_exec_context *ctx, int *ptr, int arg)
0614 {
0615     printk("ATOM BIOS beeped!\n");
0616 }
0617 
0618 static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg)
0619 {
0620     int idx = U8((*ptr)++);
0621     int r = 0;
0622 
0623     if (idx < ATOM_TABLE_NAMES_CNT)
0624         SDEBUG("   table: %d (%s)\n", idx, atom_table_names[idx]);
0625     else
0626         SDEBUG("   table: %d\n", idx);
0627     if (U16(ctx->ctx->cmd_table + 4 + 2 * idx))
0628         r = amdgpu_atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift);
0629     if (r) {
0630         ctx->abort = true;
0631     }
0632 }
0633 
0634 static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg)
0635 {
0636     uint8_t attr = U8((*ptr)++);
0637     uint32_t saved;
0638     int dptr = *ptr;
0639     attr &= 0x38;
0640     attr |= atom_def_dst[attr >> 3] << 6;
0641     atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
0642     SDEBUG("   dst: ");
0643     atom_put_dst(ctx, arg, attr, &dptr, 0, saved);
0644 }
0645 
0646 static void atom_op_compare(atom_exec_context *ctx, int *ptr, int arg)
0647 {
0648     uint8_t attr = U8((*ptr)++);
0649     uint32_t dst, src;
0650     SDEBUG("   src1: ");
0651     dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
0652     SDEBUG("   src2: ");
0653     src = atom_get_src(ctx, attr, ptr);
0654     ctx->ctx->cs_equal = (dst == src);
0655     ctx->ctx->cs_above = (dst > src);
0656     SDEBUG("   result: %s %s\n", ctx->ctx->cs_equal ? "EQ" : "NE",
0657            ctx->ctx->cs_above ? "GT" : "LE");
0658 }
0659 
0660 static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg)
0661 {
0662     unsigned count = U8((*ptr)++);
0663     SDEBUG("   count: %d\n", count);
0664     if (arg == ATOM_UNIT_MICROSEC)
0665         udelay(count);
0666     else if (!drm_can_sleep())
0667         mdelay(count);
0668     else
0669         msleep(count);
0670 }
0671 
0672 static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg)
0673 {
0674     uint8_t attr = U8((*ptr)++);
0675     uint32_t dst, src;
0676     SDEBUG("   src1: ");
0677     dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
0678     SDEBUG("   src2: ");
0679     src = atom_get_src(ctx, attr, ptr);
0680     if (src != 0) {
0681         ctx->ctx->divmul[0] = dst / src;
0682         ctx->ctx->divmul[1] = dst % src;
0683     } else {
0684         ctx->ctx->divmul[0] = 0;
0685         ctx->ctx->divmul[1] = 0;
0686     }
0687 }
0688 
0689 static void atom_op_div32(atom_exec_context *ctx, int *ptr, int arg)
0690 {
0691     uint64_t val64;
0692     uint8_t attr = U8((*ptr)++);
0693     uint32_t dst, src;
0694     SDEBUG("   src1: ");
0695     dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
0696     SDEBUG("   src2: ");
0697     src = atom_get_src(ctx, attr, ptr);
0698     if (src != 0) {
0699         val64 = dst;
0700         val64 |= ((uint64_t)ctx->ctx->divmul[1]) << 32;
0701         do_div(val64, src);
0702         ctx->ctx->divmul[0] = lower_32_bits(val64);
0703         ctx->ctx->divmul[1] = upper_32_bits(val64);
0704     } else {
0705         ctx->ctx->divmul[0] = 0;
0706         ctx->ctx->divmul[1] = 0;
0707     }
0708 }
0709 
0710 static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg)
0711 {
0712     /* functionally, a nop */
0713 }
0714 
0715 static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg)
0716 {
0717     int execute = 0, target = U16(*ptr);
0718     unsigned long cjiffies;
0719 
0720     (*ptr) += 2;
0721     switch (arg) {
0722     case ATOM_COND_ABOVE:
0723         execute = ctx->ctx->cs_above;
0724         break;
0725     case ATOM_COND_ABOVEOREQUAL:
0726         execute = ctx->ctx->cs_above || ctx->ctx->cs_equal;
0727         break;
0728     case ATOM_COND_ALWAYS:
0729         execute = 1;
0730         break;
0731     case ATOM_COND_BELOW:
0732         execute = !(ctx->ctx->cs_above || ctx->ctx->cs_equal);
0733         break;
0734     case ATOM_COND_BELOWOREQUAL:
0735         execute = !ctx->ctx->cs_above;
0736         break;
0737     case ATOM_COND_EQUAL:
0738         execute = ctx->ctx->cs_equal;
0739         break;
0740     case ATOM_COND_NOTEQUAL:
0741         execute = !ctx->ctx->cs_equal;
0742         break;
0743     }
0744     if (arg != ATOM_COND_ALWAYS)
0745         SDEBUG("   taken: %s\n", str_yes_no(execute));
0746     SDEBUG("   target: 0x%04X\n", target);
0747     if (execute) {
0748         if (ctx->last_jump == (ctx->start + target)) {
0749             cjiffies = jiffies;
0750             if (time_after(cjiffies, ctx->last_jump_jiffies)) {
0751                 cjiffies -= ctx->last_jump_jiffies;
0752                 if ((jiffies_to_msecs(cjiffies) > ATOM_CMD_TIMEOUT_SEC*1000)) {
0753                     DRM_ERROR("atombios stuck in loop for more than %dsecs aborting\n",
0754                           ATOM_CMD_TIMEOUT_SEC);
0755                     ctx->abort = true;
0756                 }
0757             } else {
0758                 /* jiffies wrap around we will just wait a little longer */
0759                 ctx->last_jump_jiffies = jiffies;
0760             }
0761         } else {
0762             ctx->last_jump = ctx->start + target;
0763             ctx->last_jump_jiffies = jiffies;
0764         }
0765         *ptr = ctx->start + target;
0766     }
0767 }
0768 
0769 static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg)
0770 {
0771     uint8_t attr = U8((*ptr)++);
0772     uint32_t dst, mask, src, saved;
0773     int dptr = *ptr;
0774     SDEBUG("   dst: ");
0775     dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
0776     mask = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr);
0777     SDEBUG("   mask: 0x%08x", mask);
0778     SDEBUG("   src: ");
0779     src = atom_get_src(ctx, attr, ptr);
0780     dst &= mask;
0781     dst |= src;
0782     SDEBUG("   dst: ");
0783     atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
0784 }
0785 
0786 static void atom_op_move(atom_exec_context *ctx, int *ptr, int arg)
0787 {
0788     uint8_t attr = U8((*ptr)++);
0789     uint32_t src, saved;
0790     int dptr = *ptr;
0791     if (((attr >> 3) & 7) != ATOM_SRC_DWORD)
0792         atom_get_dst(ctx, arg, attr, ptr, &saved, 0);
0793     else {
0794         atom_skip_dst(ctx, arg, attr, ptr);
0795         saved = 0xCDCDCDCD;
0796     }
0797     SDEBUG("   src: ");
0798     src = atom_get_src(ctx, attr, ptr);
0799     SDEBUG("   dst: ");
0800     atom_put_dst(ctx, arg, attr, &dptr, src, saved);
0801 }
0802 
0803 static void atom_op_mul(atom_exec_context *ctx, int *ptr, int arg)
0804 {
0805     uint8_t attr = U8((*ptr)++);
0806     uint32_t dst, src;
0807     SDEBUG("   src1: ");
0808     dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
0809     SDEBUG("   src2: ");
0810     src = atom_get_src(ctx, attr, ptr);
0811     ctx->ctx->divmul[0] = dst * src;
0812 }
0813 
0814 static void atom_op_mul32(atom_exec_context *ctx, int *ptr, int arg)
0815 {
0816     uint64_t val64;
0817     uint8_t attr = U8((*ptr)++);
0818     uint32_t dst, src;
0819     SDEBUG("   src1: ");
0820     dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
0821     SDEBUG("   src2: ");
0822     src = atom_get_src(ctx, attr, ptr);
0823     val64 = (uint64_t)dst * (uint64_t)src;
0824     ctx->ctx->divmul[0] = lower_32_bits(val64);
0825     ctx->ctx->divmul[1] = upper_32_bits(val64);
0826 }
0827 
0828 static void atom_op_nop(atom_exec_context *ctx, int *ptr, int arg)
0829 {
0830     /* nothing */
0831 }
0832 
0833 static void atom_op_or(atom_exec_context *ctx, int *ptr, int arg)
0834 {
0835     uint8_t attr = U8((*ptr)++);
0836     uint32_t dst, src, saved;
0837     int dptr = *ptr;
0838     SDEBUG("   dst: ");
0839     dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
0840     SDEBUG("   src: ");
0841     src = atom_get_src(ctx, attr, ptr);
0842     dst |= src;
0843     SDEBUG("   dst: ");
0844     atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
0845 }
0846 
0847 static void atom_op_postcard(atom_exec_context *ctx, int *ptr, int arg)
0848 {
0849     uint8_t val = U8((*ptr)++);
0850     SDEBUG("POST card output: 0x%02X\n", val);
0851 }
0852 
0853 static void atom_op_repeat(atom_exec_context *ctx, int *ptr, int arg)
0854 {
0855     pr_info("unimplemented!\n");
0856 }
0857 
0858 static void atom_op_restorereg(atom_exec_context *ctx, int *ptr, int arg)
0859 {
0860     pr_info("unimplemented!\n");
0861 }
0862 
0863 static void atom_op_savereg(atom_exec_context *ctx, int *ptr, int arg)
0864 {
0865     pr_info("unimplemented!\n");
0866 }
0867 
0868 static void atom_op_setdatablock(atom_exec_context *ctx, int *ptr, int arg)
0869 {
0870     int idx = U8(*ptr);
0871     (*ptr)++;
0872     SDEBUG("   block: %d\n", idx);
0873     if (!idx)
0874         ctx->ctx->data_block = 0;
0875     else if (idx == 255)
0876         ctx->ctx->data_block = ctx->start;
0877     else
0878         ctx->ctx->data_block = U16(ctx->ctx->data_table + 4 + 2 * idx);
0879     SDEBUG("   base: 0x%04X\n", ctx->ctx->data_block);
0880 }
0881 
0882 static void atom_op_setfbbase(atom_exec_context *ctx, int *ptr, int arg)
0883 {
0884     uint8_t attr = U8((*ptr)++);
0885     SDEBUG("   fb_base: ");
0886     ctx->ctx->fb_base = atom_get_src(ctx, attr, ptr);
0887 }
0888 
0889 static void atom_op_setport(atom_exec_context *ctx, int *ptr, int arg)
0890 {
0891     int port;
0892     switch (arg) {
0893     case ATOM_PORT_ATI:
0894         port = U16(*ptr);
0895         if (port < ATOM_IO_NAMES_CNT)
0896             SDEBUG("   port: %d (%s)\n", port, atom_io_names[port]);
0897         else
0898             SDEBUG("   port: %d\n", port);
0899         if (!port)
0900             ctx->ctx->io_mode = ATOM_IO_MM;
0901         else
0902             ctx->ctx->io_mode = ATOM_IO_IIO | port;
0903         (*ptr) += 2;
0904         break;
0905     case ATOM_PORT_PCI:
0906         ctx->ctx->io_mode = ATOM_IO_PCI;
0907         (*ptr)++;
0908         break;
0909     case ATOM_PORT_SYSIO:
0910         ctx->ctx->io_mode = ATOM_IO_SYSIO;
0911         (*ptr)++;
0912         break;
0913     }
0914 }
0915 
0916 static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg)
0917 {
0918     ctx->ctx->reg_block = U16(*ptr);
0919     (*ptr) += 2;
0920     SDEBUG("   base: 0x%04X\n", ctx->ctx->reg_block);
0921 }
0922 
0923 static void atom_op_shift_left(atom_exec_context *ctx, int *ptr, int arg)
0924 {
0925     uint8_t attr = U8((*ptr)++), shift;
0926     uint32_t saved, dst;
0927     int dptr = *ptr;
0928     attr &= 0x38;
0929     attr |= atom_def_dst[attr >> 3] << 6;
0930     SDEBUG("   dst: ");
0931     dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
0932     shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
0933     SDEBUG("   shift: %d\n", shift);
0934     dst <<= shift;
0935     SDEBUG("   dst: ");
0936     atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
0937 }
0938 
0939 static void atom_op_shift_right(atom_exec_context *ctx, int *ptr, int arg)
0940 {
0941     uint8_t attr = U8((*ptr)++), shift;
0942     uint32_t saved, dst;
0943     int dptr = *ptr;
0944     attr &= 0x38;
0945     attr |= atom_def_dst[attr >> 3] << 6;
0946     SDEBUG("   dst: ");
0947     dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
0948     shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
0949     SDEBUG("   shift: %d\n", shift);
0950     dst >>= shift;
0951     SDEBUG("   dst: ");
0952     atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
0953 }
0954 
0955 static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
0956 {
0957     uint8_t attr = U8((*ptr)++), shift;
0958     uint32_t saved, dst;
0959     int dptr = *ptr;
0960     uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
0961     SDEBUG("   dst: ");
0962     dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
0963     /* op needs to full dst value */
0964     dst = saved;
0965     shift = atom_get_src(ctx, attr, ptr);
0966     SDEBUG("   shift: %d\n", shift);
0967     dst <<= shift;
0968     dst &= atom_arg_mask[dst_align];
0969     dst >>= atom_arg_shift[dst_align];
0970     SDEBUG("   dst: ");
0971     atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
0972 }
0973 
0974 static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg)
0975 {
0976     uint8_t attr = U8((*ptr)++), shift;
0977     uint32_t saved, dst;
0978     int dptr = *ptr;
0979     uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3];
0980     SDEBUG("   dst: ");
0981     dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
0982     /* op needs to full dst value */
0983     dst = saved;
0984     shift = atom_get_src(ctx, attr, ptr);
0985     SDEBUG("   shift: %d\n", shift);
0986     dst >>= shift;
0987     dst &= atom_arg_mask[dst_align];
0988     dst >>= atom_arg_shift[dst_align];
0989     SDEBUG("   dst: ");
0990     atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
0991 }
0992 
0993 static void atom_op_sub(atom_exec_context *ctx, int *ptr, int arg)
0994 {
0995     uint8_t attr = U8((*ptr)++);
0996     uint32_t dst, src, saved;
0997     int dptr = *ptr;
0998     SDEBUG("   dst: ");
0999     dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
1000     SDEBUG("   src: ");
1001     src = atom_get_src(ctx, attr, ptr);
1002     dst -= src;
1003     SDEBUG("   dst: ");
1004     atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
1005 }
1006 
1007 static void atom_op_switch(atom_exec_context *ctx, int *ptr, int arg)
1008 {
1009     uint8_t attr = U8((*ptr)++);
1010     uint32_t src, val, target;
1011     SDEBUG("   switch: ");
1012     src = atom_get_src(ctx, attr, ptr);
1013     while (U16(*ptr) != ATOM_CASE_END)
1014         if (U8(*ptr) == ATOM_CASE_MAGIC) {
1015             (*ptr)++;
1016             SDEBUG("   case: ");
1017             val =
1018                 atom_get_src(ctx, (attr & 0x38) | ATOM_ARG_IMM,
1019                      ptr);
1020             target = U16(*ptr);
1021             if (val == src) {
1022                 SDEBUG("   target: %04X\n", target);
1023                 *ptr = ctx->start + target;
1024                 return;
1025             }
1026             (*ptr) += 2;
1027         } else {
1028             pr_info("Bad case\n");
1029             return;
1030         }
1031     (*ptr) += 2;
1032 }
1033 
1034 static void atom_op_test(atom_exec_context *ctx, int *ptr, int arg)
1035 {
1036     uint8_t attr = U8((*ptr)++);
1037     uint32_t dst, src;
1038     SDEBUG("   src1: ");
1039     dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
1040     SDEBUG("   src2: ");
1041     src = atom_get_src(ctx, attr, ptr);
1042     ctx->ctx->cs_equal = ((dst & src) == 0);
1043     SDEBUG("   result: %s\n", ctx->ctx->cs_equal ? "EQ" : "NE");
1044 }
1045 
1046 static void atom_op_xor(atom_exec_context *ctx, int *ptr, int arg)
1047 {
1048     uint8_t attr = U8((*ptr)++);
1049     uint32_t dst, src, saved;
1050     int dptr = *ptr;
1051     SDEBUG("   dst: ");
1052     dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
1053     SDEBUG("   src: ");
1054     src = atom_get_src(ctx, attr, ptr);
1055     dst ^= src;
1056     SDEBUG("   dst: ");
1057     atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
1058 }
1059 
1060 static void atom_op_debug(atom_exec_context *ctx, int *ptr, int arg)
1061 {
1062     uint8_t val = U8((*ptr)++);
1063     SDEBUG("DEBUG output: 0x%02X\n", val);
1064 }
1065 
1066 static void atom_op_processds(atom_exec_context *ctx, int *ptr, int arg)
1067 {
1068     uint16_t val = U16(*ptr);
1069     (*ptr) += val + 2;
1070     SDEBUG("PROCESSDS output: 0x%02X\n", val);
1071 }
1072 
1073 static struct {
1074     void (*func) (atom_exec_context *, int *, int);
1075     int arg;
1076 } opcode_table[ATOM_OP_CNT] = {
1077     {
1078     NULL, 0}, {
1079     atom_op_move, ATOM_ARG_REG}, {
1080     atom_op_move, ATOM_ARG_PS}, {
1081     atom_op_move, ATOM_ARG_WS}, {
1082     atom_op_move, ATOM_ARG_FB}, {
1083     atom_op_move, ATOM_ARG_PLL}, {
1084     atom_op_move, ATOM_ARG_MC}, {
1085     atom_op_and, ATOM_ARG_REG}, {
1086     atom_op_and, ATOM_ARG_PS}, {
1087     atom_op_and, ATOM_ARG_WS}, {
1088     atom_op_and, ATOM_ARG_FB}, {
1089     atom_op_and, ATOM_ARG_PLL}, {
1090     atom_op_and, ATOM_ARG_MC}, {
1091     atom_op_or, ATOM_ARG_REG}, {
1092     atom_op_or, ATOM_ARG_PS}, {
1093     atom_op_or, ATOM_ARG_WS}, {
1094     atom_op_or, ATOM_ARG_FB}, {
1095     atom_op_or, ATOM_ARG_PLL}, {
1096     atom_op_or, ATOM_ARG_MC}, {
1097     atom_op_shift_left, ATOM_ARG_REG}, {
1098     atom_op_shift_left, ATOM_ARG_PS}, {
1099     atom_op_shift_left, ATOM_ARG_WS}, {
1100     atom_op_shift_left, ATOM_ARG_FB}, {
1101     atom_op_shift_left, ATOM_ARG_PLL}, {
1102     atom_op_shift_left, ATOM_ARG_MC}, {
1103     atom_op_shift_right, ATOM_ARG_REG}, {
1104     atom_op_shift_right, ATOM_ARG_PS}, {
1105     atom_op_shift_right, ATOM_ARG_WS}, {
1106     atom_op_shift_right, ATOM_ARG_FB}, {
1107     atom_op_shift_right, ATOM_ARG_PLL}, {
1108     atom_op_shift_right, ATOM_ARG_MC}, {
1109     atom_op_mul, ATOM_ARG_REG}, {
1110     atom_op_mul, ATOM_ARG_PS}, {
1111     atom_op_mul, ATOM_ARG_WS}, {
1112     atom_op_mul, ATOM_ARG_FB}, {
1113     atom_op_mul, ATOM_ARG_PLL}, {
1114     atom_op_mul, ATOM_ARG_MC}, {
1115     atom_op_div, ATOM_ARG_REG}, {
1116     atom_op_div, ATOM_ARG_PS}, {
1117     atom_op_div, ATOM_ARG_WS}, {
1118     atom_op_div, ATOM_ARG_FB}, {
1119     atom_op_div, ATOM_ARG_PLL}, {
1120     atom_op_div, ATOM_ARG_MC}, {
1121     atom_op_add, ATOM_ARG_REG}, {
1122     atom_op_add, ATOM_ARG_PS}, {
1123     atom_op_add, ATOM_ARG_WS}, {
1124     atom_op_add, ATOM_ARG_FB}, {
1125     atom_op_add, ATOM_ARG_PLL}, {
1126     atom_op_add, ATOM_ARG_MC}, {
1127     atom_op_sub, ATOM_ARG_REG}, {
1128     atom_op_sub, ATOM_ARG_PS}, {
1129     atom_op_sub, ATOM_ARG_WS}, {
1130     atom_op_sub, ATOM_ARG_FB}, {
1131     atom_op_sub, ATOM_ARG_PLL}, {
1132     atom_op_sub, ATOM_ARG_MC}, {
1133     atom_op_setport, ATOM_PORT_ATI}, {
1134     atom_op_setport, ATOM_PORT_PCI}, {
1135     atom_op_setport, ATOM_PORT_SYSIO}, {
1136     atom_op_setregblock, 0}, {
1137     atom_op_setfbbase, 0}, {
1138     atom_op_compare, ATOM_ARG_REG}, {
1139     atom_op_compare, ATOM_ARG_PS}, {
1140     atom_op_compare, ATOM_ARG_WS}, {
1141     atom_op_compare, ATOM_ARG_FB}, {
1142     atom_op_compare, ATOM_ARG_PLL}, {
1143     atom_op_compare, ATOM_ARG_MC}, {
1144     atom_op_switch, 0}, {
1145     atom_op_jump, ATOM_COND_ALWAYS}, {
1146     atom_op_jump, ATOM_COND_EQUAL}, {
1147     atom_op_jump, ATOM_COND_BELOW}, {
1148     atom_op_jump, ATOM_COND_ABOVE}, {
1149     atom_op_jump, ATOM_COND_BELOWOREQUAL}, {
1150     atom_op_jump, ATOM_COND_ABOVEOREQUAL}, {
1151     atom_op_jump, ATOM_COND_NOTEQUAL}, {
1152     atom_op_test, ATOM_ARG_REG}, {
1153     atom_op_test, ATOM_ARG_PS}, {
1154     atom_op_test, ATOM_ARG_WS}, {
1155     atom_op_test, ATOM_ARG_FB}, {
1156     atom_op_test, ATOM_ARG_PLL}, {
1157     atom_op_test, ATOM_ARG_MC}, {
1158     atom_op_delay, ATOM_UNIT_MILLISEC}, {
1159     atom_op_delay, ATOM_UNIT_MICROSEC}, {
1160     atom_op_calltable, 0}, {
1161     atom_op_repeat, 0}, {
1162     atom_op_clear, ATOM_ARG_REG}, {
1163     atom_op_clear, ATOM_ARG_PS}, {
1164     atom_op_clear, ATOM_ARG_WS}, {
1165     atom_op_clear, ATOM_ARG_FB}, {
1166     atom_op_clear, ATOM_ARG_PLL}, {
1167     atom_op_clear, ATOM_ARG_MC}, {
1168     atom_op_nop, 0}, {
1169     atom_op_eot, 0}, {
1170     atom_op_mask, ATOM_ARG_REG}, {
1171     atom_op_mask, ATOM_ARG_PS}, {
1172     atom_op_mask, ATOM_ARG_WS}, {
1173     atom_op_mask, ATOM_ARG_FB}, {
1174     atom_op_mask, ATOM_ARG_PLL}, {
1175     atom_op_mask, ATOM_ARG_MC}, {
1176     atom_op_postcard, 0}, {
1177     atom_op_beep, 0}, {
1178     atom_op_savereg, 0}, {
1179     atom_op_restorereg, 0}, {
1180     atom_op_setdatablock, 0}, {
1181     atom_op_xor, ATOM_ARG_REG}, {
1182     atom_op_xor, ATOM_ARG_PS}, {
1183     atom_op_xor, ATOM_ARG_WS}, {
1184     atom_op_xor, ATOM_ARG_FB}, {
1185     atom_op_xor, ATOM_ARG_PLL}, {
1186     atom_op_xor, ATOM_ARG_MC}, {
1187     atom_op_shl, ATOM_ARG_REG}, {
1188     atom_op_shl, ATOM_ARG_PS}, {
1189     atom_op_shl, ATOM_ARG_WS}, {
1190     atom_op_shl, ATOM_ARG_FB}, {
1191     atom_op_shl, ATOM_ARG_PLL}, {
1192     atom_op_shl, ATOM_ARG_MC}, {
1193     atom_op_shr, ATOM_ARG_REG}, {
1194     atom_op_shr, ATOM_ARG_PS}, {
1195     atom_op_shr, ATOM_ARG_WS}, {
1196     atom_op_shr, ATOM_ARG_FB}, {
1197     atom_op_shr, ATOM_ARG_PLL}, {
1198     atom_op_shr, ATOM_ARG_MC}, {
1199     atom_op_debug, 0}, {
1200     atom_op_processds, 0}, {
1201     atom_op_mul32, ATOM_ARG_PS}, {
1202     atom_op_mul32, ATOM_ARG_WS}, {
1203     atom_op_div32, ATOM_ARG_PS}, {
1204     atom_op_div32, ATOM_ARG_WS},
1205 };
1206 
1207 static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t *params)
1208 {
1209     int base = CU16(ctx->cmd_table + 4 + 2 * index);
1210     int len, ws, ps, ptr;
1211     unsigned char op;
1212     atom_exec_context ectx;
1213     int ret = 0;
1214 
1215     if (!base)
1216         return -EINVAL;
1217 
1218     len = CU16(base + ATOM_CT_SIZE_PTR);
1219     ws = CU8(base + ATOM_CT_WS_PTR);
1220     ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK;
1221     ptr = base + ATOM_CT_CODE_PTR;
1222 
1223     SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps);
1224 
1225     ectx.ctx = ctx;
1226     ectx.ps_shift = ps / 4;
1227     ectx.start = base;
1228     ectx.ps = params;
1229     ectx.abort = false;
1230     ectx.last_jump = 0;
1231     if (ws)
1232         ectx.ws = kcalloc(4, ws, GFP_KERNEL);
1233     else
1234         ectx.ws = NULL;
1235 
1236     debug_depth++;
1237     while (1) {
1238         op = CU8(ptr++);
1239         if (op < ATOM_OP_NAMES_CNT)
1240             SDEBUG("%s @ 0x%04X\n", atom_op_names[op], ptr - 1);
1241         else
1242             SDEBUG("[%d] @ 0x%04X\n", op, ptr - 1);
1243         if (ectx.abort) {
1244             DRM_ERROR("atombios stuck executing %04X (len %d, WS %d, PS %d) @ 0x%04X\n",
1245                 base, len, ws, ps, ptr - 1);
1246             ret = -EINVAL;
1247             goto free;
1248         }
1249 
1250         if (op < ATOM_OP_CNT && op > 0)
1251             opcode_table[op].func(&ectx, &ptr,
1252                           opcode_table[op].arg);
1253         else
1254             break;
1255 
1256         if (op == ATOM_OP_EOT)
1257             break;
1258     }
1259     debug_depth--;
1260     SDEBUG("<<\n");
1261 
1262 free:
1263     if (ws)
1264         kfree(ectx.ws);
1265     return ret;
1266 }
1267 
1268 int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t *params)
1269 {
1270     int r;
1271 
1272     mutex_lock(&ctx->mutex);
1273     /* reset data block */
1274     ctx->data_block = 0;
1275     /* reset reg block */
1276     ctx->reg_block = 0;
1277     /* reset fb window */
1278     ctx->fb_base = 0;
1279     /* reset io mode */
1280     ctx->io_mode = ATOM_IO_MM;
1281     /* reset divmul */
1282     ctx->divmul[0] = 0;
1283     ctx->divmul[1] = 0;
1284     r = amdgpu_atom_execute_table_locked(ctx, index, params);
1285     mutex_unlock(&ctx->mutex);
1286     return r;
1287 }
1288 
1289 static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 };
1290 
1291 static void atom_index_iio(struct atom_context *ctx, int base)
1292 {
1293     ctx->iio = kzalloc(2 * 256, GFP_KERNEL);
1294     if (!ctx->iio)
1295         return;
1296     while (CU8(base) == ATOM_IIO_START) {
1297         ctx->iio[CU8(base + 1)] = base + 2;
1298         base += 2;
1299         while (CU8(base) != ATOM_IIO_END)
1300             base += atom_iio_len[CU8(base)];
1301         base += 3;
1302     }
1303 }
1304 
1305 static void atom_get_vbios_name(struct atom_context *ctx)
1306 {
1307     unsigned char *p_rom;
1308     unsigned char str_num;
1309     unsigned short off_to_vbios_str;
1310     unsigned char *c_ptr;
1311     int name_size;
1312     int i;
1313 
1314     const char *na = "--N/A--";
1315     char *back;
1316 
1317     p_rom = ctx->bios;
1318 
1319     str_num = *(p_rom + OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS);
1320     if (str_num != 0) {
1321         off_to_vbios_str =
1322             *(unsigned short *)(p_rom + OFFSET_TO_GET_ATOMBIOS_STRING_START);
1323 
1324         c_ptr = (unsigned char *)(p_rom + off_to_vbios_str);
1325     } else {
1326         /* do not know where to find name */
1327         memcpy(ctx->name, na, 7);
1328         ctx->name[7] = 0;
1329         return;
1330     }
1331 
1332     /*
1333      * skip the atombios strings, usually 4
1334      * 1st is P/N, 2nd is ASIC, 3rd is PCI type, 4th is Memory type
1335      */
1336     for (i = 0; i < str_num; i++) {
1337         while (*c_ptr != 0)
1338             c_ptr++;
1339         c_ptr++;
1340     }
1341 
1342     /* skip the following 2 chars: 0x0D 0x0A */
1343     c_ptr += 2;
1344 
1345     name_size = strnlen(c_ptr, STRLEN_LONG - 1);
1346     memcpy(ctx->name, c_ptr, name_size);
1347     back = ctx->name + name_size;
1348     while ((*--back) == ' ')
1349         ;
1350     *(back + 1) = '\0';
1351 }
1352 
1353 static void atom_get_vbios_date(struct atom_context *ctx)
1354 {
1355     unsigned char *p_rom;
1356     unsigned char *date_in_rom;
1357 
1358     p_rom = ctx->bios;
1359 
1360     date_in_rom = p_rom + OFFSET_TO_VBIOS_DATE;
1361 
1362     ctx->date[0] = '2';
1363     ctx->date[1] = '0';
1364     ctx->date[2] = date_in_rom[6];
1365     ctx->date[3] = date_in_rom[7];
1366     ctx->date[4] = '/';
1367     ctx->date[5] = date_in_rom[0];
1368     ctx->date[6] = date_in_rom[1];
1369     ctx->date[7] = '/';
1370     ctx->date[8] = date_in_rom[3];
1371     ctx->date[9] = date_in_rom[4];
1372     ctx->date[10] = ' ';
1373     ctx->date[11] = date_in_rom[9];
1374     ctx->date[12] = date_in_rom[10];
1375     ctx->date[13] = date_in_rom[11];
1376     ctx->date[14] = date_in_rom[12];
1377     ctx->date[15] = date_in_rom[13];
1378     ctx->date[16] = '\0';
1379 }
1380 
1381 static unsigned char *atom_find_str_in_rom(struct atom_context *ctx, char *str, int start,
1382                        int end, int maxlen)
1383 {
1384     unsigned long str_off;
1385     unsigned char *p_rom;
1386     unsigned short str_len;
1387 
1388     str_off = 0;
1389     str_len = strnlen(str, maxlen);
1390     p_rom = ctx->bios;
1391 
1392     for (; start <= end; ++start) {
1393         for (str_off = 0; str_off < str_len; ++str_off) {
1394             if (str[str_off] != *(p_rom + start + str_off))
1395                 break;
1396         }
1397 
1398         if (str_off == str_len || str[str_off] == 0)
1399             return p_rom + start;
1400     }
1401     return NULL;
1402 }
1403 
1404 static void atom_get_vbios_pn(struct atom_context *ctx)
1405 {
1406     unsigned char *p_rom;
1407     unsigned short off_to_vbios_str;
1408     unsigned char *vbios_str;
1409     int count;
1410 
1411     off_to_vbios_str = 0;
1412     p_rom = ctx->bios;
1413 
1414     if (*(p_rom + OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS) != 0) {
1415         off_to_vbios_str =
1416             *(unsigned short *)(p_rom + OFFSET_TO_GET_ATOMBIOS_STRING_START);
1417 
1418         vbios_str = (unsigned char *)(p_rom + off_to_vbios_str);
1419     } else {
1420         vbios_str = p_rom + OFFSET_TO_VBIOS_PART_NUMBER;
1421     }
1422 
1423     if (*vbios_str == 0) {
1424         vbios_str = atom_find_str_in_rom(ctx, BIOS_ATOM_PREFIX, 3, 1024, 64);
1425         if (vbios_str == NULL)
1426             vbios_str += sizeof(BIOS_ATOM_PREFIX) - 1;
1427     }
1428     if (vbios_str != NULL && *vbios_str == 0)
1429         vbios_str++;
1430 
1431     if (vbios_str != NULL) {
1432         count = 0;
1433         while ((count < BIOS_STRING_LENGTH) && vbios_str[count] >= ' ' &&
1434                vbios_str[count] <= 'z') {
1435             ctx->vbios_pn[count] = vbios_str[count];
1436             count++;
1437         }
1438 
1439         ctx->vbios_pn[count] = 0;
1440     }
1441 }
1442 
1443 static void atom_get_vbios_version(struct atom_context *ctx)
1444 {
1445     unsigned char *vbios_ver;
1446 
1447     /* find anchor ATOMBIOSBK-AMD */
1448     vbios_ver = atom_find_str_in_rom(ctx, BIOS_VERSION_PREFIX, 3, 1024, 64);
1449     if (vbios_ver != NULL) {
1450         /* skip ATOMBIOSBK-AMD VER */
1451         vbios_ver += 18;
1452         memcpy(ctx->vbios_ver_str, vbios_ver, STRLEN_NORMAL);
1453     } else {
1454         ctx->vbios_ver_str[0] = '\0';
1455     }
1456 }
1457 
1458 struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios)
1459 {
1460     int base;
1461     struct atom_context *ctx =
1462         kzalloc(sizeof(struct atom_context), GFP_KERNEL);
1463     char *str;
1464     struct _ATOM_ROM_HEADER *atom_rom_header;
1465     struct _ATOM_MASTER_DATA_TABLE *master_table;
1466     struct _ATOM_FIRMWARE_INFO *atom_fw_info;
1467     u16 idx;
1468 
1469     if (!ctx)
1470         return NULL;
1471 
1472     ctx->card = card;
1473     ctx->bios = bios;
1474 
1475     if (CU16(0) != ATOM_BIOS_MAGIC) {
1476         pr_info("Invalid BIOS magic\n");
1477         kfree(ctx);
1478         return NULL;
1479     }
1480     if (strncmp
1481         (CSTR(ATOM_ATI_MAGIC_PTR), ATOM_ATI_MAGIC,
1482          strlen(ATOM_ATI_MAGIC))) {
1483         pr_info("Invalid ATI magic\n");
1484         kfree(ctx);
1485         return NULL;
1486     }
1487 
1488     base = CU16(ATOM_ROM_TABLE_PTR);
1489     if (strncmp
1490         (CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC,
1491          strlen(ATOM_ROM_MAGIC))) {
1492         pr_info("Invalid ATOM magic\n");
1493         kfree(ctx);
1494         return NULL;
1495     }
1496 
1497     ctx->cmd_table = CU16(base + ATOM_ROM_CMD_PTR);
1498     ctx->data_table = CU16(base + ATOM_ROM_DATA_PTR);
1499     atom_index_iio(ctx, CU16(ctx->data_table + ATOM_DATA_IIO_PTR) + 4);
1500     if (!ctx->iio) {
1501         amdgpu_atom_destroy(ctx);
1502         return NULL;
1503     }
1504 
1505     idx = CU16(ATOM_ROM_PART_NUMBER_PTR);
1506     if (idx == 0)
1507         idx = 0x80;
1508 
1509     str = CSTR(idx);
1510     if (*str != '\0') {
1511         pr_info("ATOM BIOS: %s\n", str);
1512         strlcpy(ctx->vbios_version, str, sizeof(ctx->vbios_version));
1513     }
1514 
1515     atom_rom_header = (struct _ATOM_ROM_HEADER *)CSTR(base);
1516     if (atom_rom_header->usMasterDataTableOffset != 0) {
1517         master_table = (struct _ATOM_MASTER_DATA_TABLE *)
1518                 CSTR(atom_rom_header->usMasterDataTableOffset);
1519         if (master_table->ListOfDataTables.FirmwareInfo != 0) {
1520             atom_fw_info = (struct _ATOM_FIRMWARE_INFO *)
1521                     CSTR(master_table->ListOfDataTables.FirmwareInfo);
1522             ctx->version = atom_fw_info->ulFirmwareRevision;
1523         }
1524     }
1525 
1526     atom_get_vbios_name(ctx);
1527     atom_get_vbios_pn(ctx);
1528     atom_get_vbios_date(ctx);
1529     atom_get_vbios_version(ctx);
1530 
1531     return ctx;
1532 }
1533 
1534 int amdgpu_atom_asic_init(struct atom_context *ctx)
1535 {
1536     int hwi = CU16(ctx->data_table + ATOM_DATA_FWI_PTR);
1537     uint32_t ps[16];
1538     int ret;
1539 
1540     memset(ps, 0, 64);
1541 
1542     ps[0] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFSCLK_PTR));
1543     ps[1] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFMCLK_PTR));
1544     if (!ps[0] || !ps[1])
1545         return 1;
1546 
1547     if (!CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_INIT))
1548         return 1;
1549     ret = amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, ps);
1550     if (ret)
1551         return ret;
1552 
1553     memset(ps, 0, 64);
1554 
1555     return ret;
1556 }
1557 
1558 void amdgpu_atom_destroy(struct atom_context *ctx)
1559 {
1560     kfree(ctx->iio);
1561     kfree(ctx);
1562 }
1563 
1564 bool amdgpu_atom_parse_data_header(struct atom_context *ctx, int index,
1565                 uint16_t *size, uint8_t *frev, uint8_t *crev,
1566                 uint16_t *data_start)
1567 {
1568     int offset = index * 2 + 4;
1569     int idx = CU16(ctx->data_table + offset);
1570     u16 *mdt = (u16 *)(ctx->bios + ctx->data_table + 4);
1571 
1572     if (!mdt[index])
1573         return false;
1574 
1575     if (size)
1576         *size = CU16(idx);
1577     if (frev)
1578         *frev = CU8(idx + 2);
1579     if (crev)
1580         *crev = CU8(idx + 3);
1581     *data_start = idx;
1582     return true;
1583 }
1584 
1585 bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t *frev,
1586                uint8_t *crev)
1587 {
1588     int offset = index * 2 + 4;
1589     int idx = CU16(ctx->cmd_table + offset);
1590     u16 *mct = (u16 *)(ctx->bios + ctx->cmd_table + 4);
1591 
1592     if (!mct[index])
1593         return false;
1594 
1595     if (frev)
1596         *frev = CU8(idx + 2);
1597     if (crev)
1598         *crev = CU8(idx + 3);
1599     return true;
1600 }
1601
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