amd/amdgpu/athub_v3_0.c

0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #include "amdgpu.h"
0025 #include "athub_v3_0.h"
0026 #include "athub/athub_3_0_0_offset.h"
0027 #include "athub/athub_3_0_0_sh_mask.h"
0028 #include "navi10_enum.h"
0029 #include "soc15_common.h"
0030
0031 #define regATHUB_MISC_CNTL_V3_0_1           0x00d7
0032 #define regATHUB_MISC_CNTL_V3_0_1_BASE_IDX      0
0033
0034
0035 static uint32_t athub_v3_0_get_cg_cntl(struct amdgpu_device *adev)
0036 {
0037     uint32_t data;
0038
0039     switch (adev->ip_versions[ATHUB_HWIP][0]) {
0040     case IP_VERSION(3, 0, 1):
0041         data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1);
0042         break;
0043     default:
0044         data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);
0045         break;
0046     }
0047     return data;
0048 }
0049
0050 static void athub_v3_0_set_cg_cntl(struct amdgpu_device *adev, uint32_t data)
0051 {
0052     switch (adev->ip_versions[ATHUB_HWIP][0]) {
0053     case IP_VERSION(3, 0, 1):
0054         WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL_V3_0_1, data);
0055         break;
0056     default:
0057         WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL, data);
0058         break;
0059     }
0060 }
0061
0062 static void
0063 athub_v3_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
0064                         bool enable)
0065 {
0066     uint32_t def, data;
0067
0068     def = data = athub_v3_0_get_cg_cntl(adev);
0069
0070     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_MGCG))
0071         data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
0072     else
0073         data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
0074
0075     if (def != data)
0076         athub_v3_0_set_cg_cntl(adev, data);
0077 }
0078
0079 static void
0080 athub_v3_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
0081                        bool enable)
0082 {
0083     uint32_t def, data;
0084
0085     def = data = athub_v3_0_get_cg_cntl(adev);
0086
0087     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_LS))
0088         data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
0089     else
0090         data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
0091
0092     if (def != data)
0093         athub_v3_0_set_cg_cntl(adev, data);
0094 }
0095
0096 int athub_v3_0_set_clockgating(struct amdgpu_device *adev,
0097                    enum amd_clockgating_state state)
0098 {
0099     if (amdgpu_sriov_vf(adev))
0100         return 0;
0101
0102     switch (adev->ip_versions[ATHUB_HWIP][0]) {
0103     case IP_VERSION(3, 0, 0):
0104     case IP_VERSION(3, 0, 1):
0105     case IP_VERSION(3, 0, 2):
0106         athub_v3_0_update_medium_grain_clock_gating(adev,
0107                 state == AMD_CG_STATE_GATE);
0108         athub_v3_0_update_medium_grain_light_sleep(adev,
0109                 state == AMD_CG_STATE_GATE);
0110         break;
0111     default:
0112         break;
0113     }
0114
0115     return 0;
0116 }
0117
0118 void athub_v3_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)
0119 {
0120     int data;
0121
0122     /* AMD_CG_SUPPORT_ATHUB_MGCG */
0123     data = athub_v3_0_get_cg_cntl(adev);
0124     if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
0125         *flags |= AMD_CG_SUPPORT_ATHUB_MGCG;
0126
0127     /* AMD_CG_SUPPORT_ATHUB_LS */
0128     if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK)
0129         *flags |= AMD_CG_SUPPORT_ATHUB_LS;
0130 }