amd/amdgpu/athub_v2_1.c

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #include "amdgpu.h"
0025 #include "athub_v2_1.h"
0026
0027 #include "athub/athub_2_1_0_offset.h"
0028 #include "athub/athub_2_1_0_sh_mask.h"
0029
0030 #include "soc15_common.h"
0031
0032 static void
0033 athub_v2_1_update_medium_grain_clock_gating(struct amdgpu_device *adev,
0034                         bool enable)
0035 {
0036     uint32_t def, data;
0037
0038     def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
0039
0040     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
0041         data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
0042     else
0043         data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
0044
0045     if (def != data)
0046         WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
0047 }
0048
0049 static void
0050 athub_v2_1_update_medium_grain_light_sleep(struct amdgpu_device *adev,
0051                        bool enable)
0052 {
0053     uint32_t def, data;
0054
0055     def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
0056
0057     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
0058         (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
0059         data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
0060     else
0061         data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
0062
0063     if(def != data)
0064         WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
0065 }
0066
0067 int athub_v2_1_set_clockgating(struct amdgpu_device *adev,
0068                    enum amd_clockgating_state state)
0069 {
0070     if (amdgpu_sriov_vf(adev))
0071         return 0;
0072
0073     switch (adev->ip_versions[ATHUB_HWIP][0]) {
0074     case IP_VERSION(2, 1, 0):
0075     case IP_VERSION(2, 1, 1):
0076     case IP_VERSION(2, 1, 2):
0077     case IP_VERSION(2, 4, 0):
0078         athub_v2_1_update_medium_grain_clock_gating(adev, state == AMD_CG_STATE_GATE);
0079         athub_v2_1_update_medium_grain_light_sleep(adev, state == AMD_CG_STATE_GATE);
0080         break;
0081     default:
0082         break;
0083     }
0084
0085     return 0;
0086 }
0087
0088 void athub_v2_1_get_clockgating(struct amdgpu_device *adev, u64 *flags)
0089 {
0090     int data;
0091
0092     /* AMD_CG_SUPPORT_ATHUB_MGCG */
0093     data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
0094     if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
0095         *flags |= AMD_CG_SUPPORT_ATHUB_MGCG;
0096
0097     /* AMD_CG_SUPPORT_ATHUB_LS */
0098     if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK)
0099         *flags |= AMD_CG_SUPPORT_ATHUB_LS;
0100 }