amd/amdgpu/athub_v2_0.c

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #include "amdgpu.h"
0025 #include "athub_v2_0.h"
0026
0027 #include "athub/athub_2_0_0_offset.h"
0028 #include "athub/athub_2_0_0_sh_mask.h"
0029 #include "athub/athub_2_0_0_default.h"
0030
0031 #include "soc15_common.h"
0032
0033 static void
0034 athub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
0035                         bool enable)
0036 {
0037     uint32_t def, data;
0038
0039     if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
0040         return;
0041
0042     def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
0043
0044     if (enable)
0045         data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
0046     else
0047         data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
0048
0049     if (def != data)
0050         WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
0051 }
0052
0053 static void
0054 athub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
0055                        bool enable)
0056 {
0057     uint32_t def, data;
0058
0059     if (!((adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
0060            (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)))
0061         return;
0062
0063     def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
0064
0065     if (enable)
0066         data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
0067     else
0068         data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
0069
0070     if (def != data)
0071         WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
0072 }
0073
0074 int athub_v2_0_set_clockgating(struct amdgpu_device *adev,
0075                    enum amd_clockgating_state state)
0076 {
0077     if (amdgpu_sriov_vf(adev))
0078         return 0;
0079
0080     switch (adev->ip_versions[ATHUB_HWIP][0]) {
0081     case IP_VERSION(1, 3, 1):
0082     case IP_VERSION(2, 0, 0):
0083     case IP_VERSION(2, 0, 2):
0084         athub_v2_0_update_medium_grain_clock_gating(adev,
0085                 state == AMD_CG_STATE_GATE);
0086         athub_v2_0_update_medium_grain_light_sleep(adev,
0087                 state == AMD_CG_STATE_GATE);
0088         break;
0089     default:
0090         break;
0091     }
0092
0093     return 0;
0094 }
0095
0096 void athub_v2_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)
0097 {
0098     int data;
0099
0100     /* AMD_CG_SUPPORT_ATHUB_MGCG */
0101     data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
0102     if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
0103         *flags |= AMD_CG_SUPPORT_ATHUB_MGCG;
0104
0105     /* AMD_CG_SUPPORT_ATHUB_LS */
0106     if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK)
0107         *flags |= AMD_CG_SUPPORT_ATHUB_LS;
0108 }