amd/amdgpu/athub_v1_0.c

0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #include "amdgpu.h"
0024 #include "athub_v1_0.h"
0025
0026 #include "athub/athub_1_0_offset.h"
0027 #include "athub/athub_1_0_sh_mask.h"
0028 #include "vega10_enum.h"
0029
0030 #include "soc15_common.h"
0031
0032 static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev,
0033                            bool enable)
0034 {
0035     uint32_t def, data;
0036
0037     def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
0038
0039     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
0040         data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
0041     else
0042         data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
0043
0044     if (def != data)
0045         WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
0046 }
0047
0048 static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev,
0049                           bool enable)
0050 {
0051     uint32_t def, data;
0052
0053     def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
0054
0055     if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
0056         (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
0057         data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
0058     else
0059         data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
0060
0061     if(def != data)
0062         WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
0063 }
0064
0065 int athub_v1_0_set_clockgating(struct amdgpu_device *adev,
0066                    enum amd_clockgating_state state)
0067 {
0068     if (amdgpu_sriov_vf(adev))
0069         return 0;
0070
0071     switch (adev->ip_versions[ATHUB_HWIP][0]) {
0072     case IP_VERSION(9, 0, 0):
0073     case IP_VERSION(9, 1, 0):
0074     case IP_VERSION(9, 2, 0):
0075     case IP_VERSION(9, 3, 0):
0076     case IP_VERSION(9, 4, 0):
0077     case IP_VERSION(1, 5, 0):
0078         athub_update_medium_grain_clock_gating(adev,
0079                 state == AMD_CG_STATE_GATE);
0080         athub_update_medium_grain_light_sleep(adev,
0081                 state == AMD_CG_STATE_GATE);
0082         break;
0083     default:
0084         break;
0085     }
0086
0087     return 0;
0088 }
0089
0090 void athub_v1_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)
0091 {
0092     int data;
0093
0094     if (amdgpu_sriov_vf(adev))
0095         *flags = 0;
0096
0097     /* AMD_CG_SUPPORT_ATHUB_MGCG */
0098     data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
0099     if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
0100         *flags |= AMD_CG_SUPPORT_ATHUB_MGCG;
0101
0102     /* AMD_CG_SUPPORT_ATHUB_LS */
0103     if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK)
0104         *flags |= AMD_CG_SUPPORT_ATHUB_LS;
0105 }