amd/amdgpu/amdgv_sriovmsg.h

0001 /*
0002  * Copyright (c) 2018-2021 Advanced Micro Devices, Inc. All rights reserved.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a copy
0005  * of this software and associated documentation files (the "Software"), to deal
0006  * in the Software without restriction, including without limitation the rights
0007  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
0008  * copies of the Software, and to permit persons to whom the Software is
0009  * furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
0017  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0018  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
0019  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
0020  * THE SOFTWARE.
0021  */
0022
0023 #ifndef AMDGV_SRIOV_MSG__H_
0024 #define AMDGV_SRIOV_MSG__H_
0025
0026 /* unit in kilobytes */
0027 #define AMD_SRIOV_MSG_VBIOS_OFFSET       0
0028 #define AMD_SRIOV_MSG_VBIOS_SIZE_KB      64
0029 #define AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB AMD_SRIOV_MSG_VBIOS_SIZE_KB
0030 #define AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB   4
0031
0032 /*
0033  * layout
0034  * 0           64KB        65KB        66KB
0035  * |   VBIOS   |   PF2VF   |   VF2PF   |   Bad Page   | ...
0036  * |   64KB    |   1KB     |   1KB     |
0037  */
0038 #define AMD_SRIOV_MSG_SIZE_KB                   1
0039 #define AMD_SRIOV_MSG_PF2VF_OFFSET_KB           AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB
0040 #define AMD_SRIOV_MSG_VF2PF_OFFSET_KB           (AMD_SRIOV_MSG_PF2VF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB)
0041 #define AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB        (AMD_SRIOV_MSG_VF2PF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB)
0042
0043 /*
0044  * PF2VF history log:
0045  * v1 defined in amdgim
0046  * v2 current
0047  *
0048  * VF2PF history log:
0049  * v1 defined in amdgim
0050  * v2 defined in amdgim
0051  * v3 current
0052  */
0053 #define AMD_SRIOV_MSG_FW_VRAM_PF2VF_VER 2
0054 #define AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER 3
0055
0056 #define AMD_SRIOV_MSG_RESERVE_UCODE 24
0057
0058 #define AMD_SRIOV_MSG_RESERVE_VCN_INST 4
0059
0060 enum amd_sriov_ucode_engine_id {
0061     AMD_SRIOV_UCODE_ID_VCE = 0,
0062     AMD_SRIOV_UCODE_ID_UVD,
0063     AMD_SRIOV_UCODE_ID_MC,
0064     AMD_SRIOV_UCODE_ID_ME,
0065     AMD_SRIOV_UCODE_ID_PFP,
0066     AMD_SRIOV_UCODE_ID_CE,
0067     AMD_SRIOV_UCODE_ID_RLC,
0068     AMD_SRIOV_UCODE_ID_RLC_SRLC,
0069     AMD_SRIOV_UCODE_ID_RLC_SRLG,
0070     AMD_SRIOV_UCODE_ID_RLC_SRLS,
0071     AMD_SRIOV_UCODE_ID_MEC,
0072     AMD_SRIOV_UCODE_ID_MEC2,
0073     AMD_SRIOV_UCODE_ID_SOS,
0074     AMD_SRIOV_UCODE_ID_ASD,
0075     AMD_SRIOV_UCODE_ID_TA_RAS,
0076     AMD_SRIOV_UCODE_ID_TA_XGMI,
0077     AMD_SRIOV_UCODE_ID_SMC,
0078     AMD_SRIOV_UCODE_ID_SDMA,
0079     AMD_SRIOV_UCODE_ID_SDMA2,
0080     AMD_SRIOV_UCODE_ID_VCN,
0081     AMD_SRIOV_UCODE_ID_DMCU,
0082     AMD_SRIOV_UCODE_ID__MAX
0083 };
0084
0085 #pragma pack(push, 1) // PF2VF / VF2PF data areas are byte packed
0086
0087 union amd_sriov_msg_feature_flags {
0088     struct {
0089         uint32_t error_log_collect : 1;
0090         uint32_t host_load_ucodes  : 1;
0091         uint32_t host_flr_vramlost : 1;
0092         uint32_t mm_bw_management  : 1;
0093         uint32_t pp_one_vf_mode    : 1;
0094         uint32_t reg_indirect_acc  : 1;
0095         uint32_t reserved      : 26;
0096     } flags;
0097     uint32_t all;
0098 };
0099
0100 union amd_sriov_reg_access_flags {
0101     struct {
0102         uint32_t vf_reg_access_ih    : 1;
0103         uint32_t vf_reg_access_mmhub : 1;
0104         uint32_t vf_reg_access_gc    : 1;
0105         uint32_t reserved            : 29;
0106     } flags;
0107     uint32_t all;
0108 };
0109
0110 union amd_sriov_msg_os_info {
0111     struct {
0112         uint32_t windows  : 1;
0113         uint32_t reserved : 31;
0114     } info;
0115     uint32_t all;
0116 };
0117
0118 struct amd_sriov_msg_uuid_info {
0119     union {
0120         struct {
0121             uint32_t did    : 16;
0122             uint32_t fcn    : 8;
0123             uint32_t asic_7 : 8;
0124         };
0125         uint32_t time_low;
0126     };
0127
0128     struct {
0129         uint32_t time_mid  : 16;
0130         uint32_t time_high : 12;
0131         uint32_t version   : 4;
0132     };
0133
0134     struct {
0135         struct {
0136             uint8_t clk_seq_hi : 6;
0137             uint8_t variant    : 2;
0138         };
0139         union {
0140             uint8_t clk_seq_low;
0141             uint8_t asic_6;
0142         };
0143         uint16_t asic_4;
0144     };
0145
0146     uint32_t asic_0;
0147 };
0148
0149 struct amd_sriov_msg_pf2vf_info_header {
0150     /* the total structure size in byte */
0151     uint32_t size;
0152     /* version of this structure, written by the HOST */
0153     uint32_t version;
0154     /* reserved */
0155     uint32_t reserved[2];
0156 };
0157
0158 #define AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE (48)
0159 struct amd_sriov_msg_pf2vf_info {
0160     /* header contains size and version */
0161     struct amd_sriov_msg_pf2vf_info_header header;
0162     /* use private key from mailbox 2 to create checksum */
0163     uint32_t checksum;
0164     /* The features flags of the HOST driver supports */
0165     union amd_sriov_msg_feature_flags feature_flags;
0166     /* (max_width * max_height * fps) / (16 * 16) */
0167     uint32_t hevc_enc_max_mb_per_second;
0168     /* (max_width * max_height) / (16 * 16) */
0169     uint32_t hevc_enc_max_mb_per_frame;
0170     /* (max_width * max_height * fps) / (16 * 16) */
0171     uint32_t avc_enc_max_mb_per_second;
0172     /* (max_width * max_height) / (16 * 16) */
0173     uint32_t avc_enc_max_mb_per_frame;
0174     /* MEC FW position in BYTE from the start of VF visible frame buffer */
0175     uint64_t mecfw_offset;
0176     /* MEC FW size in BYTE */
0177     uint32_t mecfw_size;
0178     /* UVD FW position in BYTE from the start of VF visible frame buffer */
0179     uint64_t uvdfw_offset;
0180     /* UVD FW size in BYTE */
0181     uint32_t uvdfw_size;
0182     /* VCE FW position in BYTE from the start of VF visible frame buffer */
0183     uint64_t vcefw_offset;
0184     /* VCE FW size in BYTE */
0185     uint32_t vcefw_size;
0186     /* Bad pages block position in BYTE */
0187     uint32_t bp_block_offset_low;
0188     uint32_t bp_block_offset_high;
0189     /* Bad pages block size in BYTE */
0190     uint32_t bp_block_size;
0191     /* frequency for VF to update the VF2PF area in msec, 0 = manual */
0192     uint32_t vf2pf_update_interval_ms;
0193     /* identification in ROCm SMI */
0194     uint64_t uuid;
0195     uint32_t fcn_idx;
0196     /* flags to indicate which register access method VF should use */
0197     union amd_sriov_reg_access_flags reg_access_flags;
0198     /* MM BW management */
0199     struct {
0200         uint32_t decode_max_dimension_pixels;
0201         uint32_t decode_max_frame_pixels;
0202         uint32_t encode_max_dimension_pixels;
0203         uint32_t encode_max_frame_pixels;
0204     } mm_bw_management[AMD_SRIOV_MSG_RESERVE_VCN_INST];
0205     /* UUID info */
0206     struct amd_sriov_msg_uuid_info uuid_info;
0207     /* PCIE atomic ops support flag */
0208     uint32_t pcie_atomic_ops_support_flags;
0209     /* reserved */
0210     uint32_t reserved[256 - AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE];
0211 };
0212
0213 struct amd_sriov_msg_vf2pf_info_header {
0214     /* the total structure size in byte */
0215     uint32_t size;
0216     /* version of this structure, written by the guest */
0217     uint32_t version;
0218     /* reserved */
0219     uint32_t reserved[2];
0220 };
0221
0222 #define AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE (70)
0223 struct amd_sriov_msg_vf2pf_info {
0224     /* header contains size and version */
0225     struct amd_sriov_msg_vf2pf_info_header header;
0226     uint32_t checksum;
0227     /* driver version */
0228     uint8_t driver_version[64];
0229     /* driver certification, 1=WHQL, 0=None */
0230     uint32_t driver_cert;
0231     /* guest OS type and version */
0232     union amd_sriov_msg_os_info os_info;
0233     /* guest fb information in the unit of MB */
0234     uint32_t fb_usage;
0235     /* guest gfx engine usage percentage */
0236     uint32_t gfx_usage;
0237     /* guest gfx engine health percentage */
0238     uint32_t gfx_health;
0239     /* guest compute engine usage percentage */
0240     uint32_t compute_usage;
0241     /* guest compute engine health percentage */
0242     uint32_t compute_health;
0243     /* guest avc engine usage percentage. 0xffff means N/A */
0244     uint32_t avc_enc_usage;
0245     /* guest avc engine health percentage. 0xffff means N/A */
0246     uint32_t avc_enc_health;
0247     /* guest hevc engine usage percentage. 0xffff means N/A */
0248     uint32_t hevc_enc_usage;
0249     /* guest hevc engine usage percentage. 0xffff means N/A */
0250     uint32_t hevc_enc_health;
0251     /* combined encode/decode usage */
0252     uint32_t encode_usage;
0253     uint32_t decode_usage;
0254     /* Version of PF2VF that VF understands */
0255     uint32_t pf2vf_version_required;
0256     /* additional FB usage */
0257     uint32_t fb_vis_usage;
0258     uint32_t fb_vis_size;
0259     uint32_t fb_size;
0260     /* guest ucode data, each one is 1.25 Dword */
0261     struct {
0262         uint8_t id;
0263         uint32_t version;
0264     } ucode_info[AMD_SRIOV_MSG_RESERVE_UCODE];
0265     uint64_t dummy_page_addr;
0266
0267     /* reserved */
0268     uint32_t reserved[256 - AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE];
0269 };
0270
0271 /* mailbox message send from guest to host  */
0272 enum amd_sriov_mailbox_request_message {
0273     MB_REQ_MSG_REQ_GPU_INIT_ACCESS = 1,
0274     MB_REQ_MSG_REL_GPU_INIT_ACCESS,
0275     MB_REQ_MSG_REQ_GPU_FINI_ACCESS,
0276     MB_REQ_MSG_REL_GPU_FINI_ACCESS,
0277     MB_REQ_MSG_REQ_GPU_RESET_ACCESS,
0278     MB_REQ_MSG_REQ_GPU_INIT_DATA,
0279
0280     MB_REQ_MSG_LOG_VF_ERROR = 200,
0281 };
0282
0283 /* mailbox message send from host to guest  */
0284 enum amd_sriov_mailbox_response_message {
0285     MB_RES_MSG_CLR_MSG_BUF = 0,
0286     MB_RES_MSG_READY_TO_ACCESS_GPU = 1,
0287     MB_RES_MSG_FLR_NOTIFICATION,
0288     MB_RES_MSG_FLR_NOTIFICATION_COMPLETION,
0289     MB_RES_MSG_SUCCESS,
0290     MB_RES_MSG_FAIL,
0291     MB_RES_MSG_QUERY_ALIVE,
0292     MB_RES_MSG_GPU_INIT_DATA_READY,
0293
0294     MB_RES_MSG_TEXT_MESSAGE = 255
0295 };
0296
0297 /* version data stored in MAILBOX_MSGBUF_RCV_DW1 for future expansion */
0298 enum amd_sriov_gpu_init_data_version {
0299     GPU_INIT_DATA_READY_V1 = 1,
0300 };
0301
0302 #pragma pack(pop) // Restore previous packing option
0303
0304 /* checksum function between host and guest */
0305 unsigned int amd_sriov_msg_checksum(void *obj, unsigned long obj_size, unsigned int key,
0306                     unsigned int checksum);
0307
0308 /* assertion at compile time */
0309 #ifdef __linux__
0310 #define stringification(s)  _stringification(s)
0311 #define _stringification(s) #s
0312
0313 _Static_assert(
0314     sizeof(struct amd_sriov_msg_vf2pf_info) == AMD_SRIOV_MSG_SIZE_KB << 10,
0315     "amd_sriov_msg_vf2pf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB");
0316
0317 _Static_assert(
0318     sizeof(struct amd_sriov_msg_pf2vf_info) == AMD_SRIOV_MSG_SIZE_KB << 10,
0319     "amd_sriov_msg_pf2vf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB");
0320
0321 _Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE % 4 == 0,
0322            "AMD_SRIOV_MSG_RESERVE_UCODE must be multiple of 4");
0323
0324 _Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE > AMD_SRIOV_UCODE_ID__MAX,
0325            "AMD_SRIOV_MSG_RESERVE_UCODE must be bigger than AMD_SRIOV_UCODE_ID__MAX");
0326
0327 #undef _stringification
0328 #undef stringification
0329 #endif
0330
0331 #endif /* AMDGV_SRIOV_MSG__H_ */