amd/amdgpu/amdgpu_xgmi.h

0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  */
0022 #ifndef __AMDGPU_XGMI_H__
0023 #define __AMDGPU_XGMI_H__
0024
0025 #include <drm/task_barrier.h>
0026 #include "amdgpu_psp.h"
0027 #include "amdgpu_ras.h"
0028
0029 struct amdgpu_hive_info {
0030     struct kobject kobj;
0031     uint64_t hive_id;
0032     struct list_head device_list;
0033     struct list_head node;
0034     atomic_t number_devices;
0035     struct mutex hive_lock;
0036     int hi_req_count;
0037     struct amdgpu_device *hi_req_gpu;
0038     struct task_barrier tb;
0039     enum {
0040         AMDGPU_XGMI_PSTATE_MIN,
0041         AMDGPU_XGMI_PSTATE_MAX_VEGA20,
0042         AMDGPU_XGMI_PSTATE_UNKNOWN
0043     } pstate;
0044
0045     struct amdgpu_reset_domain *reset_domain;
0046 };
0047
0048 struct amdgpu_pcs_ras_field {
0049     const char *err_name;
0050     uint32_t pcs_err_mask;
0051     uint32_t pcs_err_shift;
0052 };
0053
0054 extern struct amdgpu_xgmi_ras  xgmi_ras;
0055 struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev);
0056 void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive);
0057 int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev);
0058 int amdgpu_xgmi_add_device(struct amdgpu_device *adev);
0059 int amdgpu_xgmi_remove_device(struct amdgpu_device *adev);
0060 int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate);
0061 int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev,
0062         struct amdgpu_device *peer_adev);
0063 int amdgpu_xgmi_get_num_links(struct amdgpu_device *adev,
0064         struct amdgpu_device *peer_adev);
0065 uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev,
0066                        uint64_t addr);
0067 static inline bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev,
0068         struct amdgpu_device *bo_adev)
0069 {
0070     return (amdgpu_use_xgmi_p2p &&
0071         adev != bo_adev &&
0072         adev->gmc.xgmi.hive_id &&
0073         adev->gmc.xgmi.hive_id == bo_adev->gmc.xgmi.hive_id);
0074 }
0075
0076 #endif