amd/amdgpu/amdgpu_vm_cpu.c

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  */
0022
0023 #include "amdgpu_vm.h"
0024 #include "amdgpu_object.h"
0025 #include "amdgpu_trace.h"
0026
0027 /**
0028  * amdgpu_vm_cpu_map_table - make sure new PDs/PTs are kmapped
0029  *
0030  * @table: newly allocated or validated PD/PT
0031  */
0032 static int amdgpu_vm_cpu_map_table(struct amdgpu_bo_vm *table)
0033 {
0034     return amdgpu_bo_kmap(&table->bo, NULL);
0035 }
0036
0037 /**
0038  * amdgpu_vm_cpu_prepare - prepare page table update with the CPU
0039  *
0040  * @p: see amdgpu_vm_update_params definition
0041  * @resv: reservation object with embedded fence
0042  * @sync_mode: synchronization mode
0043  *
0044  * Returns:
0045  * Negativ errno, 0 for success.
0046  */
0047 static int amdgpu_vm_cpu_prepare(struct amdgpu_vm_update_params *p,
0048                  struct dma_resv *resv,
0049                  enum amdgpu_sync_mode sync_mode)
0050 {
0051     if (!resv)
0052         return 0;
0053
0054     return amdgpu_bo_sync_wait_resv(p->adev, resv, sync_mode, p->vm, true);
0055 }
0056
0057 /**
0058  * amdgpu_vm_cpu_update - helper to update page tables via CPU
0059  *
0060  * @p: see amdgpu_vm_update_params definition
0061  * @vmbo: PD/PT to update
0062  * @pe: byte offset of the PDE/PTE, relative to start of PDB/PTB
0063  * @addr: dst addr to write into pe
0064  * @count: number of page entries to update
0065  * @incr: increase next addr by incr bytes
0066  * @flags: hw access flags
0067  *
0068  * Write count number of PT/PD entries directly.
0069  */
0070 static int amdgpu_vm_cpu_update(struct amdgpu_vm_update_params *p,
0071                 struct amdgpu_bo_vm *vmbo, uint64_t pe,
0072                 uint64_t addr, unsigned count, uint32_t incr,
0073                 uint64_t flags)
0074 {
0075     unsigned int i;
0076     uint64_t value;
0077     long r;
0078
0079     r = dma_resv_wait_timeout(vmbo->bo.tbo.base.resv, DMA_RESV_USAGE_KERNEL,
0080                   true, MAX_SCHEDULE_TIMEOUT);
0081     if (r < 0)
0082         return r;
0083
0084     pe += (unsigned long)amdgpu_bo_kptr(&vmbo->bo);
0085
0086     trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->immediate);
0087
0088     for (i = 0; i < count; i++) {
0089         value = p->pages_addr ?
0090             amdgpu_vm_map_gart(p->pages_addr, addr) :
0091             addr;
0092         amdgpu_gmc_set_pte_pde(p->adev, (void *)(uintptr_t)pe,
0093                        i, value, flags);
0094         addr += incr;
0095     }
0096     return 0;
0097 }
0098
0099 /**
0100  * amdgpu_vm_cpu_commit - commit page table update to the HW
0101  *
0102  * @p: see amdgpu_vm_update_params definition
0103  * @fence: unused
0104  *
0105  * Make sure that the hardware sees the page table updates.
0106  */
0107 static int amdgpu_vm_cpu_commit(struct amdgpu_vm_update_params *p,
0108                 struct dma_fence **fence)
0109 {
0110     /* Flush HDP */
0111     mb();
0112     amdgpu_device_flush_hdp(p->adev, NULL);
0113     return 0;
0114 }
0115
0116 const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs = {
0117     .map_table = amdgpu_vm_cpu_map_table,
0118     .prepare = amdgpu_vm_cpu_prepare,
0119     .update = amdgpu_vm_cpu_update,
0120     .commit = amdgpu_vm_cpu_commit
0121 };