amd/amdgpu/amdgpu_virt.h

0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Author: Monk.liu@amd.com
0023  */
0024 #ifndef AMDGPU_VIRT_H
0025 #define AMDGPU_VIRT_H
0026
0027 #include "amdgv_sriovmsg.h"
0028
0029 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS  (1 << 0) /* vBIOS is sr-iov ready */
0030 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV   (1 << 1) /* sr-iov is enabled on this GPU */
0031 #define AMDGPU_SRIOV_CAPS_IS_VF        (1 << 2) /* this GPU is a virtual function */
0032 #define AMDGPU_PASSTHROUGH_MODE        (1 << 3) /* thw whole GPU is pass through for VM */
0033 #define AMDGPU_SRIOV_CAPS_RUNTIME      (1 << 4) /* is out of full access mode */
0034
0035 /* flags for indirect register access path supported by rlcg for sriov */
0036 #define AMDGPU_RLCG_GC_WRITE_LEGACY    (0x8 << 28)
0037 #define AMDGPU_RLCG_GC_WRITE           (0x0 << 28)
0038 #define AMDGPU_RLCG_GC_READ            (0x1 << 28)
0039 #define AMDGPU_RLCG_MMHUB_WRITE        (0x2 << 28)
0040
0041 /* error code for indirect register access path supported by rlcg for sriov */
0042 #define AMDGPU_RLCG_VFGATE_DISABLED     0x4000000
0043 #define AMDGPU_RLCG_WRONG_OPERATION_TYPE    0x2000000
0044 #define AMDGPU_RLCG_REG_NOT_IN_RANGE        0x1000000
0045
0046 #define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK   0xFFFFF
0047
0048 /* all asic after AI use this offset */
0049 #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5
0050 /* tonga/fiji use this offset */
0051 #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503
0052
0053 enum amdgpu_sriov_vf_mode {
0054     SRIOV_VF_MODE_BARE_METAL = 0,
0055     SRIOV_VF_MODE_ONE_VF,
0056     SRIOV_VF_MODE_MULTI_VF,
0057 };
0058
0059 struct amdgpu_mm_table {
0060     struct amdgpu_bo    *bo;
0061     uint32_t        *cpu_addr;
0062     uint64_t        gpu_addr;
0063 };
0064
0065 #define AMDGPU_VF_ERROR_ENTRY_SIZE    16
0066
0067 /* struct error_entry - amdgpu VF error information. */
0068 struct amdgpu_vf_error_buffer {
0069     struct mutex lock;
0070     int read_count;
0071     int write_count;
0072     uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE];
0073     uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE];
0074     uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE];
0075 };
0076
0077 /**
0078  * struct amdgpu_virt_ops - amdgpu device virt operations
0079  */
0080 struct amdgpu_virt_ops {
0081     int (*req_full_gpu)(struct amdgpu_device *adev, bool init);
0082     int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
0083     int (*req_init_data)(struct amdgpu_device *adev);
0084     int (*reset_gpu)(struct amdgpu_device *adev);
0085     int (*wait_reset)(struct amdgpu_device *adev);
0086     void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3);
0087 };
0088
0089 /*
0090  * Firmware Reserve Frame buffer
0091  */
0092 struct amdgpu_virt_fw_reserve {
0093     struct amd_sriov_msg_pf2vf_info_header *p_pf2vf;
0094     struct amd_sriov_msg_vf2pf_info_header *p_vf2pf;
0095     unsigned int checksum_key;
0096 };
0097
0098 /*
0099  * Legacy GIM header
0100  *
0101  * Defination between PF and VF
0102  * Structures forcibly aligned to 4 to keep the same style as PF.
0103  */
0104 #define AMDGIM_DATAEXCHANGE_OFFSET      (64 * 1024)
0105
0106 #define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \
0107         (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))
0108
0109 enum AMDGIM_FEATURE_FLAG {
0110     /* GIM supports feature of Error log collecting */
0111     AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1,
0112     /* GIM supports feature of loading uCodes */
0113     AMDGIM_FEATURE_GIM_LOAD_UCODES   = 0x2,
0114     /* VRAM LOST by GIM */
0115     AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4,
0116     /* MM bandwidth */
0117     AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8,
0118     /* PP ONE VF MODE in GIM */
0119     AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
0120     /* Indirect Reg Access enabled */
0121     AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5),
0122 };
0123
0124 enum AMDGIM_REG_ACCESS_FLAG {
0125     /* Use PSP to program IH_RB_CNTL */
0126     AMDGIM_FEATURE_IH_REG_PSP_EN     = (1 << 0),
0127     /* Use RLC to program MMHUB regs */
0128     AMDGIM_FEATURE_MMHUB_REG_RLC_EN  = (1 << 1),
0129     /* Use RLC to program GC regs */
0130     AMDGIM_FEATURE_GC_REG_RLC_EN     = (1 << 2),
0131 };
0132
0133 struct amdgim_pf2vf_info_v1 {
0134     /* header contains size and version */
0135     struct amd_sriov_msg_pf2vf_info_header header;
0136     /* max_width * max_height */
0137     unsigned int uvd_enc_max_pixels_count;
0138     /* 16x16 pixels/sec, codec independent */
0139     unsigned int uvd_enc_max_bandwidth;
0140     /* max_width * max_height */
0141     unsigned int vce_enc_max_pixels_count;
0142     /* 16x16 pixels/sec, codec independent */
0143     unsigned int vce_enc_max_bandwidth;
0144     /* MEC FW position in kb from the start of visible frame buffer */
0145     unsigned int mecfw_kboffset;
0146     /* The features flags of the GIM driver supports. */
0147     unsigned int feature_flags;
0148     /* use private key from mailbox 2 to create chueksum */
0149     unsigned int checksum;
0150 } __aligned(4);
0151
0152 struct amdgim_vf2pf_info_v1 {
0153     /* header contains size and version */
0154     struct amd_sriov_msg_vf2pf_info_header header;
0155     /* driver version */
0156     char driver_version[64];
0157     /* driver certification, 1=WHQL, 0=None */
0158     unsigned int driver_cert;
0159     /* guest OS type and version: need a define */
0160     unsigned int os_info;
0161     /* in the unit of 1M */
0162     unsigned int fb_usage;
0163     /* guest gfx engine usage percentage */
0164     unsigned int gfx_usage;
0165     /* guest gfx engine health percentage */
0166     unsigned int gfx_health;
0167     /* guest compute engine usage percentage */
0168     unsigned int compute_usage;
0169     /* guest compute engine health percentage */
0170     unsigned int compute_health;
0171     /* guest vce engine usage percentage. 0xffff means N/A. */
0172     unsigned int vce_enc_usage;
0173     /* guest vce engine health percentage. 0xffff means N/A. */
0174     unsigned int vce_enc_health;
0175     /* guest uvd engine usage percentage. 0xffff means N/A. */
0176     unsigned int uvd_enc_usage;
0177     /* guest uvd engine usage percentage. 0xffff means N/A. */
0178     unsigned int uvd_enc_health;
0179     unsigned int checksum;
0180 } __aligned(4);
0181
0182 struct amdgim_vf2pf_info_v2 {
0183     /* header contains size and version */
0184     struct amd_sriov_msg_vf2pf_info_header header;
0185     uint32_t checksum;
0186     /* driver version */
0187     uint8_t driver_version[64];
0188     /* driver certification, 1=WHQL, 0=None */
0189     uint32_t driver_cert;
0190     /* guest OS type and version: need a define */
0191     uint32_t os_info;
0192     /* in the unit of 1M */
0193     uint32_t fb_usage;
0194     /* guest gfx engine usage percentage */
0195     uint32_t gfx_usage;
0196     /* guest gfx engine health percentage */
0197     uint32_t gfx_health;
0198     /* guest compute engine usage percentage */
0199     uint32_t compute_usage;
0200     /* guest compute engine health percentage */
0201     uint32_t compute_health;
0202     /* guest vce engine usage percentage. 0xffff means N/A. */
0203     uint32_t vce_enc_usage;
0204     /* guest vce engine health percentage. 0xffff means N/A. */
0205     uint32_t vce_enc_health;
0206     /* guest uvd engine usage percentage. 0xffff means N/A. */
0207     uint32_t uvd_enc_usage;
0208     /* guest uvd engine usage percentage. 0xffff means N/A. */
0209     uint32_t uvd_enc_health;
0210     uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)];
0211 } __aligned(4);
0212
0213 struct amdgpu_virt_ras_err_handler_data {
0214     /* point to bad page records array */
0215     struct eeprom_table_record *bps;
0216     /* point to reserved bo array */
0217     struct amdgpu_bo **bps_bo;
0218     /* the count of entries */
0219     int count;
0220     /* last reserved entry's index + 1 */
0221     int last_reserved;
0222 };
0223
0224 /* GPU virtualization */
0225 struct amdgpu_virt {
0226     uint32_t            caps;
0227     struct amdgpu_bo        *csa_obj;
0228     void                *csa_cpu_addr;
0229     bool chained_ib_support;
0230     uint32_t            reg_val_offs;
0231     struct amdgpu_irq_src       ack_irq;
0232     struct amdgpu_irq_src       rcv_irq;
0233     struct work_struct      flr_work;
0234     struct amdgpu_mm_table      mm_table;
0235     const struct amdgpu_virt_ops    *ops;
0236     struct amdgpu_vf_error_buffer   vf_errors;
0237     struct amdgpu_virt_fw_reserve   fw_reserve;
0238     uint32_t gim_feature;
0239     uint32_t reg_access_mode;
0240     int req_init_data_ver;
0241     bool tdr_debug;
0242     struct amdgpu_virt_ras_err_handler_data *virt_eh_data;
0243     bool ras_init_done;
0244     uint32_t reg_access;
0245
0246     /* vf2pf message */
0247     struct delayed_work vf2pf_work;
0248     uint32_t vf2pf_update_interval_ms;
0249
0250     /* multimedia bandwidth config */
0251     bool     is_mm_bw_enabled;
0252     uint32_t decode_max_dimension_pixels;
0253     uint32_t decode_max_frame_pixels;
0254     uint32_t encode_max_dimension_pixels;
0255     uint32_t encode_max_frame_pixels;
0256 };
0257
0258 struct amdgpu_video_codec_info;
0259
0260 #define amdgpu_sriov_enabled(adev) \
0261 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV)
0262
0263 #define amdgpu_sriov_vf(adev) \
0264 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF)
0265
0266 #define amdgpu_sriov_bios(adev) \
0267 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)
0268
0269 #define amdgpu_sriov_runtime(adev) \
0270 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME)
0271
0272 #define amdgpu_sriov_fullaccess(adev) \
0273 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))
0274
0275 #define amdgpu_sriov_reg_indirect_en(adev) \
0276 (amdgpu_sriov_vf((adev)) && \
0277     ((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS)))
0278
0279 #define amdgpu_sriov_reg_indirect_ih(adev) \
0280 (amdgpu_sriov_vf((adev)) && \
0281     ((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN)))
0282
0283 #define amdgpu_sriov_reg_indirect_mmhub(adev) \
0284 (amdgpu_sriov_vf((adev)) && \
0285     ((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN)))
0286
0287 #define amdgpu_sriov_reg_indirect_gc(adev) \
0288 (amdgpu_sriov_vf((adev)) && \
0289     ((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN)))
0290
0291 #define amdgpu_sriov_rlcg_error_report_enabled(adev) \
0292         (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev))
0293
0294 #define amdgpu_passthrough(adev) \
0295 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)
0296
0297 static inline bool is_virtual_machine(void)
0298 {
0299 #if defined(CONFIG_X86)
0300     return boot_cpu_has(X86_FEATURE_HYPERVISOR);
0301 #elif defined(CONFIG_ARM64)
0302     return !is_kernel_in_hyp_mode();
0303 #else
0304     return false;
0305 #endif
0306 }
0307
0308 #define amdgpu_sriov_is_pp_one_vf(adev) \
0309     ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)
0310 #define amdgpu_sriov_is_debug(adev) \
0311     ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug)
0312 #define amdgpu_sriov_is_normal(adev) \
0313     ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug))
0314 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
0315 void amdgpu_virt_init_setting(struct amdgpu_device *adev);
0316 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
0317                     uint32_t reg0, uint32_t rreg1,
0318                     uint32_t ref, uint32_t mask);
0319 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
0320 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
0321 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
0322 void amdgpu_virt_request_init_data(struct amdgpu_device *adev);
0323 int amdgpu_virt_wait_reset(struct amdgpu_device *adev);
0324 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
0325 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
0326 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);
0327 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
0328 void amdgpu_virt_exchange_data(struct amdgpu_device *adev);
0329 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev);
0330 void amdgpu_detect_virtualization(struct amdgpu_device *adev);
0331
0332 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);
0333 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev);
0334 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev);
0335
0336 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev);
0337
0338 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
0339             struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,
0340             struct amdgpu_video_codec_info *decode, uint32_t decode_array_size);
0341 void amdgpu_sriov_wreg(struct amdgpu_device *adev,
0342                u32 offset, u32 value,
0343                u32 acc_flags, u32 hwip);
0344 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
0345               u32 offset, u32 acc_flags, u32 hwip);
0346 #endif