amd/amdgpu/amdgpu_vce.h

0001 /*
0002  * Copyright 2014 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef __AMDGPU_VCE_H__
0025 #define __AMDGPU_VCE_H__
0026
0027 #define AMDGPU_MAX_VCE_HANDLES  16
0028 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
0029
0030 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
0031 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
0032
0033 #define AMDGPU_VCE_FW_53_45 ((53 << 24) | (45 << 16))
0034
0035 struct amdgpu_vce {
0036     struct amdgpu_bo    *vcpu_bo;
0037     uint64_t        gpu_addr;
0038     void            *cpu_addr;
0039     void            *saved_bo;
0040     unsigned        fw_version;
0041     unsigned        fb_version;
0042     atomic_t        handles[AMDGPU_MAX_VCE_HANDLES];
0043     struct drm_file     *filp[AMDGPU_MAX_VCE_HANDLES];
0044     uint32_t        img_size[AMDGPU_MAX_VCE_HANDLES];
0045     struct delayed_work idle_work;
0046     struct mutex        idle_mutex;
0047     const struct firmware   *fw;    /* VCE firmware */
0048     struct amdgpu_ring  ring[AMDGPU_MAX_VCE_RINGS];
0049     struct amdgpu_irq_src   irq;
0050     unsigned        harvest_config;
0051     struct drm_sched_entity entity;
0052     uint32_t                srbm_soft_reset;
0053     unsigned        num_rings;
0054 };
0055
0056 int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size);
0057 int amdgpu_vce_sw_fini(struct amdgpu_device *adev);
0058 int amdgpu_vce_entity_init(struct amdgpu_device *adev);
0059 int amdgpu_vce_suspend(struct amdgpu_device *adev);
0060 int amdgpu_vce_resume(struct amdgpu_device *adev);
0061 void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp);
0062 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, struct amdgpu_job *job,
0063                  struct amdgpu_ib *ib);
0064 int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p,
0065                 struct amdgpu_job *job,
0066                 struct amdgpu_ib *ib);
0067 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
0068                 struct amdgpu_ib *ib, uint32_t flags);
0069 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
0070                 unsigned flags);
0071 int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring);
0072 int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout);
0073 void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring);
0074 void amdgpu_vce_ring_end_use(struct amdgpu_ring *ring);
0075 unsigned amdgpu_vce_ring_get_emit_ib_size(struct amdgpu_ring *ring);
0076 unsigned amdgpu_vce_ring_get_dma_frame_size(struct amdgpu_ring *ring);
0077 enum amdgpu_ring_priority_level amdgpu_vce_get_ring_prio(int ring);
0078
0079 #endif