amd/amdgpu/amdgpu_uvd.h

0001 /*
0002  * Copyright 2014 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef __AMDGPU_UVD_H__
0025 #define __AMDGPU_UVD_H__
0026
0027 #define AMDGPU_DEFAULT_UVD_HANDLES  10
0028 #define AMDGPU_MAX_UVD_HANDLES      40
0029 #define AMDGPU_UVD_STACK_SIZE       (200*1024)
0030 #define AMDGPU_UVD_HEAP_SIZE        (256*1024)
0031 #define AMDGPU_UVD_SESSION_SIZE     (50*1024)
0032 #define AMDGPU_UVD_FIRMWARE_OFFSET  256
0033
0034 #define AMDGPU_MAX_UVD_INSTANCES            2
0035
0036 #define AMDGPU_UVD_FIRMWARE_SIZE(adev)    \
0037     (AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->ucode_size_bytes) + \
0038                    8) - AMDGPU_UVD_FIRMWARE_OFFSET)
0039
0040 struct amdgpu_uvd_inst {
0041     struct amdgpu_bo    *vcpu_bo;
0042     void            *cpu_addr;
0043     uint64_t        gpu_addr;
0044     void            *saved_bo;
0045     struct amdgpu_ring  ring;
0046     struct amdgpu_ring  ring_enc[AMDGPU_MAX_UVD_ENC_RINGS];
0047     struct amdgpu_irq_src   irq;
0048     uint32_t                srbm_soft_reset;
0049 };
0050
0051 #define AMDGPU_UVD_HARVEST_UVD0 (1 << 0)
0052 #define AMDGPU_UVD_HARVEST_UVD1 (1 << 1)
0053
0054 struct amdgpu_uvd {
0055     const struct firmware   *fw;    /* UVD firmware */
0056     unsigned        fw_version;
0057     unsigned        max_handles;
0058     unsigned        num_enc_rings;
0059     uint8_t         num_uvd_inst;
0060     bool            address_64_bit;
0061     bool            use_ctx_buf;
0062     struct amdgpu_uvd_inst  inst[AMDGPU_MAX_UVD_INSTANCES];
0063     struct drm_file     *filp[AMDGPU_MAX_UVD_HANDLES];
0064     atomic_t        handles[AMDGPU_MAX_UVD_HANDLES];
0065     struct drm_sched_entity entity;
0066     struct delayed_work idle_work;
0067     unsigned        harvest_config;
0068     /* store image width to adjust nb memory state */
0069     unsigned        decode_image_width;
0070     uint32_t                keyselect;
0071     struct amdgpu_bo    *ib_bo;
0072 };
0073
0074 int amdgpu_uvd_sw_init(struct amdgpu_device *adev);
0075 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev);
0076 int amdgpu_uvd_entity_init(struct amdgpu_device *adev);
0077 int amdgpu_uvd_suspend(struct amdgpu_device *adev);
0078 int amdgpu_uvd_resume(struct amdgpu_device *adev);
0079 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
0080                   struct dma_fence **fence);
0081 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
0082                    bool direct, struct dma_fence **fence);
0083 void amdgpu_uvd_free_handles(struct amdgpu_device *adev,
0084                  struct drm_file *filp);
0085 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser,
0086                  struct amdgpu_job *job,
0087                  struct amdgpu_ib *ib);
0088 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring);
0089 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring);
0090 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout);
0091 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev);
0092
0093 #endif