amd/amdgpu/amdgpu_umc.h

0001 /*
0002  * Copyright (C) 2019  Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included
0012  * in all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
0015  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
0018  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0019  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
0020  */
0021 #ifndef __AMDGPU_UMC_H__
0022 #define __AMDGPU_UMC_H__
0023 #include "amdgpu_ras.h"
0024
0025 /*
0026  * (addr / 256) * 4096, the higher 26 bits in ErrorAddr
0027  * is the index of 4KB block
0028  */
0029 #define ADDR_OF_4KB_BLOCK(addr)         (((addr) & ~0xffULL) << 4)
0030 /*
0031  * (addr / 256) * 8192, the higher 26 bits in ErrorAddr
0032  * is the index of 8KB block
0033  */
0034 #define ADDR_OF_8KB_BLOCK(addr)         (((addr) & ~0xffULL) << 5)
0035 /* channel index is the index of 256B block */
0036 #define ADDR_OF_256B_BLOCK(channel_index)   ((channel_index) << 8)
0037 /* offset in 256B block */
0038 #define OFFSET_IN_256B_BLOCK(addr)      ((addr) & 0xffULL)
0039
0040 #define LOOP_UMC_INST(umc_inst) for ((umc_inst) = 0; (umc_inst) < adev->umc.umc_inst_num; (umc_inst)++)
0041 #define LOOP_UMC_CH_INST(ch_inst) for ((ch_inst) = 0; (ch_inst) < adev->umc.channel_inst_num; (ch_inst)++)
0042 #define LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) LOOP_UMC_INST((umc_inst)) LOOP_UMC_CH_INST((ch_inst))
0043
0044 #define LOOP_UMC_NODE_INST(node_inst) \
0045         for ((node_inst) = 0; (node_inst) < adev->umc.node_inst_num; (node_inst)++)
0046
0047 #define LOOP_UMC_EACH_NODE_INST_AND_CH(node_inst, umc_inst, ch_inst) \
0048         LOOP_UMC_NODE_INST((node_inst)) LOOP_UMC_INST_AND_CH((umc_inst), (ch_inst))
0049
0050 struct amdgpu_umc_ras {
0051     struct amdgpu_ras_block_object ras_block;
0052     void (*err_cnt_init)(struct amdgpu_device *adev);
0053     bool (*query_ras_poison_mode)(struct amdgpu_device *adev);
0054     void (*ecc_info_query_ras_error_count)(struct amdgpu_device *adev,
0055                       void *ras_error_status);
0056     void (*ecc_info_query_ras_error_address)(struct amdgpu_device *adev,
0057                     void *ras_error_status);
0058 };
0059
0060 struct amdgpu_umc_funcs {
0061     void (*init_registers)(struct amdgpu_device *adev);
0062 };
0063
0064 struct amdgpu_umc {
0065     /* max error count in one ras query call */
0066     uint32_t max_ras_err_cnt_per_query;
0067     /* number of umc channel instance with memory map register access */
0068     uint32_t channel_inst_num;
0069     /* number of umc instance with memory map register access */
0070     uint32_t umc_inst_num;
0071
0072     /*number of umc node instance with memory map register access*/
0073     uint32_t node_inst_num;
0074
0075     /* UMC regiser per channel offset */
0076     uint32_t channel_offs;
0077     /* channel index table of interleaved memory */
0078     const uint32_t *channel_idx_tbl;
0079     struct ras_common_if *ras_if;
0080
0081     const struct amdgpu_umc_funcs *funcs;
0082     struct amdgpu_umc_ras *ras;
0083 };
0084
0085 int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
0086 int amdgpu_umc_poison_handler(struct amdgpu_device *adev,
0087         void *ras_error_status,
0088         bool reset);
0089 int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
0090         struct amdgpu_irq_src *source,
0091         struct amdgpu_iv_entry *entry);
0092 void amdgpu_umc_fill_error_record(struct ras_err_data *err_data,
0093         uint64_t err_addr,
0094         uint64_t retired_page,
0095         uint32_t channel_index,
0096         uint32_t umc_inst);
0097
0098 int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
0099         void *ras_error_status,
0100         struct amdgpu_iv_entry *entry);
0101 #endif