amd/amdgpu/amdgpu_ucode.h

0001 /*
0002  * Copyright 2012 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __AMDGPU_UCODE_H__
0024 #define __AMDGPU_UCODE_H__
0025
0026 #include "amdgpu_socbb.h"
0027
0028 struct common_firmware_header {
0029     uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
0030     uint32_t header_size_bytes; /* size of just the header in bytes */
0031     uint16_t header_version_major; /* header version */
0032     uint16_t header_version_minor; /* header version */
0033     uint16_t ip_version_major; /* IP version */
0034     uint16_t ip_version_minor; /* IP version */
0035     uint32_t ucode_version;
0036     uint32_t ucode_size_bytes; /* size of ucode in bytes */
0037     uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
0038     uint32_t crc32;  /* crc32 checksum of the payload */
0039 };
0040
0041 /* version_major=1, version_minor=0 */
0042 struct mc_firmware_header_v1_0 {
0043     struct common_firmware_header header;
0044     uint32_t io_debug_size_bytes; /* size of debug array in dwords */
0045     uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
0046 };
0047
0048 /* version_major=1, version_minor=0 */
0049 struct smc_firmware_header_v1_0 {
0050     struct common_firmware_header header;
0051     uint32_t ucode_start_addr;
0052 };
0053
0054 /* version_major=2, version_minor=0 */
0055 struct smc_firmware_header_v2_0 {
0056     struct smc_firmware_header_v1_0 v1_0;
0057     uint32_t ppt_offset_bytes; /* soft pptable offset */
0058     uint32_t ppt_size_bytes; /* soft pptable size */
0059 };
0060
0061 struct smc_soft_pptable_entry {
0062         uint32_t id;
0063         uint32_t ppt_offset_bytes;
0064         uint32_t ppt_size_bytes;
0065 };
0066
0067 /* version_major=2, version_minor=1 */
0068 struct smc_firmware_header_v2_1 {
0069         struct smc_firmware_header_v1_0 v1_0;
0070         uint32_t pptable_count;
0071         uint32_t pptable_entry_offset;
0072 };
0073
0074 struct psp_fw_legacy_bin_desc {
0075     uint32_t fw_version;
0076     uint32_t offset_bytes;
0077     uint32_t size_bytes;
0078 };
0079
0080 /* version_major=1, version_minor=0 */
0081 struct psp_firmware_header_v1_0 {
0082     struct common_firmware_header header;
0083     struct psp_fw_legacy_bin_desc sos;
0084 };
0085
0086 /* version_major=1, version_minor=1 */
0087 struct psp_firmware_header_v1_1 {
0088     struct psp_firmware_header_v1_0 v1_0;
0089     struct psp_fw_legacy_bin_desc toc;
0090     struct psp_fw_legacy_bin_desc kdb;
0091 };
0092
0093 /* version_major=1, version_minor=2 */
0094 struct psp_firmware_header_v1_2 {
0095     struct psp_firmware_header_v1_0 v1_0;
0096     struct psp_fw_legacy_bin_desc res;
0097     struct psp_fw_legacy_bin_desc kdb;
0098 };
0099
0100 /* version_major=1, version_minor=3 */
0101 struct psp_firmware_header_v1_3 {
0102     struct psp_firmware_header_v1_1 v1_1;
0103     struct psp_fw_legacy_bin_desc spl;
0104     struct psp_fw_legacy_bin_desc rl;
0105     struct psp_fw_legacy_bin_desc sys_drv_aux;
0106     struct psp_fw_legacy_bin_desc sos_aux;
0107 };
0108
0109 struct psp_fw_bin_desc {
0110     uint32_t fw_type;
0111     uint32_t fw_version;
0112     uint32_t offset_bytes;
0113     uint32_t size_bytes;
0114 };
0115
0116 enum psp_fw_type {
0117     PSP_FW_TYPE_UNKOWN,
0118     PSP_FW_TYPE_PSP_SOS,
0119     PSP_FW_TYPE_PSP_SYS_DRV,
0120     PSP_FW_TYPE_PSP_KDB,
0121     PSP_FW_TYPE_PSP_TOC,
0122     PSP_FW_TYPE_PSP_SPL,
0123     PSP_FW_TYPE_PSP_RL,
0124     PSP_FW_TYPE_PSP_SOC_DRV,
0125     PSP_FW_TYPE_PSP_INTF_DRV,
0126     PSP_FW_TYPE_PSP_DBG_DRV,
0127 };
0128
0129 /* version_major=2, version_minor=0 */
0130 struct psp_firmware_header_v2_0 {
0131     struct common_firmware_header header;
0132     uint32_t psp_fw_bin_count;
0133     struct psp_fw_bin_desc psp_fw_bin[];
0134 };
0135
0136 /* version_major=1, version_minor=0 */
0137 struct ta_firmware_header_v1_0 {
0138     struct common_firmware_header header;
0139     struct psp_fw_legacy_bin_desc xgmi;
0140     struct psp_fw_legacy_bin_desc ras;
0141     struct psp_fw_legacy_bin_desc hdcp;
0142     struct psp_fw_legacy_bin_desc dtm;
0143     struct psp_fw_legacy_bin_desc securedisplay;
0144 };
0145
0146 enum ta_fw_type {
0147     TA_FW_TYPE_UNKOWN,
0148     TA_FW_TYPE_PSP_ASD,
0149     TA_FW_TYPE_PSP_XGMI,
0150     TA_FW_TYPE_PSP_RAS,
0151     TA_FW_TYPE_PSP_HDCP,
0152     TA_FW_TYPE_PSP_DTM,
0153     TA_FW_TYPE_PSP_RAP,
0154     TA_FW_TYPE_PSP_SECUREDISPLAY,
0155     TA_FW_TYPE_MAX_INDEX,
0156 };
0157
0158 /* version_major=2, version_minor=0 */
0159 struct ta_firmware_header_v2_0 {
0160     struct common_firmware_header header;
0161     uint32_t ta_fw_bin_count;
0162     struct psp_fw_bin_desc ta_fw_bin[];
0163 };
0164
0165 /* version_major=1, version_minor=0 */
0166 struct gfx_firmware_header_v1_0 {
0167     struct common_firmware_header header;
0168     uint32_t ucode_feature_version;
0169     uint32_t jt_offset; /* jt location */
0170     uint32_t jt_size;  /* size of jt */
0171 };
0172
0173 /* version_major=2, version_minor=0 */
0174 struct gfx_firmware_header_v2_0 {
0175     struct common_firmware_header header;
0176     uint32_t ucode_feature_version;
0177     uint32_t ucode_size_bytes;
0178     uint32_t ucode_offset_bytes;
0179     uint32_t data_size_bytes;
0180     uint32_t data_offset_bytes;
0181     uint32_t ucode_start_addr_lo;
0182     uint32_t ucode_start_addr_hi;
0183 };
0184
0185 /* version_major=1, version_minor=0 */
0186 struct mes_firmware_header_v1_0 {
0187     struct common_firmware_header header;
0188     uint32_t mes_ucode_version;
0189     uint32_t mes_ucode_size_bytes;
0190     uint32_t mes_ucode_offset_bytes;
0191     uint32_t mes_ucode_data_version;
0192     uint32_t mes_ucode_data_size_bytes;
0193     uint32_t mes_ucode_data_offset_bytes;
0194     uint32_t mes_uc_start_addr_lo;
0195     uint32_t mes_uc_start_addr_hi;
0196     uint32_t mes_data_start_addr_lo;
0197     uint32_t mes_data_start_addr_hi;
0198 };
0199
0200 /* version_major=1, version_minor=0 */
0201 struct rlc_firmware_header_v1_0 {
0202     struct common_firmware_header header;
0203     uint32_t ucode_feature_version;
0204     uint32_t save_and_restore_offset;
0205     uint32_t clear_state_descriptor_offset;
0206     uint32_t avail_scratch_ram_locations;
0207     uint32_t master_pkt_description_offset;
0208 };
0209
0210 /* version_major=2, version_minor=0 */
0211 struct rlc_firmware_header_v2_0 {
0212     struct common_firmware_header header;
0213     uint32_t ucode_feature_version;
0214     uint32_t jt_offset; /* jt location */
0215     uint32_t jt_size;  /* size of jt */
0216     uint32_t save_and_restore_offset;
0217     uint32_t clear_state_descriptor_offset;
0218     uint32_t avail_scratch_ram_locations;
0219     uint32_t reg_restore_list_size;
0220     uint32_t reg_list_format_start;
0221     uint32_t reg_list_format_separate_start;
0222     uint32_t starting_offsets_start;
0223     uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */
0224     uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */
0225     uint32_t reg_list_size_bytes; /* size of reg list array in bytes */
0226     uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */
0227     uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */
0228     uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */
0229     uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */
0230     uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */
0231 };
0232
0233 /* version_major=2, version_minor=1 */
0234 struct rlc_firmware_header_v2_1 {
0235     struct rlc_firmware_header_v2_0 v2_0;
0236     uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */
0237     uint32_t save_restore_list_cntl_ucode_ver;
0238     uint32_t save_restore_list_cntl_feature_ver;
0239     uint32_t save_restore_list_cntl_size_bytes;
0240     uint32_t save_restore_list_cntl_offset_bytes;
0241     uint32_t save_restore_list_gpm_ucode_ver;
0242     uint32_t save_restore_list_gpm_feature_ver;
0243     uint32_t save_restore_list_gpm_size_bytes;
0244     uint32_t save_restore_list_gpm_offset_bytes;
0245     uint32_t save_restore_list_srm_ucode_ver;
0246     uint32_t save_restore_list_srm_feature_ver;
0247     uint32_t save_restore_list_srm_size_bytes;
0248     uint32_t save_restore_list_srm_offset_bytes;
0249 };
0250
0251 /* version_major=2, version_minor=2 */
0252 struct rlc_firmware_header_v2_2 {
0253     struct rlc_firmware_header_v2_1 v2_1;
0254     uint32_t rlc_iram_ucode_size_bytes;
0255     uint32_t rlc_iram_ucode_offset_bytes;
0256     uint32_t rlc_dram_ucode_size_bytes;
0257     uint32_t rlc_dram_ucode_offset_bytes;
0258 };
0259
0260 /* version_major=2, version_minor=3 */
0261 struct rlc_firmware_header_v2_3 {
0262     struct rlc_firmware_header_v2_2 v2_2;
0263     uint32_t rlcp_ucode_version;
0264     uint32_t rlcp_ucode_feature_version;
0265     uint32_t rlcp_ucode_size_bytes;
0266     uint32_t rlcp_ucode_offset_bytes;
0267     uint32_t rlcv_ucode_version;
0268     uint32_t rlcv_ucode_feature_version;
0269     uint32_t rlcv_ucode_size_bytes;
0270     uint32_t rlcv_ucode_offset_bytes;
0271 };
0272
0273 /* version_major=2, version_minor=4 */
0274 struct rlc_firmware_header_v2_4 {
0275     struct rlc_firmware_header_v2_3 v2_3;
0276     uint32_t global_tap_delays_ucode_size_bytes;
0277     uint32_t global_tap_delays_ucode_offset_bytes;
0278     uint32_t se0_tap_delays_ucode_size_bytes;
0279     uint32_t se0_tap_delays_ucode_offset_bytes;
0280     uint32_t se1_tap_delays_ucode_size_bytes;
0281     uint32_t se1_tap_delays_ucode_offset_bytes;
0282     uint32_t se2_tap_delays_ucode_size_bytes;
0283     uint32_t se2_tap_delays_ucode_offset_bytes;
0284     uint32_t se3_tap_delays_ucode_size_bytes;
0285     uint32_t se3_tap_delays_ucode_offset_bytes;
0286 };
0287
0288 /* version_major=1, version_minor=0 */
0289 struct sdma_firmware_header_v1_0 {
0290     struct common_firmware_header header;
0291     uint32_t ucode_feature_version;
0292     uint32_t ucode_change_version;
0293     uint32_t jt_offset; /* jt location */
0294     uint32_t jt_size; /* size of jt */
0295 };
0296
0297 /* version_major=1, version_minor=1 */
0298 struct sdma_firmware_header_v1_1 {
0299     struct sdma_firmware_header_v1_0 v1_0;
0300     uint32_t digest_size;
0301 };
0302
0303 /* version_major=2, version_minor=0 */
0304 struct sdma_firmware_header_v2_0 {
0305     struct common_firmware_header header;
0306     uint32_t ucode_feature_version;
0307     uint32_t ctx_ucode_size_bytes; /* context thread ucode size */
0308     uint32_t ctx_jt_offset; /* context thread jt location */
0309     uint32_t ctx_jt_size; /* context thread size of jt */
0310     uint32_t ctl_ucode_offset;
0311     uint32_t ctl_ucode_size_bytes; /* control thread ucode size */
0312     uint32_t ctl_jt_offset; /* control thread jt location */
0313     uint32_t ctl_jt_size; /* control thread size of jt */
0314 };
0315
0316 /* gpu info payload */
0317 struct gpu_info_firmware_v1_0 {
0318     uint32_t gc_num_se;
0319     uint32_t gc_num_cu_per_sh;
0320     uint32_t gc_num_sh_per_se;
0321     uint32_t gc_num_rb_per_se;
0322     uint32_t gc_num_tccs;
0323     uint32_t gc_num_gprs;
0324     uint32_t gc_num_max_gs_thds;
0325     uint32_t gc_gs_table_depth;
0326     uint32_t gc_gsprim_buff_depth;
0327     uint32_t gc_parameter_cache_depth;
0328     uint32_t gc_double_offchip_lds_buffer;
0329     uint32_t gc_wave_size;
0330     uint32_t gc_max_waves_per_simd;
0331     uint32_t gc_max_scratch_slots_per_cu;
0332     uint32_t gc_lds_size;
0333 };
0334
0335 struct gpu_info_firmware_v1_1 {
0336     struct gpu_info_firmware_v1_0 v1_0;
0337     uint32_t num_sc_per_sh;
0338     uint32_t num_packer_per_sc;
0339 };
0340
0341 /* gpu info payload
0342  * version_major=1, version_minor=1 */
0343 struct gpu_info_firmware_v1_2 {
0344     struct gpu_info_firmware_v1_1 v1_1;
0345     struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box;
0346 };
0347
0348 /* version_major=1, version_minor=0 */
0349 struct gpu_info_firmware_header_v1_0 {
0350     struct common_firmware_header header;
0351     uint16_t version_major; /* version */
0352     uint16_t version_minor; /* version */
0353 };
0354
0355 /* version_major=1, version_minor=0 */
0356 struct dmcu_firmware_header_v1_0 {
0357     struct common_firmware_header header;
0358     uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */
0359     uint32_t intv_size_bytes;  /* size of interrupt vectors, in bytes */
0360 };
0361
0362 /* version_major=1, version_minor=0 */
0363 struct dmcub_firmware_header_v1_0 {
0364     struct common_firmware_header header;
0365     uint32_t inst_const_bytes; /* size of instruction region, in bytes */
0366     uint32_t bss_data_bytes; /* size of bss/data region, in bytes */
0367 };
0368
0369 /* version_major=1, version_minor=0 */
0370 struct imu_firmware_header_v1_0 {
0371     struct common_firmware_header header;
0372     uint32_t imu_iram_ucode_size_bytes;
0373     uint32_t imu_iram_ucode_offset_bytes;
0374     uint32_t imu_dram_ucode_size_bytes;
0375     uint32_t imu_dram_ucode_offset_bytes;
0376 };
0377
0378 /* header is fixed size */
0379 union amdgpu_firmware_header {
0380     struct common_firmware_header common;
0381     struct mc_firmware_header_v1_0 mc;
0382     struct smc_firmware_header_v1_0 smc;
0383     struct smc_firmware_header_v2_0 smc_v2_0;
0384     struct psp_firmware_header_v1_0 psp;
0385     struct psp_firmware_header_v1_1 psp_v1_1;
0386     struct psp_firmware_header_v1_3 psp_v1_3;
0387     struct psp_firmware_header_v2_0 psp_v2_0;
0388     struct ta_firmware_header_v1_0 ta;
0389     struct ta_firmware_header_v2_0 ta_v2_0;
0390     struct gfx_firmware_header_v1_0 gfx;
0391     struct gfx_firmware_header_v2_0 gfx_v2_0;
0392     struct rlc_firmware_header_v1_0 rlc;
0393     struct rlc_firmware_header_v2_0 rlc_v2_0;
0394     struct rlc_firmware_header_v2_1 rlc_v2_1;
0395     struct rlc_firmware_header_v2_2 rlc_v2_2;
0396     struct rlc_firmware_header_v2_3 rlc_v2_3;
0397     struct rlc_firmware_header_v2_4 rlc_v2_4;
0398     struct sdma_firmware_header_v1_0 sdma;
0399     struct sdma_firmware_header_v1_1 sdma_v1_1;
0400     struct sdma_firmware_header_v2_0 sdma_v2_0;
0401     struct gpu_info_firmware_header_v1_0 gpu_info;
0402     struct dmcu_firmware_header_v1_0 dmcu;
0403     struct dmcub_firmware_header_v1_0 dmcub;
0404     struct imu_firmware_header_v1_0 imu;
0405     uint8_t raw[0x100];
0406 };
0407
0408 #define UCODE_MAX_PSP_PACKAGING ((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc))
0409
0410 /*
0411  * fw loading support
0412  */
0413 enum AMDGPU_UCODE_ID {
0414     AMDGPU_UCODE_ID_CAP = 0,
0415     AMDGPU_UCODE_ID_SDMA0,
0416     AMDGPU_UCODE_ID_SDMA1,
0417     AMDGPU_UCODE_ID_SDMA2,
0418     AMDGPU_UCODE_ID_SDMA3,
0419     AMDGPU_UCODE_ID_SDMA4,
0420     AMDGPU_UCODE_ID_SDMA5,
0421     AMDGPU_UCODE_ID_SDMA6,
0422     AMDGPU_UCODE_ID_SDMA7,
0423     AMDGPU_UCODE_ID_SDMA_UCODE_TH0,
0424     AMDGPU_UCODE_ID_SDMA_UCODE_TH1,
0425     AMDGPU_UCODE_ID_CP_CE,
0426     AMDGPU_UCODE_ID_CP_PFP,
0427     AMDGPU_UCODE_ID_CP_ME,
0428     AMDGPU_UCODE_ID_CP_RS64_PFP,
0429     AMDGPU_UCODE_ID_CP_RS64_ME,
0430     AMDGPU_UCODE_ID_CP_RS64_MEC,
0431     AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK,
0432     AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK,
0433     AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK,
0434     AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK,
0435     AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK,
0436     AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK,
0437     AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK,
0438     AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK,
0439     AMDGPU_UCODE_ID_CP_MEC1,
0440     AMDGPU_UCODE_ID_CP_MEC1_JT,
0441     AMDGPU_UCODE_ID_CP_MEC2,
0442     AMDGPU_UCODE_ID_CP_MEC2_JT,
0443     AMDGPU_UCODE_ID_CP_MES,
0444     AMDGPU_UCODE_ID_CP_MES_DATA,
0445     AMDGPU_UCODE_ID_CP_MES1,
0446     AMDGPU_UCODE_ID_CP_MES1_DATA,
0447     AMDGPU_UCODE_ID_IMU_I,
0448     AMDGPU_UCODE_ID_IMU_D,
0449     AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS,
0450     AMDGPU_UCODE_ID_SE0_TAP_DELAYS,
0451     AMDGPU_UCODE_ID_SE1_TAP_DELAYS,
0452     AMDGPU_UCODE_ID_SE2_TAP_DELAYS,
0453     AMDGPU_UCODE_ID_SE3_TAP_DELAYS,
0454     AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
0455     AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
0456     AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,
0457     AMDGPU_UCODE_ID_RLC_IRAM,
0458     AMDGPU_UCODE_ID_RLC_DRAM,
0459     AMDGPU_UCODE_ID_RLC_P,
0460     AMDGPU_UCODE_ID_RLC_V,
0461     AMDGPU_UCODE_ID_RLC_G,
0462     AMDGPU_UCODE_ID_STORAGE,
0463     AMDGPU_UCODE_ID_SMC,
0464     AMDGPU_UCODE_ID_PPTABLE,
0465     AMDGPU_UCODE_ID_UVD,
0466     AMDGPU_UCODE_ID_UVD1,
0467     AMDGPU_UCODE_ID_VCE,
0468     AMDGPU_UCODE_ID_VCN,
0469     AMDGPU_UCODE_ID_VCN1,
0470     AMDGPU_UCODE_ID_DMCU_ERAM,
0471     AMDGPU_UCODE_ID_DMCU_INTV,
0472     AMDGPU_UCODE_ID_VCN0_RAM,
0473     AMDGPU_UCODE_ID_VCN1_RAM,
0474     AMDGPU_UCODE_ID_DMCUB,
0475     AMDGPU_UCODE_ID_MAXIMUM,
0476 };
0477
0478 /* engine firmware status */
0479 enum AMDGPU_UCODE_STATUS {
0480     AMDGPU_UCODE_STATUS_INVALID,
0481     AMDGPU_UCODE_STATUS_NOT_LOADED,
0482     AMDGPU_UCODE_STATUS_LOADED,
0483 };
0484
0485 enum amdgpu_firmware_load_type {
0486     AMDGPU_FW_LOAD_DIRECT = 0,
0487     AMDGPU_FW_LOAD_PSP,
0488     AMDGPU_FW_LOAD_SMU,
0489     AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO,
0490 };
0491
0492 /* conform to smu_ucode_xfer_cz.h */
0493 #define AMDGPU_SDMA0_UCODE_LOADED   0x00000001
0494 #define AMDGPU_SDMA1_UCODE_LOADED   0x00000002
0495 #define AMDGPU_CPCE_UCODE_LOADED    0x00000004
0496 #define AMDGPU_CPPFP_UCODE_LOADED   0x00000008
0497 #define AMDGPU_CPME_UCODE_LOADED    0x00000010
0498 #define AMDGPU_CPMEC1_UCODE_LOADED  0x00000020
0499 #define AMDGPU_CPMEC2_UCODE_LOADED  0x00000040
0500 #define AMDGPU_CPRLC_UCODE_LOADED   0x00000100
0501
0502 /* amdgpu firmware info */
0503 struct amdgpu_firmware_info {
0504     /* ucode ID */
0505     enum AMDGPU_UCODE_ID ucode_id;
0506     /* request_firmware */
0507     const struct firmware *fw;
0508     /* starting mc address */
0509     uint64_t mc_addr;
0510     /* kernel linear address */
0511     void *kaddr;
0512     /* ucode_size_bytes */
0513     uint32_t ucode_size;
0514     /* starting tmr mc address */
0515     uint32_t tmr_mc_addr_lo;
0516     uint32_t tmr_mc_addr_hi;
0517 };
0518
0519 struct amdgpu_firmware {
0520     struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
0521     enum amdgpu_firmware_load_type load_type;
0522     struct amdgpu_bo *fw_buf;
0523     unsigned int fw_size;
0524     unsigned int max_ucodes;
0525     /* firmwares are loaded by psp instead of smu from vega10 */
0526     const struct amdgpu_psp_funcs *funcs;
0527     struct amdgpu_bo *rbuf;
0528     struct mutex mutex;
0529
0530     /* gpu info firmware data pointer */
0531     const struct firmware *gpu_info_fw;
0532
0533     void *fw_buf_ptr;
0534     uint64_t fw_buf_mc;
0535 };
0536
0537 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
0538 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
0539 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
0540 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
0541 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
0542 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr);
0543 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr);
0544 int amdgpu_ucode_validate(const struct firmware *fw);
0545 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
0546                 uint16_t hdr_major, uint16_t hdr_minor);
0547
0548 int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
0549 int amdgpu_ucode_create_bo(struct amdgpu_device *adev);
0550 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev);
0551 void amdgpu_ucode_free_bo(struct amdgpu_device *adev);
0552 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev);
0553
0554 enum amdgpu_firmware_load_type
0555 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type);
0556
0557 const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id);
0558
0559 void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len);
0560
0561 #endif