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0001 /*
0002  * Copyright 2014 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #include <linux/firmware.h>
0025 #include <linux/slab.h>
0026 #include <linux/module.h>
0027 
0028 #include "amdgpu.h"
0029 #include "amdgpu_ucode.h"
0030 
0031 static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr)
0032 {
0033     DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes));
0034     DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes));
0035     DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major));
0036     DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor));
0037     DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major));
0038     DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor));
0039     DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version));
0040     DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes));
0041     DRM_DEBUG("ucode_array_offset_bytes: %u\n",
0042           le32_to_cpu(hdr->ucode_array_offset_bytes));
0043     DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32));
0044 }
0045 
0046 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr)
0047 {
0048     uint16_t version_major = le16_to_cpu(hdr->header_version_major);
0049     uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
0050 
0051     DRM_DEBUG("MC\n");
0052     amdgpu_ucode_print_common_hdr(hdr);
0053 
0054     if (version_major == 1) {
0055         const struct mc_firmware_header_v1_0 *mc_hdr =
0056             container_of(hdr, struct mc_firmware_header_v1_0, header);
0057 
0058         DRM_DEBUG("io_debug_size_bytes: %u\n",
0059               le32_to_cpu(mc_hdr->io_debug_size_bytes));
0060         DRM_DEBUG("io_debug_array_offset_bytes: %u\n",
0061               le32_to_cpu(mc_hdr->io_debug_array_offset_bytes));
0062     } else {
0063         DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor);
0064     }
0065 }
0066 
0067 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr)
0068 {
0069     uint16_t version_major = le16_to_cpu(hdr->header_version_major);
0070     uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
0071     const struct smc_firmware_header_v1_0 *v1_0_hdr;
0072     const struct smc_firmware_header_v2_0 *v2_0_hdr;
0073     const struct smc_firmware_header_v2_1 *v2_1_hdr;
0074 
0075     DRM_DEBUG("SMC\n");
0076     amdgpu_ucode_print_common_hdr(hdr);
0077 
0078     if (version_major == 1) {
0079         v1_0_hdr = container_of(hdr, struct smc_firmware_header_v1_0, header);
0080         DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(v1_0_hdr->ucode_start_addr));
0081     } else if (version_major == 2) {
0082         switch (version_minor) {
0083         case 0:
0084             v2_0_hdr = container_of(hdr, struct smc_firmware_header_v2_0, v1_0.header);
0085             DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_offset_bytes));
0086             DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_size_bytes));
0087             break;
0088         case 1:
0089             v2_1_hdr = container_of(hdr, struct smc_firmware_header_v2_1, v1_0.header);
0090             DRM_DEBUG("pptable_count: %u\n", le32_to_cpu(v2_1_hdr->pptable_count));
0091             DRM_DEBUG("pptable_entry_offset: %u\n", le32_to_cpu(v2_1_hdr->pptable_entry_offset));
0092             break;
0093         default:
0094             break;
0095         }
0096 
0097     } else {
0098         DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor);
0099     }
0100 }
0101 
0102 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
0103 {
0104     uint16_t version_major = le16_to_cpu(hdr->header_version_major);
0105     uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
0106 
0107     DRM_DEBUG("GFX\n");
0108     amdgpu_ucode_print_common_hdr(hdr);
0109 
0110     if (version_major == 1) {
0111         const struct gfx_firmware_header_v1_0 *gfx_hdr =
0112             container_of(hdr, struct gfx_firmware_header_v1_0, header);
0113 
0114         DRM_DEBUG("ucode_feature_version: %u\n",
0115               le32_to_cpu(gfx_hdr->ucode_feature_version));
0116         DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset));
0117         DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size));
0118     } else if (version_major == 2) {
0119         const struct gfx_firmware_header_v2_0 *gfx_hdr =
0120             container_of(hdr, struct gfx_firmware_header_v2_0, header);
0121 
0122         DRM_DEBUG("ucode_feature_version: %u\n",
0123               le32_to_cpu(gfx_hdr->ucode_feature_version));
0124     } else {
0125         DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
0126     }
0127 }
0128 
0129 void amdgpu_ucode_print_imu_hdr(const struct common_firmware_header *hdr)
0130 {
0131     uint16_t version_major = le16_to_cpu(hdr->header_version_major);
0132     uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
0133 
0134     DRM_DEBUG("IMU\n");
0135     amdgpu_ucode_print_common_hdr(hdr);
0136 
0137     if (version_major != 1) {
0138         DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
0139     }
0140 }
0141 
0142 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
0143 {
0144     uint16_t version_major = le16_to_cpu(hdr->header_version_major);
0145     uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
0146 
0147     DRM_DEBUG("RLC\n");
0148     amdgpu_ucode_print_common_hdr(hdr);
0149 
0150     if (version_major == 1) {
0151         const struct rlc_firmware_header_v1_0 *rlc_hdr =
0152             container_of(hdr, struct rlc_firmware_header_v1_0, header);
0153 
0154         DRM_DEBUG("ucode_feature_version: %u\n",
0155               le32_to_cpu(rlc_hdr->ucode_feature_version));
0156         DRM_DEBUG("save_and_restore_offset: %u\n",
0157               le32_to_cpu(rlc_hdr->save_and_restore_offset));
0158         DRM_DEBUG("clear_state_descriptor_offset: %u\n",
0159               le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
0160         DRM_DEBUG("avail_scratch_ram_locations: %u\n",
0161               le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
0162         DRM_DEBUG("master_pkt_description_offset: %u\n",
0163               le32_to_cpu(rlc_hdr->master_pkt_description_offset));
0164     } else if (version_major == 2) {
0165         const struct rlc_firmware_header_v2_0 *rlc_hdr =
0166             container_of(hdr, struct rlc_firmware_header_v2_0, header);
0167 
0168         DRM_DEBUG("ucode_feature_version: %u\n",
0169               le32_to_cpu(rlc_hdr->ucode_feature_version));
0170         DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset));
0171         DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size));
0172         DRM_DEBUG("save_and_restore_offset: %u\n",
0173               le32_to_cpu(rlc_hdr->save_and_restore_offset));
0174         DRM_DEBUG("clear_state_descriptor_offset: %u\n",
0175               le32_to_cpu(rlc_hdr->clear_state_descriptor_offset));
0176         DRM_DEBUG("avail_scratch_ram_locations: %u\n",
0177               le32_to_cpu(rlc_hdr->avail_scratch_ram_locations));
0178         DRM_DEBUG("reg_restore_list_size: %u\n",
0179               le32_to_cpu(rlc_hdr->reg_restore_list_size));
0180         DRM_DEBUG("reg_list_format_start: %u\n",
0181               le32_to_cpu(rlc_hdr->reg_list_format_start));
0182         DRM_DEBUG("reg_list_format_separate_start: %u\n",
0183               le32_to_cpu(rlc_hdr->reg_list_format_separate_start));
0184         DRM_DEBUG("starting_offsets_start: %u\n",
0185               le32_to_cpu(rlc_hdr->starting_offsets_start));
0186         DRM_DEBUG("reg_list_format_size_bytes: %u\n",
0187               le32_to_cpu(rlc_hdr->reg_list_format_size_bytes));
0188         DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n",
0189               le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
0190         DRM_DEBUG("reg_list_size_bytes: %u\n",
0191               le32_to_cpu(rlc_hdr->reg_list_size_bytes));
0192         DRM_DEBUG("reg_list_array_offset_bytes: %u\n",
0193               le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
0194         DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n",
0195               le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes));
0196         DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n",
0197               le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes));
0198         DRM_DEBUG("reg_list_separate_size_bytes: %u\n",
0199               le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes));
0200         DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n",
0201               le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes));
0202         if (version_minor == 1) {
0203             const struct rlc_firmware_header_v2_1 *v2_1 =
0204                 container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0);
0205             DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n",
0206                   le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length));
0207             DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n",
0208                   le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver));
0209             DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n",
0210                   le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver));
0211             DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n",
0212                   le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes));
0213             DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n",
0214                   le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes));
0215             DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n",
0216                   le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver));
0217             DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n",
0218                   le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver));
0219             DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n",
0220                   le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes));
0221             DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n",
0222                   le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes));
0223             DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n",
0224                   le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver));
0225             DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n",
0226                   le32_to_cpu(v2_1->save_restore_list_srm_feature_ver));
0227             DRM_DEBUG("save_restore_list_srm_size_bytes %u\n",
0228                   le32_to_cpu(v2_1->save_restore_list_srm_size_bytes));
0229             DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n",
0230                   le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes));
0231         }
0232     } else {
0233         DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor);
0234     }
0235 }
0236 
0237 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr)
0238 {
0239     uint16_t version_major = le16_to_cpu(hdr->header_version_major);
0240     uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
0241 
0242     DRM_DEBUG("SDMA\n");
0243     amdgpu_ucode_print_common_hdr(hdr);
0244 
0245     if (version_major == 1) {
0246         const struct sdma_firmware_header_v1_0 *sdma_hdr =
0247             container_of(hdr, struct sdma_firmware_header_v1_0, header);
0248 
0249         DRM_DEBUG("ucode_feature_version: %u\n",
0250               le32_to_cpu(sdma_hdr->ucode_feature_version));
0251         DRM_DEBUG("ucode_change_version: %u\n",
0252               le32_to_cpu(sdma_hdr->ucode_change_version));
0253         DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset));
0254         DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size));
0255         if (version_minor >= 1) {
0256             const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr =
0257                 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0);
0258             DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size));
0259         }
0260     } else if (version_major == 2) {
0261         const struct sdma_firmware_header_v2_0 *sdma_hdr =
0262             container_of(hdr, struct sdma_firmware_header_v2_0, header);
0263 
0264         DRM_DEBUG("ucode_feature_version: %u\n",
0265               le32_to_cpu(sdma_hdr->ucode_feature_version));
0266         DRM_DEBUG("ctx_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_offset));
0267         DRM_DEBUG("ctx_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_size));
0268         DRM_DEBUG("ctl_ucode_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_ucode_offset));
0269         DRM_DEBUG("ctl_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_offset));
0270         DRM_DEBUG("ctl_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_size));
0271     } else {
0272         DRM_ERROR("Unknown SDMA ucode version: %u.%u\n",
0273               version_major, version_minor);
0274     }
0275 }
0276 
0277 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr)
0278 {
0279     uint16_t version_major = le16_to_cpu(hdr->header_version_major);
0280     uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
0281     uint32_t fw_index;
0282     const struct psp_fw_bin_desc *desc;
0283 
0284     DRM_DEBUG("PSP\n");
0285     amdgpu_ucode_print_common_hdr(hdr);
0286 
0287     if (version_major == 1) {
0288         const struct psp_firmware_header_v1_0 *psp_hdr =
0289             container_of(hdr, struct psp_firmware_header_v1_0, header);
0290 
0291         DRM_DEBUG("ucode_feature_version: %u\n",
0292               le32_to_cpu(psp_hdr->sos.fw_version));
0293         DRM_DEBUG("sos_offset_bytes: %u\n",
0294               le32_to_cpu(psp_hdr->sos.offset_bytes));
0295         DRM_DEBUG("sos_size_bytes: %u\n",
0296               le32_to_cpu(psp_hdr->sos.size_bytes));
0297         if (version_minor == 1) {
0298             const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
0299                 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
0300             DRM_DEBUG("toc_header_version: %u\n",
0301                   le32_to_cpu(psp_hdr_v1_1->toc.fw_version));
0302             DRM_DEBUG("toc_offset_bytes: %u\n",
0303                   le32_to_cpu(psp_hdr_v1_1->toc.offset_bytes));
0304             DRM_DEBUG("toc_size_bytes: %u\n",
0305                   le32_to_cpu(psp_hdr_v1_1->toc.size_bytes));
0306             DRM_DEBUG("kdb_header_version: %u\n",
0307                   le32_to_cpu(psp_hdr_v1_1->kdb.fw_version));
0308             DRM_DEBUG("kdb_offset_bytes: %u\n",
0309                   le32_to_cpu(psp_hdr_v1_1->kdb.offset_bytes));
0310             DRM_DEBUG("kdb_size_bytes: %u\n",
0311                   le32_to_cpu(psp_hdr_v1_1->kdb.size_bytes));
0312         }
0313         if (version_minor == 2) {
0314             const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 =
0315                 container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0);
0316             DRM_DEBUG("kdb_header_version: %u\n",
0317                   le32_to_cpu(psp_hdr_v1_2->kdb.fw_version));
0318             DRM_DEBUG("kdb_offset_bytes: %u\n",
0319                   le32_to_cpu(psp_hdr_v1_2->kdb.offset_bytes));
0320             DRM_DEBUG("kdb_size_bytes: %u\n",
0321                   le32_to_cpu(psp_hdr_v1_2->kdb.size_bytes));
0322         }
0323         if (version_minor == 3) {
0324             const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
0325                 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
0326             const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 =
0327                 container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1);
0328             DRM_DEBUG("toc_header_version: %u\n",
0329                   le32_to_cpu(psp_hdr_v1_3->v1_1.toc.fw_version));
0330             DRM_DEBUG("toc_offset_bytes: %u\n",
0331                   le32_to_cpu(psp_hdr_v1_3->v1_1.toc.offset_bytes));
0332             DRM_DEBUG("toc_size_bytes: %u\n",
0333                   le32_to_cpu(psp_hdr_v1_3->v1_1.toc.size_bytes));
0334             DRM_DEBUG("kdb_header_version: %u\n",
0335                   le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.fw_version));
0336             DRM_DEBUG("kdb_offset_bytes: %u\n",
0337                   le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.offset_bytes));
0338             DRM_DEBUG("kdb_size_bytes: %u\n",
0339                   le32_to_cpu(psp_hdr_v1_3->v1_1.kdb.size_bytes));
0340             DRM_DEBUG("spl_header_version: %u\n",
0341                   le32_to_cpu(psp_hdr_v1_3->spl.fw_version));
0342             DRM_DEBUG("spl_offset_bytes: %u\n",
0343                   le32_to_cpu(psp_hdr_v1_3->spl.offset_bytes));
0344             DRM_DEBUG("spl_size_bytes: %u\n",
0345                   le32_to_cpu(psp_hdr_v1_3->spl.size_bytes));
0346         }
0347     } else if (version_major == 2) {
0348         const struct psp_firmware_header_v2_0 *psp_hdr_v2_0 =
0349              container_of(hdr, struct psp_firmware_header_v2_0, header);
0350         for (fw_index = 0; fw_index < le32_to_cpu(psp_hdr_v2_0->psp_fw_bin_count); fw_index++) {
0351             desc = &(psp_hdr_v2_0->psp_fw_bin[fw_index]);
0352             switch (desc->fw_type) {
0353             case PSP_FW_TYPE_PSP_SOS:
0354                 DRM_DEBUG("psp_sos_version: %u\n",
0355                       le32_to_cpu(desc->fw_version));
0356                 DRM_DEBUG("psp_sos_size_bytes: %u\n",
0357                       le32_to_cpu(desc->size_bytes));
0358                 break;
0359             case PSP_FW_TYPE_PSP_SYS_DRV:
0360                 DRM_DEBUG("psp_sys_drv_version: %u\n",
0361                       le32_to_cpu(desc->fw_version));
0362                 DRM_DEBUG("psp_sys_drv_size_bytes: %u\n",
0363                       le32_to_cpu(desc->size_bytes));
0364                 break;
0365             case PSP_FW_TYPE_PSP_KDB:
0366                 DRM_DEBUG("psp_kdb_version: %u\n",
0367                       le32_to_cpu(desc->fw_version));
0368                 DRM_DEBUG("psp_kdb_size_bytes: %u\n",
0369                       le32_to_cpu(desc->size_bytes));
0370                 break;
0371             case PSP_FW_TYPE_PSP_TOC:
0372                 DRM_DEBUG("psp_toc_version: %u\n",
0373                       le32_to_cpu(desc->fw_version));
0374                 DRM_DEBUG("psp_toc_size_bytes: %u\n",
0375                       le32_to_cpu(desc->size_bytes));
0376                 break;
0377             case PSP_FW_TYPE_PSP_SPL:
0378                 DRM_DEBUG("psp_spl_version: %u\n",
0379                       le32_to_cpu(desc->fw_version));
0380                 DRM_DEBUG("psp_spl_size_bytes: %u\n",
0381                       le32_to_cpu(desc->size_bytes));
0382                 break;
0383             case PSP_FW_TYPE_PSP_RL:
0384                 DRM_DEBUG("psp_rl_version: %u\n",
0385                       le32_to_cpu(desc->fw_version));
0386                 DRM_DEBUG("psp_rl_size_bytes: %u\n",
0387                       le32_to_cpu(desc->size_bytes));
0388                 break;
0389             case PSP_FW_TYPE_PSP_SOC_DRV:
0390                 DRM_DEBUG("psp_soc_drv_version: %u\n",
0391                       le32_to_cpu(desc->fw_version));
0392                 DRM_DEBUG("psp_soc_drv_size_bytes: %u\n",
0393                       le32_to_cpu(desc->size_bytes));
0394                 break;
0395             case PSP_FW_TYPE_PSP_INTF_DRV:
0396                 DRM_DEBUG("psp_intf_drv_version: %u\n",
0397                       le32_to_cpu(desc->fw_version));
0398                 DRM_DEBUG("psp_intf_drv_size_bytes: %u\n",
0399                       le32_to_cpu(desc->size_bytes));
0400                 break;
0401             case PSP_FW_TYPE_PSP_DBG_DRV:
0402                 DRM_DEBUG("psp_dbg_drv_version: %u\n",
0403                       le32_to_cpu(desc->fw_version));
0404                 DRM_DEBUG("psp_dbg_drv_size_bytes: %u\n",
0405                       le32_to_cpu(desc->size_bytes));
0406                 break;
0407             default:
0408                 DRM_DEBUG("Unsupported PSP fw type: %d\n", desc->fw_type);
0409                 break;
0410             }
0411         }
0412     } else {
0413         DRM_ERROR("Unknown PSP ucode version: %u.%u\n",
0414               version_major, version_minor);
0415     }
0416 }
0417 
0418 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr)
0419 {
0420     uint16_t version_major = le16_to_cpu(hdr->header_version_major);
0421     uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
0422 
0423     DRM_DEBUG("GPU_INFO\n");
0424     amdgpu_ucode_print_common_hdr(hdr);
0425 
0426     if (version_major == 1) {
0427         const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr =
0428             container_of(hdr, struct gpu_info_firmware_header_v1_0, header);
0429 
0430         DRM_DEBUG("version_major: %u\n",
0431               le16_to_cpu(gpu_info_hdr->version_major));
0432         DRM_DEBUG("version_minor: %u\n",
0433               le16_to_cpu(gpu_info_hdr->version_minor));
0434     } else {
0435         DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor);
0436     }
0437 }
0438 
0439 int amdgpu_ucode_validate(const struct firmware *fw)
0440 {
0441     const struct common_firmware_header *hdr =
0442         (const struct common_firmware_header *)fw->data;
0443 
0444     if (fw->size == le32_to_cpu(hdr->size_bytes))
0445         return 0;
0446 
0447     return -EINVAL;
0448 }
0449 
0450 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
0451                 uint16_t hdr_major, uint16_t hdr_minor)
0452 {
0453     if ((hdr->common.header_version_major == hdr_major) &&
0454         (hdr->common.header_version_minor == hdr_minor))
0455         return true;
0456     return false;
0457 }
0458 
0459 enum amdgpu_firmware_load_type
0460 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
0461 {
0462     switch (adev->asic_type) {
0463 #ifdef CONFIG_DRM_AMDGPU_SI
0464     case CHIP_TAHITI:
0465     case CHIP_PITCAIRN:
0466     case CHIP_VERDE:
0467     case CHIP_OLAND:
0468     case CHIP_HAINAN:
0469         return AMDGPU_FW_LOAD_DIRECT;
0470 #endif
0471 #ifdef CONFIG_DRM_AMDGPU_CIK
0472     case CHIP_BONAIRE:
0473     case CHIP_KAVERI:
0474     case CHIP_KABINI:
0475     case CHIP_HAWAII:
0476     case CHIP_MULLINS:
0477         return AMDGPU_FW_LOAD_DIRECT;
0478 #endif
0479     case CHIP_TOPAZ:
0480     case CHIP_TONGA:
0481     case CHIP_FIJI:
0482     case CHIP_CARRIZO:
0483     case CHIP_STONEY:
0484     case CHIP_POLARIS10:
0485     case CHIP_POLARIS11:
0486     case CHIP_POLARIS12:
0487     case CHIP_VEGAM:
0488         return AMDGPU_FW_LOAD_SMU;
0489     case CHIP_CYAN_SKILLFISH:
0490         if (!(load_type &&
0491               adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2))
0492             return AMDGPU_FW_LOAD_DIRECT;
0493         else
0494             return AMDGPU_FW_LOAD_PSP;
0495     default:
0496         if (!load_type)
0497             return AMDGPU_FW_LOAD_DIRECT;
0498         else
0499             return AMDGPU_FW_LOAD_PSP;
0500     }
0501 }
0502 
0503 const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id)
0504 {
0505     switch (ucode_id) {
0506     case AMDGPU_UCODE_ID_SDMA0:
0507         return "SDMA0";
0508     case AMDGPU_UCODE_ID_SDMA1:
0509         return "SDMA1";
0510     case AMDGPU_UCODE_ID_SDMA2:
0511         return "SDMA2";
0512     case AMDGPU_UCODE_ID_SDMA3:
0513         return "SDMA3";
0514     case AMDGPU_UCODE_ID_SDMA4:
0515         return "SDMA4";
0516     case AMDGPU_UCODE_ID_SDMA5:
0517         return "SDMA5";
0518     case AMDGPU_UCODE_ID_SDMA6:
0519         return "SDMA6";
0520     case AMDGPU_UCODE_ID_SDMA7:
0521         return "SDMA7";
0522     case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
0523         return "SDMA_CTX";
0524     case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
0525         return "SDMA_CTL";
0526     case AMDGPU_UCODE_ID_CP_CE:
0527         return "CP_CE";
0528     case AMDGPU_UCODE_ID_CP_PFP:
0529         return "CP_PFP";
0530     case AMDGPU_UCODE_ID_CP_ME:
0531         return "CP_ME";
0532     case AMDGPU_UCODE_ID_CP_MEC1:
0533         return "CP_MEC1";
0534     case AMDGPU_UCODE_ID_CP_MEC1_JT:
0535         return "CP_MEC1_JT";
0536     case AMDGPU_UCODE_ID_CP_MEC2:
0537         return "CP_MEC2";
0538     case AMDGPU_UCODE_ID_CP_MEC2_JT:
0539         return "CP_MEC2_JT";
0540     case AMDGPU_UCODE_ID_CP_MES:
0541         return "CP_MES";
0542     case AMDGPU_UCODE_ID_CP_MES_DATA:
0543         return "CP_MES_DATA";
0544     case AMDGPU_UCODE_ID_CP_MES1:
0545         return "CP_MES_KIQ";
0546     case AMDGPU_UCODE_ID_CP_MES1_DATA:
0547         return "CP_MES_KIQ_DATA";
0548     case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
0549         return "RLC_RESTORE_LIST_CNTL";
0550     case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
0551         return "RLC_RESTORE_LIST_GPM_MEM";
0552     case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
0553         return "RLC_RESTORE_LIST_SRM_MEM";
0554     case AMDGPU_UCODE_ID_RLC_IRAM:
0555         return "RLC_IRAM";
0556     case AMDGPU_UCODE_ID_RLC_DRAM:
0557         return "RLC_DRAM";
0558     case AMDGPU_UCODE_ID_RLC_G:
0559         return "RLC_G";
0560     case AMDGPU_UCODE_ID_RLC_P:
0561         return "RLC_P";
0562     case AMDGPU_UCODE_ID_RLC_V:
0563         return "RLC_V";
0564     case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
0565         return "GLOBAL_TAP_DELAYS";
0566     case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
0567         return "SE0_TAP_DELAYS";
0568     case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
0569         return "SE1_TAP_DELAYS";
0570     case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
0571         return "SE2_TAP_DELAYS";
0572     case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
0573         return "SE3_TAP_DELAYS";
0574     case AMDGPU_UCODE_ID_IMU_I:
0575         return "IMU_I";
0576     case AMDGPU_UCODE_ID_IMU_D:
0577         return "IMU_D";
0578     case AMDGPU_UCODE_ID_STORAGE:
0579         return "STORAGE";
0580     case AMDGPU_UCODE_ID_SMC:
0581         return "SMC";
0582     case AMDGPU_UCODE_ID_PPTABLE:
0583         return "PPTABLE";
0584     case AMDGPU_UCODE_ID_UVD:
0585         return "UVD";
0586     case AMDGPU_UCODE_ID_UVD1:
0587         return "UVD1";
0588     case AMDGPU_UCODE_ID_VCE:
0589         return "VCE";
0590     case AMDGPU_UCODE_ID_VCN:
0591         return "VCN";
0592     case AMDGPU_UCODE_ID_VCN1:
0593         return "VCN1";
0594     case AMDGPU_UCODE_ID_DMCU_ERAM:
0595         return "DMCU_ERAM";
0596     case AMDGPU_UCODE_ID_DMCU_INTV:
0597         return "DMCU_INTV";
0598     case AMDGPU_UCODE_ID_VCN0_RAM:
0599         return "VCN0_RAM";
0600     case AMDGPU_UCODE_ID_VCN1_RAM:
0601         return "VCN1_RAM";
0602     case AMDGPU_UCODE_ID_DMCUB:
0603         return "DMCUB";
0604     default:
0605         return "UNKNOWN UCODE";
0606     }
0607 }
0608 
0609 #define FW_VERSION_ATTR(name, mode, field)              \
0610 static ssize_t show_##name(struct device *dev,              \
0611               struct device_attribute *attr,        \
0612               char *buf)                    \
0613 {                                   \
0614     struct drm_device *ddev = dev_get_drvdata(dev);         \
0615     struct amdgpu_device *adev = drm_to_adev(ddev);         \
0616                                     \
0617     return sysfs_emit(buf, "0x%08x\n", adev->field);    \
0618 }                                   \
0619 static DEVICE_ATTR(name, mode, show_##name, NULL)
0620 
0621 FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version);
0622 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version);
0623 FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version);
0624 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
0625 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
0626 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
0627 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
0628 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
0629 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
0630 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
0631 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
0632 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
0633 FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos.fw_version);
0634 FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_context.bin_desc.fw_version);
0635 FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ras_context.context.bin_desc.fw_version);
0636 FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.xgmi_context.context.bin_desc.fw_version);
0637 FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version);
0638 FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version);
0639 FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version);
0640 FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version);
0641 FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version);
0642 
0643 static struct attribute *fw_attrs[] = {
0644     &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr,
0645     &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr,
0646     &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr,
0647     &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr,
0648     &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr,
0649     &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr,
0650     &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr,
0651     &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr,
0652     &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr,
0653     &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr,
0654     &dev_attr_dmcu_fw_version.attr, NULL
0655 };
0656 
0657 static const struct attribute_group fw_attr_group = {
0658     .name = "fw_version",
0659     .attrs = fw_attrs
0660 };
0661 
0662 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev)
0663 {
0664     return sysfs_create_group(&adev->dev->kobj, &fw_attr_group);
0665 }
0666 
0667 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev)
0668 {
0669     sysfs_remove_group(&adev->dev->kobj, &fw_attr_group);
0670 }
0671 
0672 static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev,
0673                        struct amdgpu_firmware_info *ucode,
0674                        uint64_t mc_addr, void *kptr)
0675 {
0676     const struct common_firmware_header *header = NULL;
0677     const struct gfx_firmware_header_v1_0 *cp_hdr = NULL;
0678     const struct gfx_firmware_header_v2_0 *cpv2_hdr = NULL;
0679     const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL;
0680     const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL;
0681     const struct mes_firmware_header_v1_0 *mes_hdr = NULL;
0682     const struct sdma_firmware_header_v2_0 *sdma_hdr = NULL;
0683     const struct imu_firmware_header_v1_0 *imu_hdr = NULL;
0684     u8 *ucode_addr;
0685 
0686     if (NULL == ucode->fw)
0687         return 0;
0688 
0689     ucode->mc_addr = mc_addr;
0690     ucode->kaddr = kptr;
0691 
0692     if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE)
0693         return 0;
0694 
0695     header = (const struct common_firmware_header *)ucode->fw->data;
0696     cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
0697     cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)ucode->fw->data;
0698     dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data;
0699     dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data;
0700     mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data;
0701     sdma_hdr = (const struct sdma_firmware_header_v2_0 *)ucode->fw->data;
0702     imu_hdr = (const struct imu_firmware_header_v1_0 *)ucode->fw->data;
0703 
0704     if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
0705         switch (ucode->ucode_id) {
0706         case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
0707             ucode->ucode_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes);
0708             ucode_addr = (u8 *)ucode->fw->data +
0709                 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes);
0710             break;
0711         case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
0712             ucode->ucode_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes);
0713             ucode_addr = (u8 *)ucode->fw->data +
0714                 le32_to_cpu(sdma_hdr->ctl_ucode_offset);
0715             break;
0716         case AMDGPU_UCODE_ID_CP_MEC1:
0717         case AMDGPU_UCODE_ID_CP_MEC2:
0718             ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
0719                 le32_to_cpu(cp_hdr->jt_size) * 4;
0720             ucode_addr = (u8 *)ucode->fw->data +
0721                 le32_to_cpu(header->ucode_array_offset_bytes);
0722             break;
0723         case AMDGPU_UCODE_ID_CP_MEC1_JT:
0724         case AMDGPU_UCODE_ID_CP_MEC2_JT:
0725             ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4;
0726             ucode_addr = (u8 *)ucode->fw->data +
0727                 le32_to_cpu(header->ucode_array_offset_bytes) +
0728                 le32_to_cpu(cp_hdr->jt_offset) * 4;
0729             break;
0730         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
0731             ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes;
0732             ucode_addr = adev->gfx.rlc.save_restore_list_cntl;
0733             break;
0734         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
0735             ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes;
0736             ucode_addr = adev->gfx.rlc.save_restore_list_gpm;
0737             break;
0738         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
0739             ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes;
0740             ucode_addr = adev->gfx.rlc.save_restore_list_srm;
0741             break;
0742         case AMDGPU_UCODE_ID_RLC_IRAM:
0743             ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes;
0744             ucode_addr = adev->gfx.rlc.rlc_iram_ucode;
0745             break;
0746         case AMDGPU_UCODE_ID_RLC_DRAM:
0747             ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes;
0748             ucode_addr = adev->gfx.rlc.rlc_dram_ucode;
0749             break;
0750         case AMDGPU_UCODE_ID_RLC_P:
0751             ucode->ucode_size = adev->gfx.rlc.rlcp_ucode_size_bytes;
0752             ucode_addr = adev->gfx.rlc.rlcp_ucode;
0753             break;
0754         case AMDGPU_UCODE_ID_RLC_V:
0755             ucode->ucode_size = adev->gfx.rlc.rlcv_ucode_size_bytes;
0756             ucode_addr = adev->gfx.rlc.rlcv_ucode;
0757             break;
0758         case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
0759             ucode->ucode_size = adev->gfx.rlc.global_tap_delays_ucode_size_bytes;
0760             ucode_addr = adev->gfx.rlc.global_tap_delays_ucode;
0761             break;
0762         case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
0763             ucode->ucode_size = adev->gfx.rlc.se0_tap_delays_ucode_size_bytes;
0764             ucode_addr = adev->gfx.rlc.se0_tap_delays_ucode;
0765             break;
0766         case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
0767             ucode->ucode_size = adev->gfx.rlc.se1_tap_delays_ucode_size_bytes;
0768             ucode_addr = adev->gfx.rlc.se1_tap_delays_ucode;
0769             break;
0770         case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
0771             ucode->ucode_size = adev->gfx.rlc.se2_tap_delays_ucode_size_bytes;
0772             ucode_addr = adev->gfx.rlc.se2_tap_delays_ucode;
0773             break;
0774         case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
0775             ucode->ucode_size = adev->gfx.rlc.se3_tap_delays_ucode_size_bytes;
0776             ucode_addr = adev->gfx.rlc.se3_tap_delays_ucode;
0777             break;
0778         case AMDGPU_UCODE_ID_CP_MES:
0779             ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
0780             ucode_addr = (u8 *)ucode->fw->data +
0781                 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes);
0782             break;
0783         case AMDGPU_UCODE_ID_CP_MES_DATA:
0784             ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
0785             ucode_addr = (u8 *)ucode->fw->data +
0786                 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes);
0787             break;
0788         case AMDGPU_UCODE_ID_CP_MES1:
0789             ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
0790             ucode_addr = (u8 *)ucode->fw->data +
0791                 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes);
0792             break;
0793         case AMDGPU_UCODE_ID_CP_MES1_DATA:
0794             ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
0795             ucode_addr = (u8 *)ucode->fw->data +
0796                 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes);
0797             break;
0798         case AMDGPU_UCODE_ID_DMCU_ERAM:
0799             ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) -
0800                 le32_to_cpu(dmcu_hdr->intv_size_bytes);
0801             ucode_addr = (u8 *)ucode->fw->data +
0802                 le32_to_cpu(header->ucode_array_offset_bytes);
0803             break;
0804         case AMDGPU_UCODE_ID_DMCU_INTV:
0805             ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes);
0806             ucode_addr = (u8 *)ucode->fw->data +
0807                 le32_to_cpu(header->ucode_array_offset_bytes) +
0808                 le32_to_cpu(dmcu_hdr->intv_offset_bytes);
0809             break;
0810         case AMDGPU_UCODE_ID_DMCUB:
0811             ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes);
0812             ucode_addr = (u8 *)ucode->fw->data +
0813                 le32_to_cpu(header->ucode_array_offset_bytes);
0814             break;
0815         case AMDGPU_UCODE_ID_PPTABLE:
0816             ucode->ucode_size = ucode->fw->size;
0817             ucode_addr = (u8 *)ucode->fw->data;
0818             break;
0819         case AMDGPU_UCODE_ID_IMU_I:
0820             ucode->ucode_size = le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes);
0821             ucode_addr = (u8 *)ucode->fw->data +
0822                 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes);
0823             break;
0824         case AMDGPU_UCODE_ID_IMU_D:
0825             ucode->ucode_size = le32_to_cpu(imu_hdr->imu_dram_ucode_size_bytes);
0826             ucode_addr = (u8 *)ucode->fw->data +
0827                 le32_to_cpu(imu_hdr->header.ucode_array_offset_bytes) +
0828                 le32_to_cpu(imu_hdr->imu_iram_ucode_size_bytes);
0829             break;
0830         case AMDGPU_UCODE_ID_CP_RS64_PFP:
0831             ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
0832             ucode_addr = (u8 *)ucode->fw->data +
0833                 le32_to_cpu(header->ucode_array_offset_bytes);
0834             break;
0835         case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
0836             ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
0837             ucode_addr = (u8 *)ucode->fw->data +
0838                 le32_to_cpu(cpv2_hdr->data_offset_bytes);
0839             break;
0840         case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
0841             ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
0842             ucode_addr = (u8 *)ucode->fw->data +
0843                 le32_to_cpu(cpv2_hdr->data_offset_bytes);
0844             break;
0845         case AMDGPU_UCODE_ID_CP_RS64_ME:
0846             ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
0847             ucode_addr = (u8 *)ucode->fw->data +
0848                 le32_to_cpu(header->ucode_array_offset_bytes);
0849             break;
0850         case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
0851             ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
0852             ucode_addr = (u8 *)ucode->fw->data +
0853                 le32_to_cpu(cpv2_hdr->data_offset_bytes);
0854             break;
0855         case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
0856             ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
0857             ucode_addr = (u8 *)ucode->fw->data +
0858                 le32_to_cpu(cpv2_hdr->data_offset_bytes);
0859             break;
0860         case AMDGPU_UCODE_ID_CP_RS64_MEC:
0861             ucode->ucode_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
0862             ucode_addr = (u8 *)ucode->fw->data +
0863                 le32_to_cpu(header->ucode_array_offset_bytes);
0864             break;
0865         case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
0866             ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
0867             ucode_addr = (u8 *)ucode->fw->data +
0868                 le32_to_cpu(cpv2_hdr->data_offset_bytes);
0869             break;
0870         case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
0871             ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
0872             ucode_addr = (u8 *)ucode->fw->data +
0873                 le32_to_cpu(cpv2_hdr->data_offset_bytes);
0874             break;
0875         case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
0876             ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
0877             ucode_addr = (u8 *)ucode->fw->data +
0878                 le32_to_cpu(cpv2_hdr->data_offset_bytes);
0879             break;
0880         case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
0881             ucode->ucode_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
0882             ucode_addr = (u8 *)ucode->fw->data +
0883                 le32_to_cpu(cpv2_hdr->data_offset_bytes);
0884             break;
0885         default:
0886             ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
0887             ucode_addr = (u8 *)ucode->fw->data +
0888                 le32_to_cpu(header->ucode_array_offset_bytes);
0889             break;
0890         }
0891     } else {
0892         ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes);
0893         ucode_addr = (u8 *)ucode->fw->data +
0894             le32_to_cpu(header->ucode_array_offset_bytes);
0895     }
0896 
0897     memcpy(ucode->kaddr, ucode_addr, ucode->ucode_size);
0898 
0899     return 0;
0900 }
0901 
0902 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode,
0903                 uint64_t mc_addr, void *kptr)
0904 {
0905     const struct gfx_firmware_header_v1_0 *header = NULL;
0906     const struct common_firmware_header *comm_hdr = NULL;
0907     uint8_t *src_addr = NULL;
0908     uint8_t *dst_addr = NULL;
0909 
0910     if (NULL == ucode->fw)
0911         return 0;
0912 
0913     comm_hdr = (const struct common_firmware_header *)ucode->fw->data;
0914     header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
0915     dst_addr = ucode->kaddr +
0916                ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes),
0917                PAGE_SIZE);
0918     src_addr = (uint8_t *)ucode->fw->data +
0919                le32_to_cpu(comm_hdr->ucode_array_offset_bytes) +
0920                (le32_to_cpu(header->jt_offset) * 4);
0921     memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4);
0922 
0923     return 0;
0924 }
0925 
0926 int amdgpu_ucode_create_bo(struct amdgpu_device *adev)
0927 {
0928     if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) {
0929         amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE,
0930             amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
0931             &adev->firmware.fw_buf,
0932             &adev->firmware.fw_buf_mc,
0933             &adev->firmware.fw_buf_ptr);
0934         if (!adev->firmware.fw_buf) {
0935             dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n");
0936             return -ENOMEM;
0937         } else if (amdgpu_sriov_vf(adev)) {
0938             memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size);
0939         }
0940     }
0941     return 0;
0942 }
0943 
0944 void amdgpu_ucode_free_bo(struct amdgpu_device *adev)
0945 {
0946     amdgpu_bo_free_kernel(&adev->firmware.fw_buf,
0947         &adev->firmware.fw_buf_mc,
0948         &adev->firmware.fw_buf_ptr);
0949 }
0950 
0951 int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
0952 {
0953     uint64_t fw_offset = 0;
0954     int i;
0955     struct amdgpu_firmware_info *ucode = NULL;
0956 
0957  /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */
0958     if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend))
0959         return 0;
0960     /*
0961      * if SMU loaded firmware, it needn't add SMC, UVD, and VCE
0962      * ucode info here
0963      */
0964     if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
0965         if (amdgpu_sriov_vf(adev))
0966             adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3;
0967         else
0968             adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4;
0969     } else {
0970         adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM;
0971     }
0972 
0973     for (i = 0; i < adev->firmware.max_ucodes; i++) {
0974         ucode = &adev->firmware.ucode[i];
0975         if (ucode->fw) {
0976             amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset,
0977                             adev->firmware.fw_buf_ptr + fw_offset);
0978             if (i == AMDGPU_UCODE_ID_CP_MEC1 &&
0979                 adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
0980                 const struct gfx_firmware_header_v1_0 *cp_hdr;
0981                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
0982                 amdgpu_ucode_patch_jt(ucode,  adev->firmware.fw_buf_mc + fw_offset,
0983                             adev->firmware.fw_buf_ptr + fw_offset);
0984                 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE);
0985             }
0986             fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE);
0987         }
0988     }
0989     return 0;
0990 }
0991 
0992 void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len)
0993 {
0994     int maj, min, rev;
0995     char *ip_name;
0996     uint32_t version = adev->ip_versions[block_type][0];
0997 
0998     switch (block_type) {
0999     case GC_HWIP:
1000         ip_name = "gc";
1001         break;
1002     case SDMA0_HWIP:
1003         ip_name = "sdma";
1004         break;
1005     case MP0_HWIP:
1006         ip_name = "psp";
1007         break;
1008     case MP1_HWIP:
1009         ip_name = "smu";
1010         break;
1011     case UVD_HWIP:
1012         ip_name = "vcn";
1013         break;
1014     default:
1015         BUG();
1016     }
1017 
1018     maj = IP_VERSION_MAJ(version);
1019     min = IP_VERSION_MIN(version);
1020     rev = IP_VERSION_REV(version);
1021 
1022     snprintf(ucode_prefix, len, "%s_%d_%d_%d", ip_name, maj, min, rev);
1023 }
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