amd/amdgpu/amdgpu_ttm.h

0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef __AMDGPU_TTM_H__
0025 #define __AMDGPU_TTM_H__
0026
0027 #include <linux/dma-direction.h>
0028 #include <drm/gpu_scheduler.h>
0029 #include "amdgpu_vram_mgr.h"
0030 #include "amdgpu.h"
0031
0032 #define AMDGPU_PL_GDS       (TTM_PL_PRIV + 0)
0033 #define AMDGPU_PL_GWS       (TTM_PL_PRIV + 1)
0034 #define AMDGPU_PL_OA        (TTM_PL_PRIV + 2)
0035 #define AMDGPU_PL_PREEMPT   (TTM_PL_PRIV + 3)
0036
0037 #define AMDGPU_GTT_MAX_TRANSFER_SIZE    512
0038 #define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2
0039
0040 #define AMDGPU_POISON   0xd0bed0be
0041
0042 struct amdgpu_gtt_mgr {
0043     struct ttm_resource_manager manager;
0044     struct drm_mm mm;
0045     spinlock_t lock;
0046 };
0047
0048 struct amdgpu_mman {
0049     struct ttm_device       bdev;
0050     bool                initialized;
0051     void __iomem            *aper_base_kaddr;
0052
0053     /* buffer handling */
0054     const struct amdgpu_buffer_funcs    *buffer_funcs;
0055     struct amdgpu_ring          *buffer_funcs_ring;
0056     bool                    buffer_funcs_enabled;
0057
0058     struct mutex                gtt_window_lock;
0059     /* Scheduler entity for buffer moves */
0060     struct drm_sched_entity         entity;
0061
0062     struct amdgpu_vram_mgr vram_mgr;
0063     struct amdgpu_gtt_mgr gtt_mgr;
0064     struct ttm_resource_manager preempt_mgr;
0065
0066     uint64_t        stolen_vga_size;
0067     struct amdgpu_bo    *stolen_vga_memory;
0068     uint64_t        stolen_extended_size;
0069     struct amdgpu_bo    *stolen_extended_memory;
0070     bool            keep_stolen_vga_memory;
0071
0072     struct amdgpu_bo    *stolen_reserved_memory;
0073     uint64_t        stolen_reserved_offset;
0074     uint64_t        stolen_reserved_size;
0075
0076     /* discovery */
0077     uint8_t             *discovery_bin;
0078     uint32_t            discovery_tmr_size;
0079     struct amdgpu_bo        *discovery_memory;
0080
0081     /* firmware VRAM reservation */
0082     u64     fw_vram_usage_start_offset;
0083     u64     fw_vram_usage_size;
0084     struct amdgpu_bo    *fw_vram_usage_reserved_bo;
0085     void        *fw_vram_usage_va;
0086
0087     /* PAGE_SIZE'd BO for process memory r/w over SDMA. */
0088     struct amdgpu_bo    *sdma_access_bo;
0089     void            *sdma_access_ptr;
0090 };
0091
0092 struct amdgpu_copy_mem {
0093     struct ttm_buffer_object    *bo;
0094     struct ttm_resource     *mem;
0095     unsigned long           offset;
0096 };
0097
0098 int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size);
0099 void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev);
0100 int amdgpu_preempt_mgr_init(struct amdgpu_device *adev);
0101 void amdgpu_preempt_mgr_fini(struct amdgpu_device *adev);
0102 int amdgpu_vram_mgr_init(struct amdgpu_device *adev);
0103 void amdgpu_vram_mgr_fini(struct amdgpu_device *adev);
0104
0105 bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem);
0106 void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr);
0107
0108 uint64_t amdgpu_preempt_mgr_usage(struct ttm_resource_manager *man);
0109
0110 u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo);
0111 int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev,
0112                   struct ttm_resource *mem,
0113                   u64 offset, u64 size,
0114                   struct device *dev,
0115                   enum dma_data_direction dir,
0116                   struct sg_table **sgt);
0117 void amdgpu_vram_mgr_free_sgt(struct device *dev,
0118                   enum dma_data_direction dir,
0119                   struct sg_table *sgt);
0120 uint64_t amdgpu_vram_mgr_vis_usage(struct amdgpu_vram_mgr *mgr);
0121 int amdgpu_vram_mgr_reserve_range(struct amdgpu_vram_mgr *mgr,
0122                   uint64_t start, uint64_t size);
0123 int amdgpu_vram_mgr_query_page_status(struct amdgpu_vram_mgr *mgr,
0124                       uint64_t start);
0125
0126 int amdgpu_ttm_init(struct amdgpu_device *adev);
0127 void amdgpu_ttm_fini(struct amdgpu_device *adev);
0128 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
0129                     bool enable);
0130
0131 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
0132                uint64_t dst_offset, uint32_t byte_count,
0133                struct dma_resv *resv,
0134                struct dma_fence **fence, bool direct_submit,
0135                bool vm_needs_flush, bool tmz);
0136 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
0137                    const struct amdgpu_copy_mem *src,
0138                    const struct amdgpu_copy_mem *dst,
0139                    uint64_t size, bool tmz,
0140                    struct dma_resv *resv,
0141                    struct dma_fence **f);
0142 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
0143             uint32_t src_data,
0144             struct dma_resv *resv,
0145             struct dma_fence **fence);
0146
0147 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
0148 void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
0149 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);
0150
0151 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
0152 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages);
0153 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm);
0154 #else
0155 static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
0156                            struct page **pages)
0157 {
0158     return -EPERM;
0159 }
0160 static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
0161 {
0162     return false;
0163 }
0164 #endif
0165
0166 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages);
0167 int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo,
0168                   uint64_t *user_addr);
0169 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
0170                   uint64_t addr, uint32_t flags);
0171 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
0172 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
0173 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
0174                   unsigned long end, unsigned long *userptr);
0175 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
0176                        int *last_invalidated);
0177 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm);
0178 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
0179 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem);
0180 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
0181                  struct ttm_resource *mem);
0182 int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type);
0183
0184 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
0185
0186 #endif