amd/amdgpu/amdgpu_sync.h

0001 /*
0002  * Copyright 2016 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  * Authors: Christian König
0023  */
0024 #ifndef __AMDGPU_SYNC_H__
0025 #define __AMDGPU_SYNC_H__
0026
0027 #include <linux/hashtable.h>
0028
0029 struct dma_fence;
0030 struct dma_resv;
0031 struct amdgpu_device;
0032 struct amdgpu_ring;
0033
0034 enum amdgpu_sync_mode {
0035     AMDGPU_SYNC_ALWAYS,
0036     AMDGPU_SYNC_NE_OWNER,
0037     AMDGPU_SYNC_EQ_OWNER,
0038     AMDGPU_SYNC_EXPLICIT
0039 };
0040
0041 /*
0042  * Container for fences used to sync command submissions.
0043  */
0044 struct amdgpu_sync {
0045     DECLARE_HASHTABLE(fences, 4);
0046 };
0047
0048 void amdgpu_sync_create(struct amdgpu_sync *sync);
0049 int amdgpu_sync_fence(struct amdgpu_sync *sync, struct dma_fence *f);
0050 int amdgpu_sync_resv(struct amdgpu_device *adev, struct amdgpu_sync *sync,
0051              struct dma_resv *resv, enum amdgpu_sync_mode mode,
0052              void *owner);
0053 struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
0054                      struct amdgpu_ring *ring);
0055 struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
0056 int amdgpu_sync_clone(struct amdgpu_sync *source, struct amdgpu_sync *clone);
0057 int amdgpu_sync_wait(struct amdgpu_sync *sync, bool intr);
0058 void amdgpu_sync_free(struct amdgpu_sync *sync);
0059 int amdgpu_sync_init(void);
0060 void amdgpu_sync_fini(void);
0061
0062 #endif