amd/amdgpu/amdgpu_socbb.h

0001 /*
0002  * Copyright 2019 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 #ifndef __AMDGPU_SOCBB_H__
0024 #define __AMDGPU_SOCBB_H__
0025
0026 struct gpu_info_voltage_scaling_v1_0 {
0027     uint32_t state;
0028     uint32_t dscclk_mhz;
0029     uint32_t dcfclk_mhz;
0030     uint32_t socclk_mhz;
0031     uint32_t dram_speed_mts;
0032     uint32_t fabricclk_mhz;
0033     uint32_t dispclk_mhz;
0034     uint32_t phyclk_mhz;
0035     uint32_t dppclk_mhz;
0036 };
0037
0038 struct gpu_info_soc_bounding_box_v1_0 {
0039     uint32_t sr_exit_time_us;
0040     uint32_t sr_enter_plus_exit_time_us;
0041     uint32_t urgent_latency_us;
0042     uint32_t urgent_latency_pixel_data_only_us;
0043     uint32_t urgent_latency_pixel_mixed_with_vm_data_us;
0044     uint32_t urgent_latency_vm_data_only_us;
0045     uint32_t writeback_latency_us;
0046     uint32_t ideal_dram_bw_after_urgent_percent;
0047     uint32_t pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly
0048     uint32_t pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
0049     uint32_t pct_ideal_dram_sdp_bw_after_urgent_vm_only;
0050     uint32_t max_avg_sdp_bw_use_normal_percent;
0051     uint32_t max_avg_dram_bw_use_normal_percent;
0052     uint32_t max_request_size_bytes;
0053     uint32_t downspread_percent;
0054     uint32_t dram_page_open_time_ns;
0055     uint32_t dram_rw_turnaround_time_ns;
0056     uint32_t dram_return_buffer_per_channel_bytes;
0057     uint32_t dram_channel_width_bytes;
0058     uint32_t fabric_datapath_to_dcn_data_return_bytes;
0059     uint32_t dcn_downspread_percent;
0060     uint32_t dispclk_dppclk_vco_speed_mhz;
0061     uint32_t dfs_vco_period_ps;
0062     uint32_t urgent_out_of_order_return_per_channel_pixel_only_bytes;
0063     uint32_t urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
0064     uint32_t urgent_out_of_order_return_per_channel_vm_only_bytes;
0065     uint32_t round_trip_ping_latency_dcfclk_cycles;
0066     uint32_t urgent_out_of_order_return_per_channel_bytes;
0067     uint32_t channel_interleave_bytes;
0068     uint32_t num_banks;
0069     uint32_t num_chans;
0070     uint32_t vmm_page_size_bytes;
0071     uint32_t dram_clock_change_latency_us;
0072     uint32_t writeback_dram_clock_change_latency_us;
0073     uint32_t return_bus_width_bytes;
0074     uint32_t voltage_override;
0075     uint32_t xfc_bus_transport_time_us;
0076     uint32_t xfc_xbuf_latency_tolerance_us;
0077     uint32_t use_urgent_burst_bw;
0078     uint32_t num_states;
0079     struct gpu_info_voltage_scaling_v1_0 clock_limits[8];
0080 };
0081
0082 #endif