amd/amdgpu/amdgpu_sdma.h

0001 /*
0002  * Copyright 2018 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef __AMDGPU_SDMA_H__
0025 #define __AMDGPU_SDMA_H__
0026 #include "amdgpu_ras.h"
0027
0028 /* max number of IP instances */
0029 #define AMDGPU_MAX_SDMA_INSTANCES       8
0030
0031 enum amdgpu_sdma_irq {
0032     AMDGPU_SDMA_IRQ_INSTANCE0  = 0,
0033     AMDGPU_SDMA_IRQ_INSTANCE1,
0034     AMDGPU_SDMA_IRQ_INSTANCE2,
0035     AMDGPU_SDMA_IRQ_INSTANCE3,
0036     AMDGPU_SDMA_IRQ_INSTANCE4,
0037     AMDGPU_SDMA_IRQ_INSTANCE5,
0038     AMDGPU_SDMA_IRQ_INSTANCE6,
0039     AMDGPU_SDMA_IRQ_INSTANCE7,
0040     AMDGPU_SDMA_IRQ_LAST
0041 };
0042
0043 struct amdgpu_sdma_instance {
0044     /* SDMA firmware */
0045     const struct firmware   *fw;
0046     uint32_t        fw_version;
0047     uint32_t        feature_version;
0048
0049     struct amdgpu_ring  ring;
0050     struct amdgpu_ring  page;
0051     bool            burst_nop;
0052 };
0053
0054 struct amdgpu_sdma_ras {
0055     struct amdgpu_ras_block_object ras_block;
0056 };
0057
0058 struct amdgpu_sdma {
0059     struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
0060     struct amdgpu_irq_src   trap_irq;
0061     struct amdgpu_irq_src   illegal_inst_irq;
0062     struct amdgpu_irq_src   ecc_irq;
0063     struct amdgpu_irq_src   vm_hole_irq;
0064     struct amdgpu_irq_src   doorbell_invalid_irq;
0065     struct amdgpu_irq_src   pool_timeout_irq;
0066     struct amdgpu_irq_src   srbm_write_irq;
0067
0068     int         num_instances;
0069     uint32_t                    srbm_soft_reset;
0070     bool            has_page_queue;
0071     struct ras_common_if    *ras_if;
0072     struct amdgpu_sdma_ras  *ras;
0073 };
0074
0075 /*
0076  * Provided by hw blocks that can move/clear data.  e.g., gfx or sdma
0077  * But currently, we use sdma to move data.
0078  */
0079 struct amdgpu_buffer_funcs {
0080     /* maximum bytes in a single operation */
0081     uint32_t    copy_max_bytes;
0082
0083     /* number of dw to reserve per operation */
0084     unsigned    copy_num_dw;
0085
0086     /* used for buffer migration */
0087     void (*emit_copy_buffer)(struct amdgpu_ib *ib,
0088                  /* src addr in bytes */
0089                  uint64_t src_offset,
0090                  /* dst addr in bytes */
0091                  uint64_t dst_offset,
0092                  /* number of byte to transfer */
0093                  uint32_t byte_count,
0094                  bool tmz);
0095
0096     /* maximum bytes in a single operation */
0097     uint32_t    fill_max_bytes;
0098
0099     /* number of dw to reserve per operation */
0100     unsigned    fill_num_dw;
0101
0102     /* used for buffer clearing */
0103     void (*emit_fill_buffer)(struct amdgpu_ib *ib,
0104                  /* value to write to memory */
0105                  uint32_t src_data,
0106                  /* dst addr in bytes */
0107                  uint64_t dst_offset,
0108                  /* number of byte to fill */
0109                  uint32_t byte_count);
0110 };
0111
0112 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t) (adev)->mman.buffer_funcs->emit_copy_buffer((ib),  (s), (d), (b), (t))
0113 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
0114
0115 struct amdgpu_sdma_instance *
0116 amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring);
0117 int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
0118 uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
0119 int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
0120                   struct ras_common_if *ras_block);
0121 int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
0122         void *err_data,
0123         struct amdgpu_iv_entry *entry);
0124 int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev,
0125                       struct amdgpu_irq_src *source,
0126                       struct amdgpu_iv_entry *entry);
0127 #endif