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0001 /*
0002  * Copyright 2014 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023 
0024 #ifndef __AMDGPU_RLC_H__
0025 #define __AMDGPU_RLC_H__
0026 
0027 #include "clearstate_defs.h"
0028 
0029 /* firmware ID used in rlc toc */
0030 typedef enum _FIRMWARE_ID_ {
0031     FIRMWARE_ID_INVALID                 = 0,
0032     FIRMWARE_ID_RLC_G_UCODE                 = 1,
0033     FIRMWARE_ID_RLC_TOC                 = 2,
0034     FIRMWARE_ID_RLCG_SCRATCH                                = 3,
0035     FIRMWARE_ID_RLC_SRM_ARAM                                = 4,
0036     FIRMWARE_ID_RLC_SRM_INDEX_ADDR                          = 5,
0037     FIRMWARE_ID_RLC_SRM_INDEX_DATA                          = 6,
0038     FIRMWARE_ID_RLC_P_UCODE                                 = 7,
0039     FIRMWARE_ID_RLC_V_UCODE                                 = 8,
0040     FIRMWARE_ID_RLX6_UCODE                                  = 9,
0041     FIRMWARE_ID_RLX6_DRAM_BOOT                              = 10,
0042     FIRMWARE_ID_GLOBAL_TAP_DELAYS                           = 11,
0043     FIRMWARE_ID_SE0_TAP_DELAYS                              = 12,
0044     FIRMWARE_ID_SE1_TAP_DELAYS                              = 13,
0045     FIRMWARE_ID_GLOBAL_SE0_SE1_SKEW_DELAYS                  = 14,
0046     FIRMWARE_ID_SDMA0_UCODE                                 = 15,
0047     FIRMWARE_ID_SDMA0_JT                                    = 16,
0048     FIRMWARE_ID_SDMA1_UCODE                                 = 17,
0049     FIRMWARE_ID_SDMA1_JT                                    = 18,
0050     FIRMWARE_ID_CP_CE                                       = 19,
0051     FIRMWARE_ID_CP_PFP                                      = 20,
0052     FIRMWARE_ID_CP_ME                                       = 21,
0053     FIRMWARE_ID_CP_MEC                                      = 22,
0054     FIRMWARE_ID_CP_MES                                      = 23,
0055     FIRMWARE_ID_MES_STACK                                   = 24,
0056     FIRMWARE_ID_RLC_SRM_DRAM_SR                             = 25,
0057     FIRMWARE_ID_RLCG_SCRATCH_SR                             = 26,
0058     FIRMWARE_ID_RLCP_SCRATCH_SR                             = 27,
0059     FIRMWARE_ID_RLCV_SCRATCH_SR                             = 28,
0060     FIRMWARE_ID_RLX6_DRAM_SR                                = 29,
0061     FIRMWARE_ID_SDMA0_PG_CONTEXT                            = 30,
0062     FIRMWARE_ID_SDMA1_PG_CONTEXT                            = 31,
0063     FIRMWARE_ID_GLOBAL_MUX_SELECT_RAM                       = 32,
0064     FIRMWARE_ID_SE0_MUX_SELECT_RAM                          = 33,
0065     FIRMWARE_ID_SE1_MUX_SELECT_RAM                          = 34,
0066     FIRMWARE_ID_ACCUM_CTRL_RAM                              = 35,
0067     FIRMWARE_ID_RLCP_CAM                                    = 36,
0068     FIRMWARE_ID_RLC_SPP_CAM_EXT                             = 37,
0069     FIRMWARE_ID_MAX                                         = 38,
0070 } FIRMWARE_ID;
0071 
0072 typedef enum _SOC21_FIRMWARE_ID_ {
0073     SOC21_FIRMWARE_ID_INVALID                     = 0,
0074     SOC21_FIRMWARE_ID_RLC_G_UCODE                 = 1,
0075     SOC21_FIRMWARE_ID_RLC_TOC                     = 2,
0076     SOC21_FIRMWARE_ID_RLCG_SCRATCH                = 3,
0077     SOC21_FIRMWARE_ID_RLC_SRM_ARAM                = 4,
0078     SOC21_FIRMWARE_ID_RLC_P_UCODE                 = 5,
0079     SOC21_FIRMWARE_ID_RLC_V_UCODE                 = 6,
0080     SOC21_FIRMWARE_ID_RLX6_UCODE                  = 7,
0081     SOC21_FIRMWARE_ID_RLX6_UCODE_CORE1            = 8,
0082     SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT              = 9,
0083     SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT_CORE1        = 10,
0084     SOC21_FIRMWARE_ID_SDMA_UCODE_TH0              = 11,
0085     SOC21_FIRMWARE_ID_SDMA_UCODE_TH1              = 12,
0086     SOC21_FIRMWARE_ID_CP_PFP                      = 13,
0087     SOC21_FIRMWARE_ID_CP_ME                       = 14,
0088     SOC21_FIRMWARE_ID_CP_MEC                      = 15,
0089     SOC21_FIRMWARE_ID_RS64_MES_P0                 = 16,
0090     SOC21_FIRMWARE_ID_RS64_MES_P1                 = 17,
0091     SOC21_FIRMWARE_ID_RS64_PFP                    = 18,
0092     SOC21_FIRMWARE_ID_RS64_ME                     = 19,
0093     SOC21_FIRMWARE_ID_RS64_MEC                    = 20,
0094     SOC21_FIRMWARE_ID_RS64_MES_P0_STACK           = 21,
0095     SOC21_FIRMWARE_ID_RS64_MES_P1_STACK           = 22,
0096     SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK           = 23,
0097     SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK           = 24,
0098     SOC21_FIRMWARE_ID_RS64_ME_P0_STACK            = 25,
0099     SOC21_FIRMWARE_ID_RS64_ME_P1_STACK            = 26,
0100     SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK           = 27,
0101     SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK           = 28,
0102     SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK           = 29,
0103     SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK           = 30,
0104     SOC21_FIRMWARE_ID_RLC_SRM_DRAM_SR             = 31,
0105     SOC21_FIRMWARE_ID_RLCG_SCRATCH_SR             = 32,
0106     SOC21_FIRMWARE_ID_RLCP_SCRATCH_SR             = 33,
0107     SOC21_FIRMWARE_ID_RLCV_SCRATCH_SR             = 34,
0108     SOC21_FIRMWARE_ID_RLX6_DRAM_SR                = 35,
0109     SOC21_FIRMWARE_ID_RLX6_DRAM_SR_CORE1          = 36,
0110     SOC21_FIRMWARE_ID_MAX                         = 37
0111 } SOC21_FIRMWARE_ID;
0112 
0113 typedef struct _RLC_TABLE_OF_CONTENT {
0114     union {
0115         unsigned int    DW0;
0116         struct {
0117             unsigned int    offset      : 25;
0118             unsigned int    id      : 7;
0119         };
0120     };
0121 
0122     union {
0123         unsigned int    DW1;
0124         struct {
0125             unsigned int    load_at_boot        : 1;
0126             unsigned int    load_at_vddgfx      : 1;
0127             unsigned int    load_at_reset       : 1;
0128             unsigned int    memory_destination  : 2;
0129             unsigned int    vfflr_image_code    : 4;
0130             unsigned int    load_mode_direct    : 1;
0131             unsigned int    save_for_vddgfx     : 1;
0132             unsigned int    save_for_vfflr      : 1;
0133             unsigned int    reserved        : 1;
0134             unsigned int    signed_source       : 1;
0135             unsigned int    size            : 18;
0136         };
0137     };
0138 
0139     union {
0140         unsigned int    DW2;
0141         struct {
0142             unsigned int    indirect_addr_reg   : 16;
0143             unsigned int    index           : 16;
0144         };
0145     };
0146 
0147     union {
0148         unsigned int    DW3;
0149         struct {
0150             unsigned int    indirect_data_reg   : 16;
0151             unsigned int    indirect_start_offset   : 16;
0152         };
0153     };
0154 } RLC_TABLE_OF_CONTENT;
0155 
0156 #define RLC_TOC_MAX_SIZE        64
0157 
0158 struct amdgpu_rlc_funcs {
0159     bool (*is_rlc_enabled)(struct amdgpu_device *adev);
0160     void (*set_safe_mode)(struct amdgpu_device *adev);
0161     void (*unset_safe_mode)(struct amdgpu_device *adev);
0162     int  (*init)(struct amdgpu_device *adev);
0163     u32  (*get_csb_size)(struct amdgpu_device *adev);
0164     void (*get_csb_buffer)(struct amdgpu_device *adev, volatile u32 *buffer);
0165     int  (*get_cp_table_num)(struct amdgpu_device *adev);
0166     int  (*resume)(struct amdgpu_device *adev);
0167     void (*stop)(struct amdgpu_device *adev);
0168     void (*reset)(struct amdgpu_device *adev);
0169     void (*start)(struct amdgpu_device *adev);
0170     void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned vmid);
0171     bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg);
0172 };
0173 
0174 struct amdgpu_rlcg_reg_access_ctrl {
0175     uint32_t scratch_reg0;
0176     uint32_t scratch_reg1;
0177     uint32_t scratch_reg2;
0178     uint32_t scratch_reg3;
0179     uint32_t grbm_cntl;
0180     uint32_t grbm_idx;
0181     uint32_t spare_int;
0182 };
0183 
0184 struct amdgpu_rlc {
0185     /* for power gating */
0186     struct amdgpu_bo        *save_restore_obj;
0187     uint64_t                save_restore_gpu_addr;
0188     volatile uint32_t       *sr_ptr;
0189     const u32               *reg_list;
0190     u32                     reg_list_size;
0191     /* for clear state */
0192     struct amdgpu_bo        *clear_state_obj;
0193     uint64_t                clear_state_gpu_addr;
0194     volatile uint32_t       *cs_ptr;
0195     const struct cs_section_def   *cs_data;
0196     u32                     clear_state_size;
0197     /* for cp tables */
0198     struct amdgpu_bo        *cp_table_obj;
0199     uint64_t                cp_table_gpu_addr;
0200     volatile uint32_t       *cp_table_ptr;
0201     u32                     cp_table_size;
0202 
0203     /* safe mode for updating CG/PG state */
0204     bool in_safe_mode;
0205     const struct amdgpu_rlc_funcs *funcs;
0206 
0207     /* for firmware data */
0208     u32 save_and_restore_offset;
0209     u32 clear_state_descriptor_offset;
0210     u32 avail_scratch_ram_locations;
0211     u32 reg_restore_list_size;
0212     u32 reg_list_format_start;
0213     u32 reg_list_format_separate_start;
0214     u32 starting_offsets_start;
0215     u32 reg_list_format_size_bytes;
0216     u32 reg_list_size_bytes;
0217     u32 reg_list_format_direct_reg_list_length;
0218     u32 save_restore_list_cntl_size_bytes;
0219     u32 save_restore_list_gpm_size_bytes;
0220     u32 save_restore_list_srm_size_bytes;
0221     u32 rlc_iram_ucode_size_bytes;
0222     u32 rlc_dram_ucode_size_bytes;
0223     u32 rlcp_ucode_size_bytes;
0224     u32 rlcv_ucode_size_bytes;
0225     u32 global_tap_delays_ucode_size_bytes;
0226     u32 se0_tap_delays_ucode_size_bytes;
0227     u32 se1_tap_delays_ucode_size_bytes;
0228     u32 se2_tap_delays_ucode_size_bytes;
0229     u32 se3_tap_delays_ucode_size_bytes;
0230 
0231     u32 *register_list_format;
0232     u32 *register_restore;
0233     u8 *save_restore_list_cntl;
0234     u8 *save_restore_list_gpm;
0235     u8 *save_restore_list_srm;
0236     u8 *rlc_iram_ucode;
0237     u8 *rlc_dram_ucode;
0238     u8 *rlcp_ucode;
0239     u8 *rlcv_ucode;
0240     u8 *global_tap_delays_ucode;
0241     u8 *se0_tap_delays_ucode;
0242     u8 *se1_tap_delays_ucode;
0243     u8 *se2_tap_delays_ucode;
0244     u8 *se3_tap_delays_ucode;
0245 
0246     bool is_rlc_v2_1;
0247 
0248     /* for rlc autoload */
0249     struct amdgpu_bo    *rlc_autoload_bo;
0250     u64         rlc_autoload_gpu_addr;
0251     void            *rlc_autoload_ptr;
0252 
0253     /* rlc toc buffer */
0254     struct amdgpu_bo    *rlc_toc_bo;
0255     uint64_t        rlc_toc_gpu_addr;
0256     void            *rlc_toc_buf;
0257 
0258     bool rlcg_reg_access_supported;
0259     /* registers for rlcg indirect reg access */
0260     struct amdgpu_rlcg_reg_access_ctrl reg_access_ctrl;
0261 };
0262 
0263 void amdgpu_gfx_rlc_enter_safe_mode(struct amdgpu_device *adev);
0264 void amdgpu_gfx_rlc_exit_safe_mode(struct amdgpu_device *adev);
0265 int amdgpu_gfx_rlc_init_sr(struct amdgpu_device *adev, u32 dws);
0266 int amdgpu_gfx_rlc_init_csb(struct amdgpu_device *adev);
0267 int amdgpu_gfx_rlc_init_cpt(struct amdgpu_device *adev);
0268 void amdgpu_gfx_rlc_setup_cp_table(struct amdgpu_device *adev);
0269 void amdgpu_gfx_rlc_fini(struct amdgpu_device *adev);
0270 int amdgpu_gfx_rlc_init_microcode(struct amdgpu_device *adev,
0271                   uint16_t version_major,
0272                   uint16_t version_minor);
0273 #endif
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