amd/amdgpu/amdgpu_reset.h

0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #ifndef __AMDGPU_RESET_H__
0025 #define __AMDGPU_RESET_H__
0026
0027 #include "amdgpu.h"
0028
0029 enum AMDGPU_RESET_FLAGS {
0030
0031     AMDGPU_NEED_FULL_RESET = 0,
0032     AMDGPU_SKIP_HW_RESET = 1,
0033 };
0034
0035 struct amdgpu_reset_context {
0036     enum amd_reset_method method;
0037     struct amdgpu_device *reset_req_dev;
0038     struct amdgpu_job *job;
0039     struct amdgpu_hive_info *hive;
0040     struct list_head *reset_device_list;
0041     unsigned long flags;
0042 };
0043
0044 struct amdgpu_reset_handler {
0045     enum amd_reset_method reset_method;
0046     struct list_head handler_list;
0047     int (*prepare_env)(struct amdgpu_reset_control *reset_ctl,
0048                struct amdgpu_reset_context *context);
0049     int (*prepare_hwcontext)(struct amdgpu_reset_control *reset_ctl,
0050                  struct amdgpu_reset_context *context);
0051     int (*perform_reset)(struct amdgpu_reset_control *reset_ctl,
0052                  struct amdgpu_reset_context *context);
0053     int (*restore_hwcontext)(struct amdgpu_reset_control *reset_ctl,
0054                  struct amdgpu_reset_context *context);
0055     int (*restore_env)(struct amdgpu_reset_control *reset_ctl,
0056                struct amdgpu_reset_context *context);
0057
0058     int (*do_reset)(struct amdgpu_device *adev);
0059 };
0060
0061 struct amdgpu_reset_control {
0062     void *handle;
0063     struct work_struct reset_work;
0064     struct mutex reset_lock;
0065     struct list_head reset_handlers;
0066     atomic_t in_reset;
0067     enum amd_reset_method active_reset;
0068     struct amdgpu_reset_handler *(*get_reset_handler)(
0069         struct amdgpu_reset_control *reset_ctl,
0070         struct amdgpu_reset_context *context);
0071     void (*async_reset)(struct work_struct *work);
0072 };
0073
0074
0075 enum amdgpu_reset_domain_type {
0076     SINGLE_DEVICE,
0077     XGMI_HIVE
0078 };
0079
0080 struct amdgpu_reset_domain {
0081     struct kref refcount;
0082     struct workqueue_struct *wq;
0083     enum amdgpu_reset_domain_type type;
0084     struct rw_semaphore sem;
0085     atomic_t in_gpu_reset;
0086     atomic_t reset_res;
0087 };
0088
0089
0090 int amdgpu_reset_init(struct amdgpu_device *adev);
0091 int amdgpu_reset_fini(struct amdgpu_device *adev);
0092
0093 int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev,
0094                    struct amdgpu_reset_context *reset_context);
0095
0096 int amdgpu_reset_perform_reset(struct amdgpu_device *adev,
0097                    struct amdgpu_reset_context *reset_context);
0098
0099 int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl,
0100                  struct amdgpu_reset_handler *handler);
0101
0102 struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_domain_type type,
0103                                  char *wq_name);
0104
0105 void amdgpu_reset_destroy_reset_domain(struct kref *ref);
0106
0107 static inline bool amdgpu_reset_get_reset_domain(struct amdgpu_reset_domain *domain)
0108 {
0109     return kref_get_unless_zero(&domain->refcount) != 0;
0110 }
0111
0112 static inline void amdgpu_reset_put_reset_domain(struct amdgpu_reset_domain *domain)
0113 {
0114     kref_put(&domain->refcount, amdgpu_reset_destroy_reset_domain);
0115 }
0116
0117 static inline bool amdgpu_reset_domain_schedule(struct amdgpu_reset_domain *domain,
0118                         struct work_struct *work)
0119 {
0120     return queue_work(domain->wq, work);
0121 }
0122
0123 void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain);
0124
0125 void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain);
0126
0127 #endif