amd/amdgpu/amdgpu_reset.c

0001 /*
0002  * Copyright 2021 Advanced Micro Devices, Inc.
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice shall be included in
0012  * all copies or substantial portions of the Software.
0013  *
0014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0017  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
0018  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0019  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0020  * OTHER DEALINGS IN THE SOFTWARE.
0021  *
0022  */
0023
0024 #include "amdgpu_reset.h"
0025 #include "aldebaran.h"
0026
0027 int amdgpu_reset_add_handler(struct amdgpu_reset_control *reset_ctl,
0028                  struct amdgpu_reset_handler *handler)
0029 {
0030     /* TODO: Check if handler exists? */
0031     list_add_tail(&handler->handler_list, &reset_ctl->reset_handlers);
0032     return 0;
0033 }
0034
0035 int amdgpu_reset_init(struct amdgpu_device *adev)
0036 {
0037     int ret = 0;
0038
0039     switch (adev->ip_versions[MP1_HWIP][0]) {
0040     case IP_VERSION(13, 0, 2):
0041         ret = aldebaran_reset_init(adev);
0042         break;
0043     default:
0044         break;
0045     }
0046
0047     return ret;
0048 }
0049
0050 int amdgpu_reset_fini(struct amdgpu_device *adev)
0051 {
0052     int ret = 0;
0053
0054     switch (adev->ip_versions[MP1_HWIP][0]) {
0055     case IP_VERSION(13, 0, 2):
0056         ret = aldebaran_reset_fini(adev);
0057         break;
0058     default:
0059         break;
0060     }
0061
0062     return ret;
0063 }
0064
0065 int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev,
0066                    struct amdgpu_reset_context *reset_context)
0067 {
0068     struct amdgpu_reset_handler *reset_handler = NULL;
0069
0070     if (adev->reset_cntl && adev->reset_cntl->get_reset_handler)
0071         reset_handler = adev->reset_cntl->get_reset_handler(
0072             adev->reset_cntl, reset_context);
0073     if (!reset_handler)
0074         return -ENOSYS;
0075
0076     return reset_handler->prepare_hwcontext(adev->reset_cntl,
0077                         reset_context);
0078 }
0079
0080 int amdgpu_reset_perform_reset(struct amdgpu_device *adev,
0081                    struct amdgpu_reset_context *reset_context)
0082 {
0083     int ret;
0084     struct amdgpu_reset_handler *reset_handler = NULL;
0085
0086     if (adev->reset_cntl)
0087         reset_handler = adev->reset_cntl->get_reset_handler(
0088             adev->reset_cntl, reset_context);
0089     if (!reset_handler)
0090         return -ENOSYS;
0091
0092     ret = reset_handler->perform_reset(adev->reset_cntl, reset_context);
0093     if (ret)
0094         return ret;
0095
0096     return reset_handler->restore_hwcontext(adev->reset_cntl,
0097                         reset_context);
0098 }
0099
0100
0101 void amdgpu_reset_destroy_reset_domain(struct kref *ref)
0102 {
0103     struct amdgpu_reset_domain *reset_domain = container_of(ref,
0104                                 struct amdgpu_reset_domain,
0105                                 refcount);
0106     if (reset_domain->wq)
0107         destroy_workqueue(reset_domain->wq);
0108
0109     kvfree(reset_domain);
0110 }
0111
0112 struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_domain_type type,
0113                                  char *wq_name)
0114 {
0115     struct amdgpu_reset_domain *reset_domain;
0116
0117     reset_domain = kvzalloc(sizeof(struct amdgpu_reset_domain), GFP_KERNEL);
0118     if (!reset_domain) {
0119         DRM_ERROR("Failed to allocate amdgpu_reset_domain!");
0120         return NULL;
0121     }
0122
0123     reset_domain->type = type;
0124     kref_init(&reset_domain->refcount);
0125
0126     reset_domain->wq = create_singlethread_workqueue(wq_name);
0127     if (!reset_domain->wq) {
0128         DRM_ERROR("Failed to allocate wq for amdgpu_reset_domain!");
0129         amdgpu_reset_put_reset_domain(reset_domain);
0130         return NULL;
0131
0132     }
0133
0134     atomic_set(&reset_domain->in_gpu_reset, 0);
0135     atomic_set(&reset_domain->reset_res, 0);
0136     init_rwsem(&reset_domain->sem);
0137
0138     return reset_domain;
0139 }
0140
0141 void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain)
0142 {
0143     atomic_set(&reset_domain->in_gpu_reset, 1);
0144     down_write(&reset_domain->sem);
0145 }
0146
0147
0148 void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain)
0149 {
0150     atomic_set(&reset_domain->in_gpu_reset, 0);
0151     up_write(&reset_domain->sem);
0152 }
0153
0154
0155